DE69331677D1 - Halbleiter-Speicherbauteil und Verfahren zu seiner Herstellung - Google Patents

Halbleiter-Speicherbauteil und Verfahren zu seiner Herstellung

Info

Publication number
DE69331677D1
DE69331677D1 DE69331677T DE69331677T DE69331677D1 DE 69331677 D1 DE69331677 D1 DE 69331677D1 DE 69331677 T DE69331677 T DE 69331677T DE 69331677 T DE69331677 T DE 69331677T DE 69331677 D1 DE69331677 D1 DE 69331677D1
Authority
DE
Germany
Prior art keywords
manufacture
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69331677T
Other languages
English (en)
Other versions
DE69331677T2 (de
Inventor
Han-Soo Kim
Kyung-Tae Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE69331677D1 publication Critical patent/DE69331677D1/de
Publication of DE69331677T2 publication Critical patent/DE69331677T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
DE69331677T 1992-10-12 1993-10-12 Halbleiter-Speicherbauteil und Verfahren zu seiner Herstellung Expired - Lifetime DE69331677T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018694A KR970001346B1 (ko) 1992-10-12 1992-10-12 반도체 메모리장치 및 그 제조방법

Publications (2)

Publication Number Publication Date
DE69331677D1 true DE69331677D1 (de) 2002-04-18
DE69331677T2 DE69331677T2 (de) 2002-09-12

Family

ID=19340984

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69331677T Expired - Lifetime DE69331677T2 (de) 1992-10-12 1993-10-12 Halbleiter-Speicherbauteil und Verfahren zu seiner Herstellung

Country Status (7)

Country Link
US (1) US5436506A (de)
EP (1) EP0593247B1 (de)
JP (1) JP3623806B2 (de)
KR (1) KR970001346B1 (de)
CN (1) CN1034896C (de)
DE (1) DE69331677T2 (de)
TW (1) TW359898B (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3086757B2 (ja) * 1992-09-28 2000-09-11 三菱電機株式会社 スタティックランダムアクセスメモリ
JP3285438B2 (ja) * 1993-10-29 2002-05-27 三菱電機株式会社 半導体記憶装置
KR0135801B1 (ko) * 1994-07-26 1998-04-24 김광호 스태틱 랜덤 억세스 메모리소자 및 그 제조방법
US5489797A (en) * 1994-12-19 1996-02-06 Sgs-Thomson Microelectronics, Inc. Local interconnect structure
JP3570052B2 (ja) * 1995-01-19 2004-09-29 セイコーエプソン株式会社 半導体メモリ装置及びその製造方法
JP3428240B2 (ja) * 1995-07-31 2003-07-22 三菱電機株式会社 半導体記憶装置
JP3523746B2 (ja) * 1996-03-14 2004-04-26 株式会社東芝 半導体記憶装置の製造方法
DE19781675B4 (de) * 1996-03-28 2006-08-24 Intel Corporation, Santa Clara Speicherzellengestaltung mit vertikal gestapelten Überkeuzungen
US5847442A (en) * 1996-11-12 1998-12-08 Lucent Technologies Inc. Structure for read-only-memory
JP3179368B2 (ja) * 1997-05-30 2001-06-25 広島日本電気株式会社 スタティック型メモリセル
JP3134927B2 (ja) * 1998-05-01 2001-02-13 日本電気株式会社 半導体装置及びｓｒａｍセルの製造方法
JP3852729B2 (ja) * 1998-10-27 2006-12-06 富士通株式会社 半導体記憶装置
JP3768504B2 (ja) * 2002-04-10 2006-04-19 松下電器産業株式会社 不揮発性フリップフロップ
US6919647B2 (en) * 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7019342B2 (en) 2003-07-03 2006-03-28 American Semiconductor, Inc. Double-gated transistor circuit
US7015547B2 (en) * 2003-07-03 2006-03-21 American Semiconductor, Inc. Multi-configurable independently multi-gated MOSFET
JP2007234073A (ja) * 2006-02-27 2007-09-13 Fujitsu Ltd 半導体記憶装置
JP5054803B2 (ja) * 2010-05-26 2012-10-24 シャープ株式会社 半導体記憶装置
US8530960B2 (en) * 2010-12-07 2013-09-10 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4125854A (en) * 1976-12-02 1978-11-14 Mostek Corporation Symmetrical cell layout for static RAM
JPS58165375A (ja) * 1982-03-03 1983-09-30 Fujitsu Ltd 半導体記憶装置
US4725875A (en) * 1985-10-01 1988-02-16 General Electric Co. Memory cell with diodes providing radiation hardness
JPS62169472A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 半導体集積回路装置
JPS63296264A (ja) * 1988-05-02 1988-12-02 Hitachi Ltd スタティックｒａｍ
JPH0770624B2 (ja) * 1990-06-22 1995-07-31 株式会社東芝 半導体集積回路

Also Published As

Publication number Publication date
EP0593247B1 (de) 2002-03-13
EP0593247A2 (de) 1994-04-20
CN1034896C (zh) 1997-05-14
CN1086048A (zh) 1994-04-27
DE69331677T2 (de) 2002-09-12
US5436506A (en) 1995-07-25
TW359898B (en) 1999-06-01
JPH06204433A (ja) 1994-07-22
KR940010348A (ko) 1994-05-26
KR970001346B1 (ko) 1997-02-05
EP0593247A3 (de) 1995-04-19
JP3623806B2 (ja) 2005-02-23

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Legal Events

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