DE69416619D1 - Halbleiterspeicheranordnung und Verfahren zur Herstellung - Google Patents

Halbleiterspeicheranordnung und Verfahren zur Herstellung

Info

Publication number
DE69416619D1
DE69416619D1 DE69416619T DE69416619T DE69416619D1 DE 69416619 D1 DE69416619 D1 DE 69416619D1 DE 69416619 T DE69416619 T DE 69416619T DE 69416619 T DE69416619 T DE 69416619T DE 69416619 D1 DE69416619 D1 DE 69416619D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69416619T
Other languages
English (en)
Other versions
DE69416619T2 (de
Inventor
Jun-Ichi Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tohoku University NUC
Original Assignee
Zaidan Hojin Handotai Kenkyu Shinkokai
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zaidan Hojin Handotai Kenkyu Shinkokai filed Critical Zaidan Hojin Handotai Kenkyu Shinkokai
Publication of DE69416619D1 publication Critical patent/DE69416619D1/de
Application granted granted Critical
Publication of DE69416619T2 publication Critical patent/DE69416619T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8616Charge trapping diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Non-Volatile Memory (AREA)
DE69416619T 1993-05-12 1994-05-10 Halbleiterspeicheranordnung und Verfahren zur Herstellung Expired - Fee Related DE69416619T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14712893 1993-05-12

Publications (2)

Publication Number Publication Date
DE69416619D1 true DE69416619D1 (de) 1999-04-01
DE69416619T2 DE69416619T2 (de) 1999-09-30

Family

ID=15423194

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69416619T Expired - Fee Related DE69416619T2 (de) 1993-05-12 1994-05-10 Halbleiterspeicheranordnung und Verfahren zur Herstellung

Country Status (5)

Country Link
US (1) US5485017A (de)
EP (1) EP0631326B1 (de)
KR (1) KR0157662B1 (de)
DE (1) DE69416619T2 (de)
TW (1) TW241381B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69610017D1 (de) * 1995-05-25 2000-10-05 Matsushita Electric Ind Co Ltd Nichtlineares Element und bistabile Speicheranordnung
JP3397516B2 (ja) * 1995-06-08 2003-04-14 三菱電機株式会社 半導体記憶装置及び半導体集積回路装置
EP0843360A1 (de) * 1996-11-15 1998-05-20 Hitachi Europe Limited Speicheranordnung
JP3853905B2 (ja) * 1997-03-18 2006-12-06 株式会社東芝 量子効果装置とblトンネル素子を用いた装置
US6421682B1 (en) 1999-07-26 2002-07-16 Microsoft Corporation Catalog management system architecture having data table objects and logic table objects
WO2010050021A1 (ja) * 2008-10-29 2010-05-06 富士通株式会社 化合物半導体装置及びその製造方法
US10103226B2 (en) * 2012-04-30 2018-10-16 International Business Machines Corporation Method of fabricating tunnel transistors with abrupt junctions
US9508854B2 (en) 2013-12-06 2016-11-29 Ecole Polytechnique Federale De Lausanne (Epfl) Single field effect transistor capacitor-less memory device and method of operating the same
DE102016015475B3 (de) * 2016-12-28 2018-01-11 3-5 Power Electronics GmbH IGBT Halbleiterstruktur
KR20180129457A (ko) * 2017-05-26 2018-12-05 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3972059A (en) * 1973-12-28 1976-07-27 International Business Machines Corporation Dielectric diode, fabrication thereof, and charge store memory therewith
JPS5591166A (en) * 1978-12-28 1980-07-10 Nippon Gakki Seizo Kk Semiconductor memory
JPS56124273A (en) * 1980-03-04 1981-09-29 Semiconductor Res Found Semiconductor device
JPS5940576A (ja) * 1982-08-30 1984-03-06 Junichi Nishizawa フオトサイリスタ
JPS60254777A (ja) * 1984-05-31 1985-12-16 Fujitsu Ltd 半導体装置
JPS61158184A (ja) * 1984-12-29 1986-07-17 Fujitsu Ltd 半導体装置
US5216262A (en) * 1992-03-02 1993-06-01 Raphael Tsu Quantum well structures useful for semiconductor devices

Also Published As

Publication number Publication date
EP0631326A3 (de) 1995-05-31
EP0631326B1 (de) 1999-02-24
KR0157662B1 (ko) 1998-10-15
KR940027148A (ko) 1994-12-10
DE69416619T2 (de) 1999-09-30
EP0631326A2 (de) 1994-12-28
TW241381B (de) 1995-02-21
US5485017A (en) 1996-01-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: TOHOKU UNIVERSITY, SENDAI, MIYAGI, JP

8339 Ceased/non-payment of the annual fee