DE69631315T2 - Halbleiterspeicheranordnung und Verfahren zur Herstellung - Google Patents

Halbleiterspeicheranordnung und Verfahren zur Herstellung Download PDF

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Publication number
DE69631315T2
DE69631315T2 DE69631315T DE69631315T DE69631315T2 DE 69631315 T2 DE69631315 T2 DE 69631315T2 DE 69631315 T DE69631315 T DE 69631315T DE 69631315 T DE69631315 T DE 69631315T DE 69631315 T2 DE69631315 T2 DE 69631315T2
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69631315T
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English (en)
Other versions
DE69631315D1 (de
Inventor
Keun Hyung Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Application granted granted Critical
Publication of DE69631315D1 publication Critical patent/DE69631315D1/de
Publication of DE69631315T2 publication Critical patent/DE69631315T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
DE69631315T 1995-10-05 1996-08-28 Halbleiterspeicheranordnung und Verfahren zur Herstellung Expired - Lifetime DE69631315T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950034120A KR0179175B1 (ko) 1995-10-05 1995-10-05 반도체 메모리 장치 및 제조방법

Publications (2)

Publication Number Publication Date
DE69631315D1 DE69631315D1 (de) 2004-02-19
DE69631315T2 true DE69631315T2 (de) 2004-10-21

Family

ID=19429330

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631315T Expired - Lifetime DE69631315T2 (de) 1995-10-05 1996-08-28 Halbleiterspeicheranordnung und Verfahren zur Herstellung

Country Status (7)

Country Link
US (3) US5687119A (de)
EP (1) EP0767498B1 (de)
JP (1) JP2847507B2 (de)
KR (1) KR0179175B1 (de)
CN (1) CN1163966C (de)
DE (1) DE69631315T2 (de)
TW (1) TW300338B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69732293D1 (de) * 1997-08-27 2005-02-24 St Microelectronics Srl Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher
US6054348A (en) * 1998-05-15 2000-04-25 Taiwan Semiconductor Manufacturing Company Self-aligned source process
US6429495B2 (en) * 1998-06-17 2002-08-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with address programming circuit
US6110779A (en) * 1998-07-17 2000-08-29 Advanced Micro Devices, Inc. Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride
TW399332B (en) * 1998-08-12 2000-07-21 United Microelectronics Corp The structure of flash memory cell and the manufacturing method thereof
JP3344563B2 (ja) * 1998-10-30 2002-11-11 シャープ株式会社 半導体装置
JP2000223590A (ja) * 1999-02-04 2000-08-11 Sony Corp ゲート電荷蓄積形メモリセル
KR100387267B1 (ko) * 1999-12-22 2003-06-11 주식회사 하이닉스반도체 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법
US6642111B1 (en) * 2002-07-09 2003-11-04 Powerchip Semiconductor Corp. Memory device structure and method of fabricating the same
JP4346322B2 (ja) * 2003-02-07 2009-10-21 株式会社ルネサステクノロジ 半導体装置
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
FR2891398A1 (fr) * 2005-09-23 2007-03-30 St Microelectronics Sa Memoire non volatile reprogrammable
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) * 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US20090016118A1 (en) * 2007-07-12 2009-01-15 Silicon Storage Technology, Inc. Non-volatile dram with floating gate and method of operation
US8391078B2 (en) * 2008-02-12 2013-03-05 Chip Memory Technology, Inc. Method and apparatus of operating a non-volatile DRAM
US9029863B2 (en) * 2012-04-20 2015-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9431253B1 (en) * 2015-08-05 2016-08-30 Texas Instruments Incorporated Fabrication flow based on metal gate process for making low cost flash memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61165896A (ja) * 1985-01-17 1986-07-26 Matsushita Electronics Corp フロ−テイングゲ−ト型不揮発性メモリ素子
JPS62155568A (ja) * 1985-12-27 1987-07-10 Nec Corp 不揮発性半導体記憶装置
JPH0817209B2 (ja) * 1987-10-16 1996-02-21 松下電子工業株式会社 半導体装置
JP2500871B2 (ja) * 1991-03-30 1996-05-29 株式会社東芝 半導体不揮発性ｒａｍ
JP3114155B2 (ja) * 1991-08-05 2000-12-04 日本電信電話株式会社 アナログメモリ素子
JPH05243522A (ja) * 1992-03-02 1993-09-21 Hitachi Ltd 半導体記憶装置およびその製造方法
US5336937A (en) * 1992-08-28 1994-08-09 State University Of New York Programmable analog synapse and neural networks incorporating same
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
US5554552A (en) * 1995-04-03 1996-09-10 Taiwan Semiconductor Manufacturing Company PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof
US5541130A (en) * 1995-06-07 1996-07-30 International Business Machines Corporation Process for making and programming a flash memory array
US5753952A (en) * 1995-09-22 1998-05-19 Texas Instruments Incorporated Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

Also Published As

Publication number Publication date
US5998827A (en) 1999-12-07
US5687119A (en) 1997-11-11
TW300338B (en) 1997-03-11
JP2847507B2 (ja) 1999-01-20
JPH09129837A (ja) 1997-05-16
KR970024197A (ko) 1997-05-30
CN1163966C (zh) 2004-08-25
CN1147674A (zh) 1997-04-16
US5950088A (en) 1999-09-07
EP0767498B1 (de) 2004-01-14
EP0767498A1 (de) 1997-04-09
DE69631315D1 (de) 2004-02-19
KR0179175B1 (ko) 1999-03-20

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