DE69732293D1 - Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher - Google Patents

Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher

Info

Publication number
DE69732293D1
DE69732293D1 DE69732293T DE69732293T DE69732293D1 DE 69732293 D1 DE69732293 D1 DE 69732293D1 DE 69732293 T DE69732293 T DE 69732293T DE 69732293 T DE69732293 T DE 69732293T DE 69732293 D1 DE69732293 D1 DE 69732293D1
Authority
DE
Germany
Prior art keywords
manufacturing
nonvolatile memory
channel transistor
native mos
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69732293T
Other languages
English (en)
Inventor
Valerio Cassio
Claudio Brambilla
Manlio Sergio Cereda
Paolo Caprara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69732293D1 publication Critical patent/DE69732293D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
DE69732293T 1997-08-27 1997-08-27 Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher Expired - Lifetime DE69732293D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97830428A EP0902466B1 (de) 1997-08-27 1997-08-27 Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher

Publications (1)

Publication Number Publication Date
DE69732293D1 true DE69732293D1 (de) 2005-02-24

Family

ID=8230760

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69732293T Expired - Lifetime DE69732293D1 (de) 1997-08-27 1997-08-27 Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher

Country Status (4)

Country Link
US (1) US6063663A (de)
EP (1) EP0902466B1 (de)
JP (1) JPH11135655A (de)
DE (1) DE69732293D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10108923C1 (de) * 2001-02-23 2002-08-08 Infineon Technologies Ag Nativer Feldeffekttransistor und Verfahren zu dessen Herstellung
US8269204B2 (en) 2009-07-02 2012-09-18 Actel Corporation Back to back resistive random access memory cells
US9287278B2 (en) * 2013-03-01 2016-03-15 Microsemi SoC Corporation Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
US10270451B2 (en) 2015-12-17 2019-04-23 Microsemi SoC Corporation Low leakage ReRAM FPGA configuration cell
US10147485B2 (en) 2016-09-29 2018-12-04 Microsemi Soc Corp. Circuits and methods for preventing over-programming of ReRAM-based memory cells
CN110036484B (zh) 2016-12-09 2021-04-30 美高森美SoC公司 电阻式随机存取存储器单元
DE112018004134T5 (de) 2017-08-11 2020-04-23 Microsemi Soc Corp. Schaltlogik und verfahren zur programmierung von resistiven direktzugriffs-speichervorrichtungen
TWI826016B (zh) * 2022-09-26 2023-12-11 立錡科技股份有限公司 原生nmos元件及其製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
KR960009995B1 (ko) * 1992-07-31 1996-07-25 삼성전자 주식회사 반도체 장치의 제조 방법 및 그 구조
KR0179175B1 (ko) * 1995-10-05 1999-03-20 문정환 반도체 메모리 장치 및 제조방법
DE69625169D1 (de) * 1996-01-22 2003-01-16 St Microelectronics Srl Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher

Also Published As

Publication number Publication date
EP0902466B1 (de) 2005-01-19
JPH11135655A (ja) 1999-05-21
US6063663A (en) 2000-05-16
EP0902466A1 (de) 1999-03-17

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Legal Events

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