DE69426747D1 - Verfahren zur Herstellung des Gates eines Transistors - Google Patents
Verfahren zur Herstellung des Gates eines TransistorsInfo
- Publication number
- DE69426747D1 DE69426747D1 DE69426747T DE69426747T DE69426747D1 DE 69426747 D1 DE69426747 D1 DE 69426747D1 DE 69426747 T DE69426747 T DE 69426747T DE 69426747 T DE69426747 T DE 69426747T DE 69426747 D1 DE69426747 D1 DE 69426747D1
- Authority
- DE
- Germany
- Prior art keywords
- transistor
- gate
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/136,516 US5431770A (en) | 1993-10-13 | 1993-10-13 | Transistor gate formation |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69426747D1 true DE69426747D1 (de) | 2001-04-05 |
DE69426747T2 DE69426747T2 (de) | 2001-07-05 |
Family
ID=22473178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69426747T Expired - Fee Related DE69426747T2 (de) | 1993-10-13 | 1994-10-05 | Verfahren zur Herstellung des Gates eines Transistors |
Country Status (7)
Country | Link |
---|---|
US (1) | US5431770A (de) |
EP (1) | EP0649166B1 (de) |
JP (1) | JP2968180B2 (de) |
KR (1) | KR100374916B1 (de) |
DE (1) | DE69426747T2 (de) |
ES (1) | ES2156139T3 (de) |
TW (1) | TW258825B (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0621018A (ja) * | 1992-06-29 | 1994-01-28 | Sony Corp | ドライエッチング方法 |
TW316326B (en) * | 1996-09-21 | 1997-09-21 | United Microelectronics Corp | Manufacturing method of word line |
US5963841A (en) * | 1997-08-01 | 1999-10-05 | Advanced Micro Devices, Inc. | Gate pattern formation using a bottom anti-reflective coating |
US6107172A (en) * | 1997-08-01 | 2000-08-22 | Advanced Micro Devices, Inc. | Controlled linewidth reduction during gate pattern formation using an SiON BARC |
US5965461A (en) * | 1997-08-01 | 1999-10-12 | Advanced Micro Devices, Inc. | Controlled linewidth reduction during gate pattern formation using a spin-on barc |
US6121123A (en) * | 1997-09-05 | 2000-09-19 | Advanced Micro Devices, Inc. | Gate pattern formation using a BARC as a hardmask |
US5937315A (en) * | 1997-11-07 | 1999-08-10 | Advanced Micro Devices, Inc. | Self-aligned silicide gate technology for advanced submicron MOS devices |
US6069046A (en) * | 1997-11-26 | 2000-05-30 | Advanced Micro Devices, Inc. | Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment |
JP3570903B2 (ja) * | 1998-09-25 | 2004-09-29 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6165881A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Method of forming salicide poly gate with thin gate oxide and ultra narrow gate width |
KR100564419B1 (ko) * | 1998-12-30 | 2006-06-07 | 주식회사 하이닉스반도체 | 텅스텐 실리사이드층 형성방법 |
US6191016B1 (en) * | 1999-01-05 | 2001-02-20 | Intel Corporation | Method of patterning a layer for a gate electrode of a MOS transistor |
JP3875455B2 (ja) | 1999-04-28 | 2007-01-31 | 株式会社東芝 | 半導体装置の製造方法 |
DE19945425A1 (de) * | 1999-09-22 | 2001-04-19 | Infineon Technologies Ag | Verfahren zum Strukturieren einer Metallschicht in der Halbleiterfertigung |
US6365516B1 (en) | 2000-01-14 | 2002-04-02 | Advanced Micro Devices, Inc. | Advanced cobalt silicidation with in-situ hydrogen plasma clean |
US6492275B2 (en) | 2000-01-21 | 2002-12-10 | Advanced Micro Devices, Inc. | Control of transistor performance through adjustment of spacer oxide profile with a wet etch |
US6420097B1 (en) | 2000-05-02 | 2002-07-16 | Advanced Micro Devices, Inc. | Hardmask trim process |
US6794279B1 (en) * | 2000-05-23 | 2004-09-21 | Advanced Micro Devices, Inc. | Passivating inorganic bottom anti-reflective coating (BARC) using rapid thermal anneal (RTA) with oxidizing gas |
US6261936B1 (en) | 2000-06-07 | 2001-07-17 | Advanced Micro Devices, Inc. | Poly gate CD passivation for metrology control |
JP2002009056A (ja) * | 2000-06-22 | 2002-01-11 | Mitsubishi Electric Corp | 微細パターン形成方法およびその方法により製造した装置 |
US6403432B1 (en) | 2000-08-15 | 2002-06-11 | Taiwan Semiconductor Manufacturing Company | Hardmask for a salicide gate process with trench isolation |
US6482726B1 (en) * | 2000-10-17 | 2002-11-19 | Advanced Micro Devices, Inc. | Control trimming of hard mask for sub-100 nanometer transistor gate |
US6642152B1 (en) | 2001-03-19 | 2003-11-04 | Advanced Micro Devices, Inc. | Method for ultra thin resist linewidth reduction using implantation |
US6884722B2 (en) * | 2001-09-27 | 2005-04-26 | International Business Machines Corporation | Method of fabricating a narrow polysilicon line |
US6566214B1 (en) * | 2002-01-17 | 2003-05-20 | Advanced Micro Devices, Inc. | Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer |
US6828205B2 (en) * | 2002-02-07 | 2004-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd | Method using wet etching to trim a critical dimension |
US7105442B2 (en) | 2002-05-22 | 2006-09-12 | Applied Materials, Inc. | Ashable layers for reducing critical dimensions of integrated circuit features |
DE102004019588A1 (de) * | 2004-04-22 | 2005-11-17 | Osram Opto Semiconductors Gmbh | Verfahren zur Strukturierung von zumindest einer Schicht sowie elektrisches Bauelement mit Strukturen aus der Schicht |
DE102005008478B3 (de) | 2005-02-24 | 2006-10-26 | Infineon Technologies Ag | Verfahren zur Herstellung von sublithographischen Strukturen |
US20070037371A1 (en) * | 2005-08-10 | 2007-02-15 | Zhigang Wang | Method of forming gate electrode structures |
JP5028811B2 (ja) * | 2006-02-03 | 2012-09-19 | 住友電気工業株式会社 | 化合物半導体光デバイスを作製する方法 |
US7662718B2 (en) * | 2006-03-09 | 2010-02-16 | Micron Technology, Inc. | Trim process for critical dimension control for integrated circuits |
JP5578389B2 (ja) * | 2006-05-16 | 2014-08-27 | Nltテクノロジー株式会社 | 積層膜パターン形成方法及びゲート電極形成方法 |
CN103441069B (zh) * | 2013-08-02 | 2016-01-27 | 上海华力微电子有限公司 | 改善有源区损伤的方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4460435A (en) * | 1983-12-19 | 1984-07-17 | Rca Corporation | Patterning of submicrometer metal silicide structures |
EP0394597A1 (de) * | 1989-04-28 | 1990-10-31 | International Business Machines Corporation | System zum Verfolgen eines Ätzprozesses in einer RIE-Vorrichtung und dessen Verwendung zur Herstellung reproduzierbarer Strukturen hoher Auflösung |
DE3915650A1 (de) * | 1989-05-12 | 1990-11-15 | Siemens Ag | Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht |
US5201993A (en) * | 1989-07-20 | 1993-04-13 | Micron Technology, Inc. | Anisotropic etch method |
US5169487A (en) * | 1990-08-27 | 1992-12-08 | Micron Technology, Inc. | Anisotropic etch method |
-
1993
- 1993-10-13 US US08/136,516 patent/US5431770A/en not_active Expired - Lifetime
-
1994
- 1994-10-05 EP EP94307274A patent/EP0649166B1/de not_active Expired - Lifetime
- 1994-10-05 ES ES94307274T patent/ES2156139T3/es not_active Expired - Lifetime
- 1994-10-05 DE DE69426747T patent/DE69426747T2/de not_active Expired - Fee Related
- 1994-10-07 JP JP6268003A patent/JP2968180B2/ja not_active Expired - Fee Related
- 1994-10-12 KR KR1019940026037A patent/KR100374916B1/ko not_active IP Right Cessation
- 1994-10-17 TW TW083109611A patent/TW258825B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0649166A2 (de) | 1995-04-19 |
US5431770A (en) | 1995-07-11 |
EP0649166A3 (de) | 1995-07-26 |
JP2968180B2 (ja) | 1999-10-25 |
KR100374916B1 (ko) | 2003-05-09 |
ES2156139T3 (es) | 2001-06-16 |
JPH07169964A (ja) | 1995-07-04 |
TW258825B (de) | 1995-10-01 |
KR950012644A (ko) | 1995-05-16 |
DE69426747T2 (de) | 2001-07-05 |
EP0649166B1 (de) | 2001-02-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |