DE68914909D1 - Verfahren zur Herstellung eines Transistors mit versenktem Gate. - Google Patents

Verfahren zur Herstellung eines Transistors mit versenktem Gate.

Info

Publication number
DE68914909D1
DE68914909D1 DE68914909T DE68914909T DE68914909D1 DE 68914909 D1 DE68914909 D1 DE 68914909D1 DE 68914909 T DE68914909 T DE 68914909T DE 68914909 T DE68914909 T DE 68914909T DE 68914909 D1 DE68914909 D1 DE 68914909D1
Authority
DE
Germany
Prior art keywords
manufacturing
gate transistor
buried gate
buried
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68914909T
Other languages
English (en)
Inventor
Yuuichi Panamento Tam Hasegawa
Hidetake Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68914909D1 publication Critical patent/DE68914909D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Junction Field-Effect Transistors (AREA)
DE68914909T 1988-08-26 1989-08-11 Verfahren zur Herstellung eines Transistors mit versenktem Gate. Expired - Lifetime DE68914909D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63213319A JP2682043B2 (ja) 1988-08-26 1988-08-26 化合物半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE68914909D1 true DE68914909D1 (de) 1994-06-01

Family

ID=16637182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68914909T Expired - Lifetime DE68914909D1 (de) 1988-08-26 1989-08-11 Verfahren zur Herstellung eines Transistors mit versenktem Gate.

Country Status (4)

Country Link
US (1) US4910157A (de)
EP (1) EP0355619B1 (de)
JP (1) JP2682043B2 (de)
DE (1) DE68914909D1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585288A (en) * 1990-07-16 1996-12-17 Raytheon Company Digital MMIC/analog MMIC structures and process
JPH04171733A (ja) * 1990-11-02 1992-06-18 Matsushita Electric Ind Co Ltd 電界効果トランジスタの製造方法
KR0130963B1 (ko) * 1992-06-09 1998-04-14 구자홍 T형 단면구조의 게이트 금속전극을 갖는 전계효과 트랜지스터의 제조방법
US5384269A (en) * 1992-12-09 1995-01-24 Motorola, Inc. Methods for making and using a shallow semiconductor junction
US6642559B1 (en) * 1999-04-14 2003-11-04 The Whitaker Corporation Structure and process for improving high frequency isolation in semiconductor substrates

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3946419A (en) * 1973-06-27 1976-03-23 International Business Machines Corporation Field effect transistor structure for minimizing parasitic inversion and process for fabricating
DE2631873C2 (de) * 1976-07-15 1986-07-31 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung eines Halbleiterbauelements mit einem Schottky-Kontakt auf einem zu einem anderen Bereich justierten Gatebereich und mit kleinem Serienwiderstand
US4312112A (en) * 1978-10-23 1982-01-26 Eaton Corporation Method of making field-effect transistors with micron and submicron gate lengths
JPS61199641A (ja) * 1985-02-28 1986-09-04 Oki Electric Ind Co Ltd 化合物半導体素子の製造方法
JPH0672678B2 (ja) * 1985-07-30 1994-09-14 日東電工株式会社 管継手シ−ル工法及びシ−ル材
JPS63283029A (ja) * 1987-05-14 1988-11-18 Sanyo Electric Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2682043B2 (ja) 1997-11-26
EP0355619B1 (de) 1994-04-27
EP0355619A1 (de) 1990-02-28
JPH0262053A (ja) 1990-03-01
US4910157A (en) 1990-03-20

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Legal Events

Date Code Title Description
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