DE69625169D1 - Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher - Google Patents

Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher

Info

Publication number
DE69625169D1
DE69625169D1 DE69625169T DE69625169T DE69625169D1 DE 69625169 D1 DE69625169 D1 DE 69625169D1 DE 69625169 T DE69625169 T DE 69625169T DE 69625169 T DE69625169 T DE 69625169T DE 69625169 D1 DE69625169 D1 DE 69625169D1
Authority
DE
Germany
Prior art keywords
manufacture
volatile memory
memory process
natural transistors
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69625169T
Other languages
English (en)
Inventor
Paolo Rolandi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69625169D1 publication Critical patent/DE69625169D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE69625169T 1996-01-22 1996-01-22 Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher Expired - Lifetime DE69625169D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830021A EP0785570B1 (de) 1996-01-22 1996-01-22 Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher

Publications (1)

Publication Number Publication Date
DE69625169D1 true DE69625169D1 (de) 2003-01-16

Family

ID=8225790

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69625169T Expired - Lifetime DE69625169D1 (de) 1996-01-22 1996-01-22 Herstellung von natürlichen Transistoren in einem Verfahren für nichtflüchtige Speicher

Country Status (3)

Country Link
US (1) US5923975A (de)
EP (1) EP0785570B1 (de)
DE (1) DE69625169D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0902466B1 (de) * 1997-08-27 2005-01-19 STMicroelectronics S.r.l. Herstellungsverfahren eines nativen MOS-P-Kanal-Transistors mit Verfahren für nichtflüchtige Speicher
US6162683A (en) * 1997-12-19 2000-12-19 Texas Instruments Incorporated System and method for forming an inter-layer dielectric in floating gate memory devices
US6228782B1 (en) * 1999-05-11 2001-05-08 Advanced Micro Devices, Inc. Core field isolation for a NAND flash memory
US6159802A (en) * 1999-07-14 2000-12-12 United Microelectronics Corp. Method of forming a stack-gate of a non-volatile memory on a semiconductor wafer
US6806123B2 (en) 2002-04-26 2004-10-19 Micron Technology, Inc. Methods of forming isolation regions associated with semiconductor constructions
US6756619B2 (en) * 2002-08-26 2004-06-29 Micron Technology, Inc. Semiconductor constructions
US7244651B2 (en) * 2003-05-21 2007-07-17 Texas Instruments Incorporated Fabrication of an OTP-EPROM having reduced leakage current
EP1492126A1 (de) * 2003-06-27 2004-12-29 Dialog Semiconductor GmbH DRAM-Zelle mit natürlichem Transistor für analoge oder vielfache Pegel
US6958271B1 (en) * 2003-08-04 2005-10-25 Advanced Micro Devices, Inc. Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3105925C2 (de) * 1981-02-18 1983-01-05 Westfaelische Metall Industrie Kg Hueck & Co, 4780 Lippstadt Fahrzeugscheinwerfer, dessen Reflektor um zwei senkrecht zueinander verlaufende Achsen verstellbar ist
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
JP2509697B2 (ja) * 1989-04-28 1996-06-26 株式会社東芝 半導体装置およびその製造方法
KR930007527B1 (ko) * 1990-09-22 1993-08-12 삼성전자 주식회사 스토리지 셀 어레이와 주변회로를 갖는 불휘발성 반도체 메모리 장치의 제조방법 및 그 구조
KR960009995B1 (ko) * 1992-07-31 1996-07-25 삼성전자 주식회사 반도체 장치의 제조 방법 및 그 구조
US5412238A (en) * 1992-09-08 1995-05-02 National Semiconductor Corporation Source-coupling, split-gate, virtual ground flash EEPROM array
US5554551A (en) * 1994-11-23 1996-09-10 United Microelectronics Corporation Method of manufacture of an EEPROM cell with self-aligned thin dielectric area
KR0161402B1 (ko) * 1995-03-22 1998-12-01 김광호 불휘발성 메모리 제조방법
KR0144906B1 (ko) * 1995-03-31 1998-07-01 김광호 불휘발성 메모리 소자 및 그 제조방법

Also Published As

Publication number Publication date
EP0785570B1 (de) 2002-12-04
US5923975A (en) 1999-07-13
EP0785570A1 (de) 1997-07-23

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