DE69511320D1 - Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeichervorrichtung - Google Patents

Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeichervorrichtung

Info

Publication number
DE69511320D1
DE69511320D1 DE69511320T DE69511320T DE69511320D1 DE 69511320 D1 DE69511320 D1 DE 69511320D1 DE 69511320 T DE69511320 T DE 69511320T DE 69511320 T DE69511320 T DE 69511320T DE 69511320 D1 DE69511320 D1 DE 69511320D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
volatile semiconductor
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69511320T
Other languages
English (en)
Other versions
DE69511320T2 (de
Inventor
Jeong-Hyong Yi
Jeong-Hyuk Choi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE69511320D1 publication Critical patent/DE69511320D1/de
Application granted granted Critical
Publication of DE69511320T2 publication Critical patent/DE69511320T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
DE69511320T 1994-05-13 1995-05-12 Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeichervorrichtung Expired - Lifetime DE69511320T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940010489A KR0138312B1 (ko) 1994-05-13 1994-05-13 비휘발성 반도체 메모리장치의 제조방법

Publications (2)

Publication Number Publication Date
DE69511320D1 true DE69511320D1 (de) 1999-09-16
DE69511320T2 DE69511320T2 (de) 2000-01-13

Family

ID=19383016

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69511320T Expired - Lifetime DE69511320T2 (de) 1994-05-13 1995-05-12 Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeichervorrichtung

Country Status (5)

Country Link
US (1) US5663084A (de)
EP (1) EP0682364B1 (de)
JP (1) JPH0864706A (de)
KR (1) KR0138312B1 (de)
DE (1) DE69511320T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716864A (en) * 1994-07-22 1998-02-10 Nkk Corporation Method of manufacturing a non-volatile semiconductor memory device with peripheral transistor
JP3290827B2 (ja) * 1994-09-01 2002-06-10 東芝マイクロエレクトロニクス株式会社 半導体装置とその製造方法
JPH104182A (ja) * 1996-06-14 1998-01-06 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JPH10308497A (ja) * 1997-05-08 1998-11-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6004829A (en) * 1997-09-12 1999-12-21 Taiwan Semiconductor Manufacturing Company Method of increasing end point detection capability of reactive ion etching by adding pad area
JPH11330430A (ja) 1998-05-18 1999-11-30 Nec Corp 不揮発性半導体記憶装置の製造方法
US6232235B1 (en) * 1998-06-03 2001-05-15 Motorola, Inc. Method of forming a semiconductor device
KR100475033B1 (ko) * 1998-06-08 2005-05-27 삼성전자주식회사 불휘발성 메모리소자 제조방법
JP3228230B2 (ja) * 1998-07-21 2001-11-12 日本電気株式会社 半導体装置の製造方法
US6110782A (en) * 1998-11-19 2000-08-29 Taiwan Semiconductor Manufacturing Company Method to combine high voltage device and salicide process
EP1005079B1 (de) * 1998-11-26 2012-12-26 STMicroelectronics Srl Integrationsverfahren eines Festwertspeichers und eines Hochleistungslogikschaltkreises auf einem Chip
JP2000349164A (ja) * 1999-06-08 2000-12-15 Nec Corp 素子分離絶縁膜を有する半導体装置の製造方法
JP2001093996A (ja) * 1999-09-27 2001-04-06 Toshiba Corp 半導体装置の製造方法
JP2002083883A (ja) * 2000-09-06 2002-03-22 Oki Electric Ind Co Ltd 不揮発性半導体記憶装置およびその製造方法
KR100399350B1 (ko) * 2001-08-09 2003-09-26 삼성전자주식회사 부유 트랩형 소자를 가지는 비휘발성 반도체 메모리 장치및 그 제조방법
US6664120B1 (en) * 2001-12-17 2003-12-16 Cypress Semiconductor Corp. Method and structure for determining a concentration profile of an impurity within a semiconductor layer
US6551899B1 (en) * 2002-04-30 2003-04-22 Hsu-Sheng Yu Methods of fabricating memory cells for nonvolatile memory devices
KR20080046483A (ko) * 2006-11-22 2008-05-27 삼성전자주식회사 반도체 장치 및 그 형성방법
TWI263309B (en) * 2005-08-29 2006-10-01 Powerchip Semiconductor Corp Method of fabricating non-volatile memory
CN101479843B (zh) * 2006-06-30 2011-03-30 富士通半导体股份有限公司 半导体装置和半导体装置的制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5850771A (ja) * 1981-09-21 1983-03-25 Hitachi Ltd 再書込み可能な高集積ｒｏｍ及びその製造方法
JPH07114264B2 (ja) * 1985-08-23 1995-12-06 株式会社日立製作所 半導体集積回路装置の製造方法
IT1196997B (it) * 1986-07-25 1988-11-25 Sgs Microelettronica Spa Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati
IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
JPH02266329A (ja) * 1989-04-07 1990-10-31 Seiko Epson Corp 液晶表示体の製造方法
JPH039572A (ja) * 1989-06-07 1991-01-17 Nec Corp 半導体装置の製造方法
JPH0770628B2 (ja) * 1989-10-06 1995-07-31 株式会社東芝 半導体装置およびその製造方法
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
JP3168617B2 (ja) * 1990-07-13 2001-05-21 株式会社日立製作所 不揮発性半導体記憶装置の製造方法
US5175120A (en) * 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
JP2819972B2 (ja) * 1992-11-10 1998-11-05 日本電気株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
KR0138312B1 (ko) 1998-04-28
EP0682364A1 (de) 1995-11-15
DE69511320T2 (de) 2000-01-13
US5663084A (en) 1997-09-02
EP0682364B1 (de) 1999-08-11
KR950034731A (ko) 1995-12-28
JPH0864706A (ja) 1996-03-08

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