DE69322928D1 - Verfahren zur Herstellung eines nicht-flüchtigen Halbleiter-Speicherbauteils - Google Patents

Verfahren zur Herstellung eines nicht-flüchtigen Halbleiter-Speicherbauteils

Info

Publication number
DE69322928D1
DE69322928D1 DE69322928T DE69322928T DE69322928D1 DE 69322928 D1 DE69322928 D1 DE 69322928D1 DE 69322928 T DE69322928 T DE 69322928T DE 69322928 T DE69322928 T DE 69322928T DE 69322928 D1 DE69322928 D1 DE 69322928D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
volatile semiconductor
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69322928T
Other languages
English (en)
Other versions
DE69322928T2 (de
Inventor
Tatsuro Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69322928D1 publication Critical patent/DE69322928D1/de
Application granted granted Critical
Publication of DE69322928T2 publication Critical patent/DE69322928T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE69322928T 1992-10-27 1993-10-26 Verfahren zur Herstellung eines nicht-flüchtigen Halbleiter-Speicherbauteils Expired - Fee Related DE69322928T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28804392 1992-10-27

Publications (2)

Publication Number Publication Date
DE69322928D1 true DE69322928D1 (de) 1999-02-18
DE69322928T2 DE69322928T2 (de) 1999-07-29

Family

ID=17725098

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322928T Expired - Fee Related DE69322928T2 (de) 1992-10-27 1993-10-26 Verfahren zur Herstellung eines nicht-flüchtigen Halbleiter-Speicherbauteils

Country Status (4)

Country Link
US (1) US5449634A (de)
EP (1) EP0595250B1 (de)
KR (1) KR0139188B1 (de)
DE (1) DE69322928T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5716864A (en) * 1994-07-22 1998-02-10 Nkk Corporation Method of manufacturing a non-volatile semiconductor memory device with peripheral transistor
KR0161402B1 (ko) * 1995-03-22 1998-12-01 김광호 불휘발성 메모리 제조방법
US5830772A (en) * 1995-09-08 1998-11-03 United Microelectronicscorp. Method for fabricating isolating regions for buried conductors
US6815762B2 (en) * 1997-05-30 2004-11-09 Hitachi, Ltd. Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines
TW347558B (en) * 1996-07-10 1998-12-11 Fujitsu Ltd Semiconductor device with self-aligned contact and its manufacture
JP3212882B2 (ja) * 1996-08-15 2001-09-25 日本電気株式会社 半導体装置の製造方法
KR100234414B1 (ko) * 1997-03-05 1999-12-15 윤종용 불휘발성 메모리장치 및 그 제조방법
TW360951B (en) * 1997-04-01 1999-06-11 Nxp Bv Method of manufacturing a semiconductor device
US6027974A (en) * 1997-04-11 2000-02-22 Programmable Silicon Solutions Nonvolatile memory
US6087221A (en) * 1997-08-22 2000-07-11 Micron Technology, Inc. Method of fabricating two dissimilar devices with diminished processing steps
US6159795A (en) * 1998-07-02 2000-12-12 Advanced Micro Devices, Inc. Low voltage junction and high voltage junction optimization for flash memory
US6180456B1 (en) 1999-02-17 2001-01-30 International Business Machines Corporation Triple polysilicon embedded NVRAM cell and method thereof
JP2000311992A (ja) 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US6306760B1 (en) * 1999-12-09 2001-10-23 United Microelectronics Corp. Method of forming a self-aligned contact hole on a semiconductor wafer
JP4096507B2 (ja) * 2000-09-29 2008-06-04 富士通株式会社 半導体装置の製造方法
JP2006222203A (ja) * 2005-02-09 2006-08-24 Renesas Technology Corp 半導体装置およびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS5850771A (ja) * 1981-09-21 1983-03-25 Hitachi Ltd 再書込み可能な高集積ｒｏｍ及びその製造方法
JPS58184768A (ja) * 1982-04-23 1983-10-28 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPH07114264B2 (ja) * 1985-08-23 1995-12-06 株式会社日立製作所 半導体集積回路装置の製造方法
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
JPS63126279A (ja) * 1987-10-23 1988-05-30 Hitachi Ltd 半導体集積回路装置の製法
JPH01259566A (ja) * 1988-04-08 1989-10-17 Fujitsu Ltd 半導体装置及びその製造方法
FR2642900B1 (fr) * 1989-01-17 1991-05-10 Sgs Thomson Microelectronics Procede de fabrication de circuits integres a transistors de memoire eprom et a transistors logiques
JP2670330B2 (ja) * 1989-01-17 1997-10-29 株式会社東芝 不揮発性半導体記憶装置
JPH03125479A (ja) * 1989-10-11 1991-05-28 Kawasaki Steel Corp 不揮発性記憶素子を有する半導体集積回路の製造方法
US5175120A (en) * 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

Also Published As

Publication number Publication date
KR0139188B1 (ko) 1998-04-27
EP0595250B1 (de) 1999-01-07
EP0595250A2 (de) 1994-05-04
US5449634A (en) 1995-09-12
EP0595250A3 (en) 1994-07-06
DE69322928T2 (de) 1999-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee