IT1196997B - Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati - Google Patents
Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associatiInfo
- Publication number
- IT1196997B IT1196997B IT21254/86A IT2125486A IT1196997B IT 1196997 B IT1196997 B IT 1196997B IT 21254/86 A IT21254/86 A IT 21254/86A IT 2125486 A IT2125486 A IT 2125486A IT 1196997 B IT1196997 B IT 1196997B
- Authority
- IT
- Italy
- Prior art keywords
- volatile
- self
- memory cells
- including non
- structures including
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT21254/86A IT1196997B (it) | 1986-07-25 | 1986-07-25 | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
DE87201211T DE3787421T2 (de) | 1986-07-25 | 1987-06-24 | Verfahren zum Herstellen von Strukturen, einschliesslich nichtflüchtiger Speicherzellen vom EEPROM-Typ, mit selbstausrichtenden Siliziumschichten und dazugehörige Transistoren. |
EP87201211A EP0255159B1 (en) | 1986-07-25 | 1987-06-24 | Process for making structures including e2prom nonvolatile memory cells with self-aligned layers of silicon and associated transistors |
US07/069,183 US4780431A (en) | 1986-07-25 | 1987-07-02 | Process for making structures including E2PROM nonvolatile memory cells with self-aligned layers of silicon and associated transistors |
JP62179259A JP2520648B2 (ja) | 1986-07-25 | 1987-07-20 | 自己整合ケイ素層を有するe▲上2▼prom不揮発性メモリセルと関連トランジスタを含む構造体の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT21254/86A IT1196997B (it) | 1986-07-25 | 1986-07-25 | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
Publications (3)
Publication Number | Publication Date |
---|---|
IT8621254A0 IT8621254A0 (it) | 1986-07-25 |
IT8621254A1 IT8621254A1 (it) | 1988-01-25 |
IT1196997B true IT1196997B (it) | 1988-11-25 |
Family
ID=11179092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT21254/86A IT1196997B (it) | 1986-07-25 | 1986-07-25 | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
Country Status (5)
Country | Link |
---|---|
US (1) | US4780431A (it) |
EP (1) | EP0255159B1 (it) |
JP (1) | JP2520648B2 (it) |
DE (1) | DE3787421T2 (it) |
IT (1) | IT1196997B (it) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980309A (en) * | 1987-11-30 | 1990-12-25 | Texas Instruments, Incorporated | Method of making high density EEPROM |
US5445980A (en) * | 1988-05-10 | 1995-08-29 | Hitachi, Ltd. | Method of making a semiconductor memory device |
US4980301A (en) * | 1988-12-21 | 1990-12-25 | At&T Bell Laboratories | Method for reducing mobile ion contamination in semiconductor integrated circuits |
US5188976A (en) * | 1990-07-13 | 1993-02-23 | Hitachi, Ltd. | Manufacturing method of non-volatile semiconductor memory device |
DE69227772T2 (de) * | 1992-09-30 | 1999-06-24 | St Microelectronics Srl | Verfahren zur Herstellung von nichtflüchtigen Speichern und so hergestellte Speicher |
EP0591599B1 (en) * | 1992-09-30 | 2001-12-19 | STMicroelectronics S.r.l. | Method of fabricating integrated devices, and integrated device produced thereby |
US5568418A (en) * | 1992-09-30 | 1996-10-22 | Sgs-Thomson Microelectronics S.R.L. | Non-volatile memory in an integrated circuit |
US5604141A (en) * | 1994-03-15 | 1997-02-18 | National Semiconductor Corporation | Method for forming virtual-ground flash EPROM array with reduced cell pitch in the X direction |
US5756385A (en) * | 1994-03-30 | 1998-05-26 | Sandisk Corporation | Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US5661053A (en) * | 1994-05-25 | 1997-08-26 | Sandisk Corporation | Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
KR0138312B1 (ko) * | 1994-05-13 | 1998-04-28 | 김광호 | 비휘발성 반도체 메모리장치의 제조방법 |
US5550072A (en) * | 1994-08-30 | 1996-08-27 | National Semiconductor Corporation | Method of fabrication of integrated circuit chip containing EEPROM and capacitor |
US5894146A (en) * | 1995-02-28 | 1999-04-13 | Sgs-Thomson Microelectronics, S.R.L. | EEPROM memory cells matrix with double polysilicon level and relating manufacturing process |
DE69528816T2 (de) * | 1995-02-28 | 2003-10-23 | St Microelectronics Srl | EEPROM-Speicherzellenmatrix mit doppelter Polysiliziumebene und Herstellungsverfahren |
EP0788168A1 (en) | 1996-01-31 | 1997-08-06 | STMicroelectronics S.r.l. | Process of fabricating non-volatile floating-gate memory devices, and memory device fabricated thereby |
TW347567B (en) * | 1996-03-22 | 1998-12-11 | Philips Eloctronics N V | Semiconductor device and method of manufacturing a semiconductor device |
DE69630944D1 (de) * | 1996-03-29 | 2004-01-15 | St Microelectronics Srl | Hochspannungsfester MOS-Transistor und Verfahren zur Herstellung |
DE69630107D1 (de) * | 1996-04-15 | 2003-10-30 | St Microelectronics Srl | Mit einem EEPROM integrierter FLASH-EPROM |
US6330190B1 (en) | 1996-05-30 | 2001-12-11 | Hyundai Electronics America | Semiconductor structure for flash memory enabling low operating potentials |
US6043123A (en) * | 1996-05-30 | 2000-03-28 | Hyundai Electronics America, Inc. | Triple well flash memory fabrication process |
JPH104149A (ja) * | 1996-06-14 | 1998-01-06 | Oki Electric Ind Co Ltd | 半導体記憶装置および製造方法 |
JP2924832B2 (ja) * | 1996-11-28 | 1999-07-26 | 日本電気株式会社 | 半導体装置の製造方法 |
TW360951B (en) * | 1997-04-01 | 1999-06-11 | Nxp Bv | Method of manufacturing a semiconductor device |
JP4068781B2 (ja) | 2000-02-28 | 2008-03-26 | 株式会社ルネサステクノロジ | 半導体集積回路装置および半導体集積回路装置の製造方法 |
US8421143B2 (en) | 2000-09-26 | 2013-04-16 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having element isolating region of trench type |
JP2002176114A (ja) | 2000-09-26 | 2002-06-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5072914B2 (ja) * | 2000-09-26 | 2012-11-14 | 株式会社東芝 | 半導体装置 |
KR100487560B1 (ko) * | 2003-03-10 | 2005-05-03 | 삼성전자주식회사 | 선택 트랜지스터를 갖는 이이피롬 및 그 제조방법 |
KR100517560B1 (ko) * | 2003-07-14 | 2005-09-28 | 삼성전자주식회사 | 선택트랜지스터를 갖는 이이피롬 소자 및 그 제조방법 |
JP4377676B2 (ja) * | 2003-12-24 | 2009-12-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
KR100655285B1 (ko) * | 2004-11-04 | 2006-12-08 | 삼성전자주식회사 | 적층 게이트를 가지는 반도체 소자 및 그 제조방법 |
CN110660808B (zh) * | 2018-06-28 | 2022-11-18 | 无锡华润上华科技有限公司 | 存储器结构及其制造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53124084A (en) * | 1977-04-06 | 1978-10-30 | Hitachi Ltd | Semiconductor memory device containing floating type poly silicon layer and its manufacture |
US4178674A (en) * | 1978-03-27 | 1979-12-18 | Intel Corporation | Process for forming a contact region between layers of polysilicon with an integral polysilicon resistor |
US4180826A (en) * | 1978-05-19 | 1979-12-25 | Intel Corporation | MOS double polysilicon read-only memory and cell |
JPS56116670A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
JPS577162A (en) * | 1980-06-17 | 1982-01-14 | Toshiba Corp | Nonvolatile semiconductor memory and manufacture therefor |
DE3037744A1 (de) * | 1980-10-06 | 1982-05-19 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer monolithisch integrierten zwei-transistor-speicherzelle in mos-technik |
US4531203A (en) * | 1980-12-20 | 1985-07-23 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device and method for manufacturing the same |
JPS5963763A (ja) * | 1982-10-05 | 1984-04-11 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS5974677A (ja) * | 1982-10-22 | 1984-04-27 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JPS59103366A (ja) * | 1982-12-03 | 1984-06-14 | Fujitsu Ltd | 半導体メモリ素子の製造方法 |
JPS60189971A (ja) * | 1984-03-09 | 1985-09-27 | Toshiba Corp | 半導体装置の製造方法 |
IT1213249B (it) * | 1984-11-26 | 1989-12-14 | Ates Componenti Elettron | Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori. |
US4598460A (en) * | 1984-12-10 | 1986-07-08 | Solid State Scientific, Inc. | Method of making a CMOS EPROM with independently selectable thresholds |
JPS62156857A (ja) * | 1985-12-28 | 1987-07-11 | Ricoh Co Ltd | メモリ素子を含む半導体装置の製造方法 |
US4735919A (en) * | 1986-04-15 | 1988-04-05 | General Electric Company | Method of making a floating gate memory cell |
-
1986
- 1986-07-25 IT IT21254/86A patent/IT1196997B/it active
-
1987
- 1987-06-24 DE DE87201211T patent/DE3787421T2/de not_active Expired - Fee Related
- 1987-06-24 EP EP87201211A patent/EP0255159B1/en not_active Expired - Lifetime
- 1987-07-02 US US07/069,183 patent/US4780431A/en not_active Expired - Lifetime
- 1987-07-20 JP JP62179259A patent/JP2520648B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
IT8621254A1 (it) | 1988-01-25 |
DE3787421D1 (de) | 1993-10-21 |
JPS6334977A (ja) | 1988-02-15 |
IT8621254A0 (it) | 1986-07-25 |
EP0255159A2 (en) | 1988-02-03 |
JP2520648B2 (ja) | 1996-07-31 |
US4780431A (en) | 1988-10-25 |
DE3787421T2 (de) | 1994-03-17 |
EP0255159B1 (en) | 1993-09-15 |
EP0255159A3 (en) | 1989-11-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970730 |