IT1213249B - Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori. - Google Patents

Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.

Info

Publication number
IT1213249B
IT1213249B IT8423737A IT2373784A IT1213249B IT 1213249 B IT1213249 B IT 1213249B IT 8423737 A IT8423737 A IT 8423737A IT 2373784 A IT2373784 A IT 2373784A IT 1213249 B IT1213249 B IT 1213249B
Authority
IT
Italy
Prior art keywords
self
manufacture
memory cells
volatile memory
including non
Prior art date
Application number
IT8423737A
Other languages
English (en)
Other versions
IT8423737A0 (it
Inventor
Daniele Cantarelli
Giuseppe Crisenza
Pierangelo Pansana
Original Assignee
Ates Componenti Elettron
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ates Componenti Elettron filed Critical Ates Componenti Elettron
Priority to IT8423737A priority Critical patent/IT1213249B/it
Publication of IT8423737A0 publication Critical patent/IT8423737A0/it
Priority to GB08526959A priority patent/GB2167602B/en
Priority to DE3540422A priority patent/DE3540422C2/de
Priority to NL8503197A priority patent/NL193394C/nl
Priority to JP60259941A priority patent/JP2525144B2/ja
Priority to FR8517406A priority patent/FR2573920B1/fr
Priority to US07/022,482 priority patent/US4719184A/en
Application granted granted Critical
Publication of IT1213249B publication Critical patent/IT1213249B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
IT8423737A 1984-11-26 1984-11-26 Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori. IT1213249B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8423737A IT1213249B (it) 1984-11-26 1984-11-26 Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
GB08526959A GB2167602B (en) 1984-11-26 1985-11-01 Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors
DE3540422A DE3540422C2 (de) 1984-11-26 1985-11-14 Verfahren zum Herstellen integrierter Strukturen mit nicht-flüchtigen Speicherzellen, die selbst-ausgerichtete Siliciumschichten und dazugehörige Transistoren aufweisen
NL8503197A NL193394C (nl) 1984-11-26 1985-11-20 Werkwijze voor het vervaardigen van geïntegreerde structuren die niet- vluchtige geheugencellen en bijbehorende transistoren omvatten.
JP60259941A JP2525144B2 (ja) 1984-11-26 1985-11-21 不揮発性メモリセル及び関連トランジスタを含む集積構造体の製造方法
FR8517406A FR2573920B1 (fr) 1984-11-26 1985-11-25 Procede de fabrication de structures integrees comprenant des cellules de memoire permanente munies de couches de silicium auto-alignees, et des transistors associes a ces cellules
US07/022,482 US4719184A (en) 1984-11-26 1987-03-06 Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8423737A IT1213249B (it) 1984-11-26 1984-11-26 Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.

Publications (2)

Publication Number Publication Date
IT8423737A0 IT8423737A0 (it) 1984-11-26
IT1213249B true IT1213249B (it) 1989-12-14

Family

ID=11209566

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8423737A IT1213249B (it) 1984-11-26 1984-11-26 Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.

Country Status (7)

Country Link
US (1) US4719184A (it)
JP (1) JP2525144B2 (it)
DE (1) DE3540422C2 (it)
FR (1) FR2573920B1 (it)
GB (1) GB2167602B (it)
IT (1) IT1213249B (it)
NL (1) NL193394C (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1196997B (it) * 1986-07-25 1988-11-25 Sgs Microelettronica Spa Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati
KR890001957B1 (ko) * 1986-08-22 1989-06-03 삼성전자 주식회사 디램셀의 제조방법
IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US4859619A (en) * 1988-07-15 1989-08-22 Atmel Corporation EPROM fabrication process forming tub regions for high voltage devices
JPH02211651A (ja) * 1989-02-10 1990-08-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
IT1235690B (it) * 1989-04-07 1992-09-21 Sgs Thomson Microelectronics Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia.
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
IT1250233B (it) * 1991-11-29 1995-04-03 St Microelectronics Srl Procedimento per la fabbricazione di circuiti integrati in tecnologia mos.
CA2107602C (en) * 1992-10-07 2004-01-20 Andrew Jan Walker Method of manufacturing an integrated circuit and integrated circuit obtained by this method
DE69313816T2 (de) * 1993-02-11 1998-03-26 St Microelectronics Srl EEPROM-Zelle und peripherer MOS-Transistor
DE69312676T2 (de) * 1993-02-17 1997-12-04 Sgs Thomson Microelectronics Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz
EP0805479B1 (en) * 1996-04-30 2004-03-17 STMicroelectronics S.r.l. Process for manufacturing an integrated transistor with thick oxide
EP0902465B1 (en) * 1997-08-27 2008-10-15 STMicroelectronics S.r.l. Process for manufacturing electronic virtual-ground memory devices
JP2003518742A (ja) * 1999-12-21 2003-06-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 不揮発性のメモリーセルと周辺部
ITTO20021119A1 (it) * 2002-12-24 2004-06-25 St Microelectronics Srl Dispositivo mos e procedimento di fabbricazione di
ITTO20021118A1 (it) 2002-12-24 2004-06-25 St Microelectronics Srl Dispositivo mos e procedimento di fabbricazione di

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591877A (en) * 1978-12-30 1980-07-11 Fujitsu Ltd Manufacture of semiconductor device
JPS56116670A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor integrated circuit device and manufacture thereof
JPS577162A (en) * 1980-06-17 1982-01-14 Toshiba Corp Nonvolatile semiconductor memory and manufacture therefor
DE3037744A1 (de) * 1980-10-06 1982-05-19 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten zwei-transistor-speicherzelle in mos-technik
JPS5837701B2 (ja) * 1980-12-29 1983-08-18 富士通株式会社 半導体装置の製造方法
JPS5852871A (ja) * 1981-09-25 1983-03-29 Hitachi Ltd 半導体記憶装置
JPS58196053A (ja) * 1982-05-11 1983-11-15 Mitsubishi Electric Corp 半導体装置の製造法
JPS5974677A (ja) * 1982-10-22 1984-04-27 Ricoh Co Ltd 半導体装置及びその製造方法
FR2535525A1 (fr) * 1982-10-29 1984-05-04 Western Electric Co Procede de fabrication de circuits integres comportant des couches isolantes minces

Also Published As

Publication number Publication date
FR2573920A1 (fr) 1986-05-30
US4719184A (en) 1988-01-12
FR2573920B1 (fr) 1988-10-07
GB2167602A (en) 1986-05-29
GB2167602B (en) 1988-12-07
NL193394C (nl) 1999-08-03
DE3540422A1 (de) 1986-05-28
JP2525144B2 (ja) 1996-08-14
GB8526959D0 (en) 1985-12-04
DE3540422C2 (de) 2001-04-26
NL8503197A (nl) 1986-06-16
JPS61131488A (ja) 1986-06-19
IT8423737A0 (it) 1984-11-26
NL193394B (nl) 1999-04-01

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129