IT1225873B - Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura. - Google Patents

Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.

Info

Publication number
IT1225873B
IT1225873B IT8721536A IT2153687A IT1225873B IT 1225873 B IT1225873 B IT 1225873B IT 8721536 A IT8721536 A IT 8721536A IT 2153687 A IT2153687 A IT 2153687A IT 1225873 B IT1225873 B IT 1225873B
Authority
IT
Italy
Prior art keywords
procedure
manufacture
reduction
memory cells
eprom memory
Prior art date
Application number
IT8721536A
Other languages
English (en)
Other versions
IT8721536A0 (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Microelettrica S P A Catan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettrica S P A Catan filed Critical Sgs Microelettrica S P A Catan
Priority to IT8721536A priority Critical patent/IT1225873B/it
Publication of IT8721536A0 publication Critical patent/IT8721536A0/it
Priority to DE88111558T priority patent/DE3887025T2/de
Priority to EP88111558A priority patent/EP0301363B1/en
Priority to US07/224,102 priority patent/US5036018A/en
Priority to JP63187956A priority patent/JP2668081B2/ja
Application granted granted Critical
Publication of IT1225873B publication Critical patent/IT1225873B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
IT8721536A 1987-07-31 1987-07-31 Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura. IT1225873B (it)

Priority Applications (5)

Application Number Priority Date Filing Date Title
IT8721536A IT1225873B (it) 1987-07-31 1987-07-31 Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
DE88111558T DE3887025T2 (de) 1987-07-31 1988-07-19 Methode zur Herstellung von CMOS EPROM-Speicherzellen.
EP88111558A EP0301363B1 (en) 1987-07-31 1988-07-19 Method of manufacturing CMOS EPROM memory cells
US07/224,102 US5036018A (en) 1987-07-31 1988-07-25 Method of manufacturing CMOS EPROM memory cells
JP63187956A JP2668081B2 (ja) 1987-07-31 1988-07-27 Ｃｍｏｓｅｐｒｏｍメモリセルを製造する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8721536A IT1225873B (it) 1987-07-31 1987-07-31 Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.

Publications (2)

Publication Number Publication Date
IT8721536A0 IT8721536A0 (it) 1987-07-31
IT1225873B true IT1225873B (it) 1990-12-07

Family

ID=11183261

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8721536A IT1225873B (it) 1987-07-31 1987-07-31 Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.

Country Status (5)

Country Link
US (1) US5036018A (it)
EP (1) EP0301363B1 (it)
JP (1) JP2668081B2 (it)
DE (1) DE3887025T2 (it)
IT (1) IT1225873B (it)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059442B2 (ja) 1988-11-09 2000-07-04 株式会社日立製作所 半導体記憶装置
JP2509697B2 (ja) * 1989-04-28 1996-06-26 株式会社東芝 半導体装置およびその製造方法
DE3924062C2 (de) * 1989-07-21 1993-11-25 Eurosil Electronic Gmbh EEPROM-Halbleitereinrichtung mit Isolierzonen für Niedervolt-Logikelemente
US5153143A (en) * 1990-02-26 1992-10-06 Delco Electronics Corporation Method of manufacturing CMOS integrated circuit with EEPROM
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
KR960012303B1 (ko) * 1992-08-18 1996-09-18 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
DE69320582T2 (de) * 1992-10-07 1999-04-01 Koninklijke Philips Electronics N.V., Eindhoven Verfahren zur Herstellung eines integrierten Schaltkreises mit einem nichtflüchtigen Speicherelement
EP0613176B1 (en) * 1993-02-17 1997-07-30 STMicroelectronics S.r.l. Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection
JP2924622B2 (ja) * 1993-12-28 1999-07-26 日本電気株式会社 半導体装置の製造方法
KR0138312B1 (ko) * 1994-05-13 1998-04-28 김광호 비휘발성 반도체 메모리장치의 제조방법
US5716864A (en) * 1994-07-22 1998-02-10 Nkk Corporation Method of manufacturing a non-volatile semiconductor memory device with peripheral transistor
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3008854B2 (ja) * 1996-07-12 2000-02-14 日本電気株式会社 不揮発性半導体記憶装置の製造方法
EP0849790A1 (en) * 1996-12-16 1998-06-24 Texas Instruments Incorporated Non-volatile semiconductor memory cell with peripheral transistors
TW389944B (en) * 1997-03-17 2000-05-11 United Microelectronics Corp Method for forming gate oxide layers with different thickness
JP3586072B2 (ja) * 1997-07-10 2004-11-10 株式会社東芝 不揮発性半導体記憶装置
EP1107309B1 (en) * 1999-12-06 2010-10-13 STMicroelectronics Srl Manufacturing process for non-volatile floating gate memory cells and control circuitry
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
US8377772B2 (en) * 2010-08-17 2013-02-19 Texas Instruments Incorporated CMOS integration method for optimal IO transistor VT

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317273A (en) * 1979-11-13 1982-03-02 Texas Instruments Incorporated Method of making high coupling ratio DMOS electrically programmable ROM
JPS5963763A (ja) * 1982-10-05 1984-04-11 Fujitsu Ltd 半導体装置の製造方法
US4696092A (en) * 1984-07-02 1987-09-29 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices
IT1213249B (it) * 1984-11-26 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4646425A (en) * 1984-12-10 1987-03-03 Solid State Scientific, Inc. Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process

Also Published As

Publication number Publication date
EP0301363B1 (en) 1994-01-12
IT8721536A0 (it) 1987-07-31
EP0301363A2 (en) 1989-02-01
JPS6445161A (en) 1989-02-17
JP2668081B2 (ja) 1997-10-27
DE3887025D1 (de) 1994-02-24
EP0301363A3 (en) 1990-05-30
US5036018A (en) 1991-07-30
DE3887025T2 (de) 1994-04-28

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Effective date: 19970730