ITTO20021119A1 - Dispositivo mos e procedimento di fabbricazione di - Google Patents

Dispositivo mos e procedimento di fabbricazione di

Info

Publication number
ITTO20021119A1
ITTO20021119A1 IT001119A ITTO20021119A ITTO20021119A1 IT TO20021119 A1 ITTO20021119 A1 IT TO20021119A1 IT 001119 A IT001119 A IT 001119A IT TO20021119 A ITTO20021119 A IT TO20021119A IT TO20021119 A1 ITTO20021119 A1 IT TO20021119A1
Authority
IT
Italy
Prior art keywords
manufacturing procedure
mos device
mos
procedure
manufacturing
Prior art date
Application number
IT001119A
Other languages
English (en)
Inventor
Carlo Caimi
Paolo Caprara
Valentina Tessa Contin
Davide Merlani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT001119A priority Critical patent/ITTO20021119A1/it
Priority to EP03104939A priority patent/EP1434257B1/en
Priority to US10/745,295 priority patent/US7023047B2/en
Priority to DE60334188T priority patent/DE60334188D1/de
Publication of ITTO20021119A1 publication Critical patent/ITTO20021119A1/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42Simultaneous manufacture of periphery and memory cells
    • H10B41/43Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/035Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
IT001119A 2002-12-24 2002-12-24 Dispositivo mos e procedimento di fabbricazione di ITTO20021119A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT001119A ITTO20021119A1 (it) 2002-12-24 2002-12-24 Dispositivo mos e procedimento di fabbricazione di
EP03104939A EP1434257B1 (en) 2002-12-24 2003-12-23 Process for manufacturing MOS devices using dual-polysilicon layer technology
US10/745,295 US7023047B2 (en) 2002-12-24 2003-12-23 MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology
DE60334188T DE60334188D1 (de) 2002-12-24 2003-12-23 Verfahren zur Herstellung von MOS Bauelementen mit Zweischicht Polysilizium Technik

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001119A ITTO20021119A1 (it) 2002-12-24 2002-12-24 Dispositivo mos e procedimento di fabbricazione di

Publications (1)

Publication Number Publication Date
ITTO20021119A1 true ITTO20021119A1 (it) 2004-06-25

Family

ID=32448952

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001119A ITTO20021119A1 (it) 2002-12-24 2002-12-24 Dispositivo mos e procedimento di fabbricazione di

Country Status (4)

Country Link
US (1) US7023047B2 (it)
EP (1) EP1434257B1 (it)
DE (1) DE60334188D1 (it)
IT (1) ITTO20021119A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITTO20021118A1 (it) 2002-12-24 2004-06-25 St Microelectronics Srl Dispositivo mos e procedimento di fabbricazione di
US7306552B2 (en) * 2004-12-03 2007-12-11 Samsung Electronics Co., Ltd. Semiconductor device having load resistor and method of fabricating the same
CN102088001B (zh) * 2009-12-04 2013-10-09 中芯国际集成电路制造(上海)有限公司 快闪存储器及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213249B (it) * 1984-11-26 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori.
KR940009644B1 (ko) 1991-11-19 1994-10-15 삼성전자 주식회사 불휘발성 반도체메모리장치 및 그 제조방법
JPH104149A (ja) * 1996-06-14 1998-01-06 Oki Electric Ind Co Ltd 半導体記憶装置および製造方法
JP4392867B2 (ja) 1998-02-06 2010-01-06 株式会社ルネサステクノロジ 半導体装置およびその製造方法
EP0996162A1 (en) 1998-10-21 2000-04-26 STMicroelectronics S.r.l. Low resistance contact structure for a select transistor of EEPROM memory cells
JP2000311992A (ja) 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US6680514B1 (en) * 2000-12-20 2004-01-20 International Business Machines Corporation Contact capping local interconnect

Also Published As

Publication number Publication date
DE60334188D1 (de) 2010-10-28
EP1434257A3 (en) 2004-12-15
EP1434257A2 (en) 2004-06-30
US20040188759A1 (en) 2004-09-30
US7023047B2 (en) 2006-04-04
EP1434257B1 (en) 2010-09-15

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