DE60230840D1 - Halbleiteranordnung und Herstellungsverfahren dafür - Google Patents

Halbleiteranordnung und Herstellungsverfahren dafür

Info

Publication number
DE60230840D1
DE60230840D1 DE60230840T DE60230840T DE60230840D1 DE 60230840 D1 DE60230840 D1 DE 60230840D1 DE 60230840 T DE60230840 T DE 60230840T DE 60230840 T DE60230840 T DE 60230840T DE 60230840 D1 DE60230840 D1 DE 60230840D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
method therefor
therefor
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60230840T
Other languages
English (en)
Inventor
Takeshi Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Application granted granted Critical
Publication of DE60230840D1 publication Critical patent/DE60230840D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE60230840T 2001-08-01 2002-07-17 Halbleiteranordnung und Herstellungsverfahren dafür Expired - Lifetime DE60230840D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001233171A JP2003045960A (ja) 2001-08-01 2001-08-01 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
DE60230840D1 true DE60230840D1 (de) 2009-03-05

Family

ID=19064977

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60230840T Expired - Lifetime DE60230840D1 (de) 2001-08-01 2002-07-17 Halbleiteranordnung und Herstellungsverfahren dafür

Country Status (4)

Country Link
US (1) US6777811B2 (de)
EP (1) EP1282168B1 (de)
JP (1) JP2003045960A (de)
DE (1) DE60230840D1 (de)

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SG125881A1 (en) 1999-12-03 2006-10-30 Lytle Steven Alan Define via in dual damascene process
KR101005434B1 (ko) * 2002-04-26 2011-01-05 에이저 시스템즈 인크 신뢰성 개선을 위한 규화 구리 패시베이션
JP4571781B2 (ja) * 2003-03-26 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7268073B2 (en) * 2004-11-10 2007-09-11 Texas Instruments Incorporated Post-polish treatment for inhibiting copper corrosion
JP4621888B2 (ja) * 2005-02-02 2011-01-26 独立行政法人産業技術総合研究所 半導体装置の製造方法
KR100782202B1 (ko) 2005-02-25 2007-12-05 가부시끼가이샤 도시바 반도체 장치 및 그 제조 방법
JP4523535B2 (ja) * 2005-08-30 2010-08-11 富士通株式会社 半導体装置の製造方法
JP2007109736A (ja) * 2005-10-11 2007-04-26 Nec Electronics Corp 半導体装置およびその製造方法
US7790617B2 (en) * 2005-11-12 2010-09-07 Chartered Semiconductor Manufacturing, Ltd. Formation of metal silicide layer over copper interconnect for reliability enhancement
JP4675258B2 (ja) * 2006-02-22 2011-04-20 富士通セミコンダクター株式会社 半導体装置の製造方法および半導体装置
KR100807065B1 (ko) * 2006-12-27 2008-02-25 동부일렉트로닉스 주식회사 반도체 소자의 금속배선 형성방법
JP5143769B2 (ja) * 2008-03-12 2013-02-13 東京エレクトロン株式会社 半導体装置およびその製造方法
DE102008063417B4 (de) * 2008-12-31 2016-08-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Lokale Silizidierung an Kontaktlochunterseiten in Metallisierungssystemen von Halbleiterbauelementen
US9997007B2 (en) * 2009-10-01 2018-06-12 Patent Investment & Licensing Company Method and system for implementing mystery bonus in place of base game results on gaming machine
WO2011161797A1 (ja) 2010-06-24 2011-12-29 富士通株式会社 配線構造の形成方法、半導体装置の製造方法、基板処理装置
DE102010063294B4 (de) * 2010-12-16 2019-07-11 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Metallisierungssystemen von Halbleiterbauelementen, die eine Kupfer/Silizium-Verbindung als ein Barrierenmaterial aufweisen
JP5408116B2 (ja) * 2010-12-17 2014-02-05 富士通セミコンダクター株式会社 半導体装置の製造方法
US20120273950A1 (en) * 2011-04-27 2012-11-01 Nanya Technology Corporation Integrated circuit structure including copper-aluminum interconnect and method for fabricating the same
TWI550745B (zh) * 2015-07-29 2016-09-21 恆勁科技股份有限公司 封裝基板及其製作方法
US10658234B2 (en) * 2016-07-29 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of interconnection structure of semiconductor device
CN110164850A (zh) 2018-02-15 2019-08-23 松下知识产权经营株式会社 电容元件和电容元件的制造方法

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US5801444A (en) * 1989-09-29 1998-09-01 International Business Machines Corporation Multilevel electronic structures containing copper layer and copper-semiconductor layers
EP0472804B1 (de) * 1990-08-01 1997-07-30 International Business Machines Corporation Kupfer-Germanium Verbindungen, die bei Niedrigtemperatur hergestellt werden können
US5447887A (en) * 1994-04-01 1995-09-05 Motorola, Inc. Method for capping copper in semiconductor devices
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Also Published As

Publication number Publication date
US20030025207A1 (en) 2003-02-06
EP1282168B1 (de) 2009-01-14
US6777811B2 (en) 2004-08-17
EP1282168A2 (de) 2003-02-05
JP2003045960A (ja) 2003-02-14
EP1282168A3 (de) 2003-10-22

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP