DE3583091D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3583091D1
DE3583091D1 DE8585109509T DE3583091T DE3583091D1 DE 3583091 D1 DE3583091 D1 DE 3583091D1 DE 8585109509 T DE8585109509 T DE 8585109509T DE 3583091 T DE3583091 T DE 3583091T DE 3583091 D1 DE3583091 D1 DE 3583091D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585109509T
Other languages
English (en)
Inventor
Junichi C O Patent Di Miyamoto
Jun-Ichi C O Patent Tsujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3583091D1 publication Critical patent/DE3583091D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
DE8585109509T 1984-09-21 1985-07-29 Halbleiterspeicheranordnung. Expired - Lifetime DE3583091D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59197925A JPS6177199A (ja) 1984-09-21 1984-09-21 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3583091D1 true DE3583091D1 (de) 1991-07-11

Family

ID=16382557

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585109509T Expired - Lifetime DE3583091D1 (de) 1984-09-21 1985-07-29 Halbleiterspeicheranordnung.

Country Status (4)

Country Link
US (1) US4694427A (de)
EP (1) EP0175102B1 (de)
JP (1) JPS6177199A (de)
DE (1) DE3583091D1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5101379A (en) * 1986-05-27 1992-03-31 Seeq Technology, Incorporated Apparatus for page mode programming of an EEPROM cell array with false loading protection
FR2600809B1 (fr) * 1986-06-24 1988-08-19 Eurotechnique Sa Dispositif de detection du fonctionnement du systeme de lecture d'une cellule-memoire eprom ou eeprom
JPS63251999A (ja) * 1987-04-08 1988-10-19 Mitsubishi Electric Corp 半導体記憶装置
US5313420A (en) 1987-04-24 1994-05-17 Kabushiki Kaisha Toshiba Programmable semiconductor memory
JPH0682520B2 (ja) * 1987-07-31 1994-10-19 株式会社東芝 半導体メモリ
US5022009A (en) * 1988-06-02 1991-06-04 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having reading operation of information by differential amplification
US5003507A (en) * 1988-09-06 1991-03-26 Simon Johnson EPROM emulator for selectively simulating a variety of different paging EPROMs in a test circuit
EP0424172B1 (de) * 1989-10-20 1995-01-18 Fujitsu Limited Nichtflüchtige Halbleiterspeicheranordnung
IT1249809B (it) * 1991-05-10 1995-03-28 St Microelectronics Srl Circuito di lettura a offset di corrente modulata o a sbilanciamento di corrente per celle di memorie programmabili
US5461713A (en) * 1991-05-10 1995-10-24 Sgs-Thomson Microelectronics S.R.L. Current offset sense amplifier of a modulated current or current unbalance type for programmable memories
US5228106A (en) * 1991-05-30 1993-07-13 Integrated Device Technology, Inc. Track-and-regenerate amplifiers and memories using such amplifiers
US5357462A (en) * 1991-09-24 1994-10-18 Kabushiki Kaisha Toshiba Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller
JP3397404B2 (ja) * 1993-08-09 2003-04-14 株式会社日立製作所 半導体記憶装置
GB9423032D0 (en) * 1994-11-15 1995-01-04 Sgs Thomson Microelectronics Bit line sensing in a memory array
US6002270A (en) * 1995-11-09 1999-12-14 Spaceborne, Inc. Synchronous differential logic system for hyperfrequency operation
US6744671B2 (en) * 2000-12-29 2004-06-01 Intel Corporation Kicker for non-volatile memory drain bias
US6924538B2 (en) 2001-07-25 2005-08-02 Nantero, Inc. Devices having vertically-disposed nanofabric articles and methods of making the same
US6706402B2 (en) 2001-07-25 2004-03-16 Nantero, Inc. Nanotube films and articles
US7259410B2 (en) 2001-07-25 2007-08-21 Nantero, Inc. Devices having horizontally-disposed nanofabric articles and methods of making the same
US6835591B2 (en) 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
US6574130B2 (en) 2001-07-25 2003-06-03 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US7566478B2 (en) 2001-07-25 2009-07-28 Nantero, Inc. Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles
US6911682B2 (en) 2001-12-28 2005-06-28 Nantero, Inc. Electromechanical three-trace junction devices
US6919592B2 (en) 2001-07-25 2005-07-19 Nantero, Inc. Electromechanical memory array using nanotube ribbons and method for making same
US6643165B2 (en) 2001-07-25 2003-11-04 Nantero, Inc. Electromechanical memory having cell selection circuitry constructed with nanotube technology
US7176505B2 (en) 2001-12-28 2007-02-13 Nantero, Inc. Electromechanical three-trace junction devices
US6784028B2 (en) 2001-12-28 2004-08-31 Nantero, Inc. Methods of making electromechanical three-trace junction devices
US7335395B2 (en) 2002-04-23 2008-02-26 Nantero, Inc. Methods of using pre-formed nanotubes to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
US7560136B2 (en) 2003-01-13 2009-07-14 Nantero, Inc. Methods of using thin metal layers to make carbon nanotube films, layers, fabrics, ribbons, elements and articles
JP2007200512A (ja) * 2006-01-30 2007-08-09 Renesas Technology Corp 半導体記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4031524A (en) * 1975-10-17 1977-06-21 Teletype Corporation Read-only memories, and readout circuits therefor
US4223394A (en) * 1979-02-13 1980-09-16 Intel Corporation Sensing amplifier for floating gate memory devices
JPS56137587A (en) * 1980-03-31 1981-10-27 Chiyou Lsi Gijutsu Kenkyu Kumiai Dynamic type memory circuit
JPS6014439B2 (ja) * 1980-07-08 1985-04-13 松下電器産業株式会社 リ−ドオンリメモリ回路
DE3177270D1 (de) * 1980-10-15 1992-02-27 Toshiba Kawasaki Kk Halbleiterspeicher mit datenprogrammierzeit.
US4459684A (en) * 1981-06-02 1984-07-10 Texas Instruments Incorporated Nonvolatile JRAM cell using nonvolatile capacitance for information retrieval
JPH10232A (ja) * 1996-06-14 1998-01-06 Toray Ind Inc 粉体の溶解装置および溶解方法

Also Published As

Publication number Publication date
US4694427A (en) 1987-09-15
JPH0249515B2 (de) 1990-10-30
EP0175102A3 (en) 1987-12-16
JPS6177199A (ja) 1986-04-19
EP0175102B1 (de) 1991-06-05
EP0175102A2 (de) 1986-03-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee