DE69324524D1 - Verfahren zur Herstellung eines Halbleiter-Speicherbauteils - Google Patents

Verfahren zur Herstellung eines Halbleiter-Speicherbauteils

Info

Publication number
DE69324524D1
DE69324524D1 DE69324524T DE69324524T DE69324524D1 DE 69324524 D1 DE69324524 D1 DE 69324524D1 DE 69324524 T DE69324524 T DE 69324524T DE 69324524 T DE69324524 T DE 69324524T DE 69324524 D1 DE69324524 D1 DE 69324524D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69324524T
Other languages
English (en)
Other versions
DE69324524T2 (de
Inventor
Hideaki Kuroda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE69324524D1 publication Critical patent/DE69324524D1/de
Application granted granted Critical
Publication of DE69324524T2 publication Critical patent/DE69324524T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
DE69324524T 1992-06-12 1993-06-09 Verfahren zur Herstellung eines Halbleiter-Speicherbauteils Expired - Fee Related DE69324524T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17917492A JP3230696B2 (ja) 1992-06-12 1992-06-12 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
DE69324524D1 true DE69324524D1 (de) 1999-05-27
DE69324524T2 DE69324524T2 (de) 1999-10-28

Family

ID=16061235

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69324524T Expired - Fee Related DE69324524T2 (de) 1992-06-12 1993-06-09 Verfahren zur Herstellung eines Halbleiter-Speicherbauteils

Country Status (5)

Country Link
US (1) US5332687A (de)
EP (1) EP0573996B1 (de)
JP (1) JP3230696B2 (de)
KR (1) KR100286109B1 (de)
DE (1) DE69324524T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0121297B1 (en) * 1992-04-16 1997-11-15 Fujitsu Ltd Semiconductor device and process of producing the same
DE69531089T2 (de) * 1994-11-07 2004-05-13 Texas Instruments Inc., Dallas Verbesserungen an oder in Bezug auf halbleitende Anordnungen
US5872060A (en) * 1995-11-02 1999-02-16 Texas Instruments Incorporated Semiconductor device manufacturing method
US5786249A (en) * 1996-03-07 1998-07-28 Micron Technology, Inc. Method of forming dram circuitry on a semiconductor substrate
KR19980060632A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 캐패시터 제조방법
US5930618A (en) * 1997-08-04 1999-07-27 United Microelectronics Corp. Method of Making High-K Dielectrics for embedded DRAMS
JPH11345946A (ja) 1998-06-01 1999-12-14 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6110818A (en) * 1998-07-15 2000-08-29 Philips Electronics North America Corp. Semiconductor device with gate electrodes for sub-micron applications and fabrication thereof
US6208004B1 (en) 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
KR20010057669A (ko) 1999-12-23 2001-07-05 한신혁 적층형 캐패시터를 갖는 반도체 장치의 제조 방법
US7838427B2 (en) * 2006-01-13 2010-11-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for planarization
US8607782B2 (en) * 2008-01-14 2013-12-17 Allen I Bronstein Stretched membrane solar collector with bearing edge

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642162A (en) * 1986-01-02 1987-02-10 Honeywell Inc. Planarization of dielectric layers in integrated circuits
US4836885A (en) * 1988-05-03 1989-06-06 International Business Machines Corporation Planarization process for wide trench isolation
JP2671466B2 (ja) * 1988-12-15 1997-10-29 富士通株式会社 半導体装置及びその製造方法
JP2768758B2 (ja) * 1989-10-04 1998-06-25 株式会社東芝 半導体記憶装置及びその製造方法
US5030585A (en) * 1990-03-22 1991-07-09 Micron Technology, Inc. Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation
JP2519569B2 (ja) * 1990-04-27 1996-07-31 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2524862B2 (ja) * 1990-05-01 1996-08-14 三菱電機株式会社 半導体記憶装置およびその製造方法
US5240872A (en) * 1990-05-02 1993-08-31 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers
JPH0482263A (ja) * 1990-07-25 1992-03-16 Sharp Corp 半導体記憶装置

Also Published As

Publication number Publication date
JP3230696B2 (ja) 2001-11-19
EP0573996B1 (de) 1999-04-21
EP0573996A1 (de) 1993-12-15
US5332687A (en) 1994-07-26
KR940001421A (ko) 1994-01-11
DE69324524T2 (de) 1999-10-28
KR100286109B1 (ko) 2001-04-16
JPH05347389A (ja) 1993-12-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee