DE69331816T2 - Verfahren zur Herstellung eines Halbleitersubstrats - Google Patents
Verfahren zur Herstellung eines HalbleitersubstratsInfo
- Publication number
- DE69331816T2 DE69331816T2 DE69331816T DE69331816T DE69331816T2 DE 69331816 T2 DE69331816 T2 DE 69331816T2 DE 69331816 T DE69331816 T DE 69331816T DE 69331816 T DE69331816 T DE 69331816T DE 69331816 T2 DE69331816 T2 DE 69331816T2
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor substrate
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/96—Porous semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Electromagnetism (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Element Separation (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04058492A JP3300857B2 (ja) | 1992-01-31 | 1992-01-31 | 貼り合わせ半導体ウエハ及びその製造方法 |
JP04630492A JP3237889B2 (ja) | 1992-01-31 | 1992-01-31 | 半導体基体及びその作製方法 |
JP04630592A JP3237890B2 (ja) | 1992-01-31 | 1992-01-31 | 半導体基体及びその作製方法 |
JP04630392A JP3157030B2 (ja) | 1992-01-31 | 1992-01-31 | 半導体基体とその作製方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69331816D1 DE69331816D1 (de) | 2002-05-23 |
DE69331816T2 true DE69331816T2 (de) | 2002-08-29 |
Family
ID=27460917
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69331816T Expired - Fee Related DE69331816T2 (de) | 1992-01-31 | 1993-01-29 | Verfahren zur Herstellung eines Halbleitersubstrats |
Country Status (3)
Country | Link |
---|---|
US (1) | US5439843A (de) |
EP (2) | EP1179842A3 (de) |
DE (1) | DE69331816T2 (de) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0553852B1 (de) * | 1992-01-30 | 2003-08-20 | Canon Kabushiki Kaisha | Verfahren zur Herstellung eines Halbleitersubstrates |
TW330313B (en) * | 1993-12-28 | 1998-04-21 | Canon Kk | A semiconductor substrate and process for producing same |
JP2669368B2 (ja) * | 1994-03-16 | 1997-10-27 | 日本電気株式会社 | Si基板上化合物半導体積層構造の製造方法 |
US5510633A (en) * | 1994-06-08 | 1996-04-23 | Xerox Corporation | Porous silicon light emitting diode arrays and method of fabrication |
EP0899574B1 (de) | 1997-02-21 | 2004-07-21 | Matsushita Electric Works, Ltd. | Beschleunigungsmesselement sowie verfahren zu seiner herstellung |
CA2231625C (en) * | 1997-03-17 | 2002-04-02 | Canon Kabushiki Kaisha | Semiconductor substrate having compound semiconductor layer, process for its production, and electronic device fabricated on semiconductor substrate |
EP0867919B1 (de) * | 1997-03-26 | 2004-09-08 | Canon Kabushiki Kaisha | Halbleitersubstrat und Verfahren zu dessen Herstellung |
CA2233096C (en) | 1997-03-26 | 2003-01-07 | Canon Kabushiki Kaisha | Substrate and production method thereof |
FR2775121B1 (fr) * | 1998-02-13 | 2000-05-05 | Picogiga Sa | Procede de fabrication de substrats en film mince de materiau semiconducteur, structures epitaxiales de materiau semiconducteur formees sur de tels substrats, et composants obtenus a partir de ces structures |
US7227176B2 (en) | 1998-04-10 | 2007-06-05 | Massachusetts Institute Of Technology | Etch stop layer system |
US6750130B1 (en) * | 2000-01-20 | 2004-06-15 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6414333B1 (en) * | 2000-03-10 | 2002-07-02 | Samsung Electronics Co., Ltd. | Single electron transistor using porous silicon |
US6573126B2 (en) | 2000-08-16 | 2003-06-03 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
EP1217663A1 (de) * | 2000-12-21 | 2002-06-26 | Interuniversitair Micro-Elektronica Centrum | Herstellungsverfahren einer Halbleiterschicht auf einem Substrat |
EP1220330B1 (de) * | 2000-12-21 | 2012-03-14 | Imec | Verfahren zur Herstellung einer Halbleiterschicht auf ein Substrat |
US6602760B2 (en) | 2000-12-21 | 2003-08-05 | Interuniversitair Microelektronica Centrum (Imec) | Method of producing a semiconductor layer on a substrate |
US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
KR100387242B1 (ko) * | 2001-05-26 | 2003-06-12 | 삼성전기주식회사 | 반도체 발광소자의 제조방법 |
US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US7307273B2 (en) | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US20030227057A1 (en) | 2002-06-07 | 2003-12-11 | Lochtefeld Anthony J. | Strained-semiconductor-on-insulator device structures |
WO2004099473A1 (en) * | 2003-05-06 | 2004-11-18 | Canon Kabushiki Kaisha | Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
US7380318B2 (en) * | 2003-11-13 | 2008-06-03 | Canon Kabushiki Kaisha | Method of manufacturing liquid discharge head |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US7422956B2 (en) * | 2004-12-08 | 2008-09-09 | Advanced Micro Devices, Inc. | Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers |
JP4654458B2 (ja) * | 2004-12-24 | 2011-03-23 | リコープリンティングシステムズ株式会社 | シリコン部材の陽極接合法及びこれを用いたインクジェットヘッド製造方法並びにインクジェットヘッド及びこれを用いたインクジェット記録装置 |
US7244630B2 (en) * | 2005-04-05 | 2007-07-17 | Philips Lumileds Lighting Company, Llc | A1InGaP LED having reduced temperature dependence |
EP2091070A1 (de) * | 2008-02-13 | 2009-08-19 | S.O.I. TEC Silicon | Verfahren zur Herstellung einer Halbleitersubstratoberfläche |
US8815618B2 (en) | 2008-08-29 | 2014-08-26 | Tsmc Solid State Lighting Ltd. | Light-emitting diode on a conductive substrate |
FR2953328B1 (fr) * | 2009-12-01 | 2012-03-30 | S O I Tec Silicon On Insulator Tech | Heterostructure pour composants electroniques de puissance, composants optoelectroniques ou photovoltaiques |
US8723335B2 (en) | 2010-05-20 | 2014-05-13 | Sang-Yun Lee | Semiconductor circuit structure and method of forming the same using a capping layer |
CN103390591B (zh) * | 2013-07-22 | 2015-11-25 | 中国科学院半导体研究所 | 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 |
US20150144975A1 (en) * | 2013-11-25 | 2015-05-28 | Epistar Corporation | Light-emitting device |
US10032870B2 (en) * | 2015-03-12 | 2018-07-24 | Globalfoundries Inc. | Low defect III-V semiconductor template on porous silicon |
US11355340B2 (en) * | 2019-07-19 | 2022-06-07 | Iqe Plc | Semiconductor material having tunable permittivity and tunable thermal conductivity |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3997381A (en) * | 1975-01-10 | 1976-12-14 | Intel Corporation | Method of manufacture of an epitaxial semiconductor layer on an insulating substrate |
SE409553B (sv) * | 1976-10-04 | 1979-08-27 | Aga Ab | Sett vid fraktionering av en gasblandning under utnyttjande av minst tva beddar |
JPS5516464A (en) * | 1978-07-21 | 1980-02-05 | Nec Corp | Method of forming wafer for semiconductor device |
JPS57149749A (en) * | 1981-03-12 | 1982-09-16 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
US4380865A (en) * | 1981-11-13 | 1983-04-26 | Bell Telephone Laboratories, Incorporated | Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation |
JPS58197740A (ja) * | 1982-04-23 | 1983-11-17 | Jido Keisoku Gijutsu Kenkiyuukumiai | 集積回路用基板の製造方法 |
JPS5918657A (ja) * | 1982-07-21 | 1984-01-31 | Jido Keisoku Gijutsu Kenkiyuukumiai | 集積回路用基板の製造方法 |
JPS5918656A (ja) * | 1982-07-21 | 1984-01-31 | Jido Keisoku Gijutsu Kenkiyuukumiai | 集積回路用基板の製造方法 |
US4459181A (en) * | 1982-09-23 | 1984-07-10 | Eaton Corporation | Semiconductor pattern definition by selective anodization |
JPS59111321A (ja) * | 1982-12-17 | 1984-06-27 | Asahi Chem Ind Co Ltd | 化合物半導体薄膜構造体及びその製造方法 |
JPS59144149A (ja) * | 1983-02-08 | 1984-08-18 | Toko Inc | 誘電体分離基板の製造方法 |
US4649627A (en) * | 1984-06-28 | 1987-03-17 | International Business Machines Corporation | Method of fabricating silicon-on-insulator transistors with a shared element |
JP2505736B2 (ja) * | 1985-06-18 | 1996-06-12 | キヤノン株式会社 | 半導体装置の製造方法 |
JPS61292935A (ja) * | 1985-06-21 | 1986-12-23 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH0666263B2 (ja) * | 1985-12-16 | 1994-08-24 | 日本電気株式会社 | Iii−v化合物半導体/絶縁体/iii−v化合物半導体積層構造 |
JPH0828470B2 (ja) * | 1986-11-07 | 1996-03-21 | キヤノン株式会社 | 半導体メモリ装置 |
CA1321121C (en) * | 1987-03-27 | 1993-08-10 | Hiroyuki Tokunaga | Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same |
US4743568A (en) * | 1987-07-24 | 1988-05-10 | Motorola Inc. | Multilevel interconnect transfer process |
US4891329A (en) * | 1988-11-29 | 1990-01-02 | University Of North Carolina | Method of forming a nonsilicon semiconductor on insulator structure |
US5013681A (en) * | 1989-09-29 | 1991-05-07 | The United States Of America As Represented By The Secretary Of The Navy | Method of producing a thin silicon-on-insulator layer |
JPH03223106A (ja) * | 1990-01-26 | 1991-10-02 | Mitsubishi Electric Corp | Siのエッチング方法 |
JPH0412098A (ja) * | 1990-04-27 | 1992-01-16 | Sumitomo Electric Ind Ltd | 化合物半導体及びその成長方法 |
JPH0412092A (ja) * | 1990-04-27 | 1992-01-16 | Sumitomo Electric Ind Ltd | 化合物半導体及びその成長方法 |
CA2069038C (en) * | 1991-05-22 | 1997-08-12 | Kiyofumi Sakaguchi | Method for preparing semiconductor member |
JP3250673B2 (ja) * | 1992-01-31 | 2002-01-28 | キヤノン株式会社 | 半導体素子基体とその作製方法 |
-
1993
- 1993-01-29 EP EP01119915A patent/EP1179842A3/de not_active Withdrawn
- 1993-01-29 EP EP93101417A patent/EP0553856B1/de not_active Expired - Lifetime
- 1993-01-29 DE DE69331816T patent/DE69331816T2/de not_active Expired - Fee Related
-
1994
- 1994-09-06 US US08/301,263 patent/US5439843A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1179842A3 (de) | 2002-09-04 |
EP0553856A2 (de) | 1993-08-04 |
DE69331816D1 (de) | 2002-05-23 |
US5439843A (en) | 1995-08-08 |
EP1179842A2 (de) | 2002-02-13 |
EP0553856B1 (de) | 2002-04-17 |
EP0553856A3 (en) | 1997-10-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |