CN103390591B - 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 - Google Patents
硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 Download PDFInfo
- Publication number
- CN103390591B CN103390591B CN201310306968.2A CN201310306968A CN103390591B CN 103390591 B CN103390591 B CN 103390591B CN 201310306968 A CN201310306968 A CN 201310306968A CN 103390591 B CN103390591 B CN 103390591B
- Authority
- CN
- China
- Prior art keywords
- layer
- germanium
- silica
- groove
- nmosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 104
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 52
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 61
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 61
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 42
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000011435 rock Substances 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 238000005516 engineering process Methods 0.000 claims abstract description 10
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims abstract description 10
- 230000006911 nucleation Effects 0.000 claims abstract description 5
- 238000010899 nucleation Methods 0.000 claims abstract description 5
- 238000004140 cleaning Methods 0.000 claims abstract description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 4
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 claims description 2
- 239000012895 dilution Substances 0.000 claims description 2
- 238000010790 dilution Methods 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 claims description 2
- KTWOOEGAPBSYNW-UHFFFAOYSA-N ferrocene Chemical group [Fe+2].C=1C=C[CH-]C=1.C=1C=C[CH-]C=1 KTWOOEGAPBSYNW-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 238000004377 microelectronic Methods 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02433—Crystal orientation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02461—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Plasma & Fusion (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Recrystallisation Techniques (AREA)
Abstract
一种硅基高迁移率III-V/Ge沟道的CMOS制备方法,包括:在硅衬底上生长锗层;第一次退火后,在锗层上依次生长低温成核砷化镓层、高温砷化镓层、在生长半绝缘InGaP层和砷化镓盖层,形成样品;将样品的砷化镓盖层进行砷化镓抛光工艺,将样品进行第二次退火后生长nMOSFET结构;在nMOSFET结构的表面,选区ICP刻蚀,从nMOSFET结构向下刻蚀到锗层,形成凹槽,并在凹槽内及nMOSFET结构的表面PECVD生长二氧化硅层;在选区刻蚀的位置再次进行ICP刻蚀二氧化硅层到锗层,形成沟槽;清洗样品,采用超高真空化学气相沉积的方法,在沟槽内生长锗成核层和锗顶层;对锗顶层进行抛光,并去掉nMOSFET结构上的部分二氧化硅层;在nMOSFET结构和锗顶层上进行源、漏和栅的CMOS工艺完成器件的制备。
Description
技术领域
本发明涉及微电子领域,将超高真空化学气相沉积与MOCVD结合,并且利用高深宽比限制技术,实现硅基高迁移率III-V/Ge沟道材料同时集成,应用于硅基III-V/Ge沟道CMOS器件中。
背景技术
特征尺寸下降到22nm节点,以硅CMOS技术为基础的集成电路技术遵循摩尔定律通过缩小器件的特征尺寸来实现提高芯片的工作速度、增加集成度以及降低成本的目的,出现了困难。纳米加工工艺成本的增加,短沟道效应降低了栅控能力,以及硅材料本身迁移率的限制等因素否定了继续缩小器件特征尺寸的可能性。因此,各种可能的方案不断产生,Intel于2012年4月在中国推出的第三代IvyBridge处理器为采用了3D三栅Fin-FET的22nm制程工艺。而通过采用III-V/Ge高迁移率沟道是另一种解决方案。
III-V族化合物半导体的电子迁移率远大于硅(GaAs、InAs材料的电子迁移率分别可达到9000cm2V-1·s-1、40000cm2V-1·s-1,而硅的只有1300cm2V-1·s-1),它们在低场和高场下都具有优异的电子输运性能,是超高速、低功耗nMOS的理想沟道材料;同时锗的空穴迁移率(1800cm2V-1·s-1)也大于硅(500cm2V-1·s-1)。为了应对集成电路技术所面临的严峻挑战,采用与硅工艺兼容的高迁移率III-V族半导体材料以及锗材料代替应变硅沟道,以大幅提高逻辑电路的开关速度并实现低功耗工作研究已成为近期全球微电子领域的前沿和热点。
在Si衬底上外延高质量的III-V族半导体材料以及锗材料是制备大面积低成本Si基高迁移率CMOS器件的前提。硅基锗材料的外延和器件的研究一直是微电子和光电子的一个重点,采用超高真空化学气相外延(UHVCVD)可以获得高质量平整表面的锗层。另一方面,GaAs是研究较为成熟的III-V族半导体材料,但是进行硅基GaAs的外延时会遇到很多问题。Si和GaAs的晶格失配较大(4.1%),热失配较大(Si和GaAs的热膨胀系数分别为2.59×10-6K-1,5.75×10-6K-1),因此在异质外延时会产生大量的位错。同时,由于极性材料在非极性衬底上外延以及衬底台阶的存在,外延层中会产生大量的反相畴(Anti-phasedomain,APD),反相畴边界(Anti-phaseboundary,APB)是载流子的散射和复合中心,同时在禁带引入缺陷能级。这些位错和反相畴边界会一直延伸到外延层的表面,严重影响了外延层的质量。国际上Si基III-V族半导体材料的生长一般通过锗层来过渡,然后以MOCVD控制GaAs层的生长来实现高质量的III-V族层。
但是将锗材料和III-V化合物半导体材料集成在同一个硅衬底上并且实现CMOS功能的工艺方案并未实现。目前,唯一接近目标的是将InGaAs沟道通过键合到锗衬底上实现了同时集成nMOSFET和pMOSFET的原型锗基CMOS器件(M.Yokoyamaetal,Appl.Phys.Express5,076501,2012)。解决III-V族N型沟道和锗P型沟道的另外一个方案是采用硅基选区外延的办法,但是选区外延获得的III-V或者锗材料的质量均不理想(尺寸微米级别),该方案实现的可能性有待考察;同时极小尺寸选区外延通过高的深宽比限制(aspectratiotrapping,ART)近年来获得很大的关注(J.S.Parketal,Appl.Phys.Lett.90,052113,2007),在SiO2沟槽中,外延材料是沿着{311}和{111}晶族组成的晶面(平行于沟槽的方向)进行生长的,Si-Ge界面处的失配位错等缺陷一般是顺沿着外延层的生长方向延伸的。这样,当这些失配位错遇到SiO2壁时就受到阻挡,不能延伸到顶层。但是通过该方案获得硅基高迁移率N、P沟道的集成尚未实现。
本方法中采用超高真空化学气相沉积从硅衬底过渡到锗层,通过底层弛豫锗来消除4%的应变,由于砷化镓与锗的晶格失配只有800ppm,从锗层到砷化镓,减少了失配位错的产生,采用高低温砷化镓层的配合来解决反向畴以及缺陷的问题。另外,为了使高迁移率的III-V族半导体与锗区集成在硅衬底上,采用了选区刻蚀以及ART外延Ge材料的方法;然后通过源漏栅工艺,最终实现高迁移率InGaAs的N型沟道和锗的P型沟道的硅基集成。
发明内容
本发明的目的在于,提供一种硅基高迁移率III-V/Ge沟道的CMOS制备方法,来获得将III-V族半导体高电子迁移率特性和Ge高空穴迁移率特性的高速硅基CMOS。
本发明提供一种硅基高迁移率III-V/Ge沟道的CMOS制备方法,包括以下步骤:
步骤1:在清洗好的硅衬底上,采用超高真空化学气相沉积生长锗层;
步骤2:将硅衬底立即放入MOCVD反应室中,第一次退火后,在锗层上依次生长低温成核砷化镓层、高温砷化镓层、在生长半绝缘InGaP层和砷化镓盖层,形成样品;
步骤3:将样品取出,对砷化镓盖层进行砷化镓抛光工艺,并清洗MOCVD反应室和样品舟,将样品清洗后放入MOCVD反应室,第二次退火后生长nMOSFET结构;
步骤4:在nMOSFET结构的表面,选区ICP刻蚀,从nMOSFET结构向下刻蚀到锗层,形成凹槽,并在凹槽内及nMOSFET结构的表面PECVD生长二氧化硅层;
步骤5:在选区刻蚀的位置再次进行ICP刻蚀二氧化硅层到锗层,形成沟槽;
步骤6:清洗样品,采用超高真空化学气相沉积的方法,在沟槽内生长锗成核层和锗顶层;
步骤7:对锗顶层进行抛光,并去掉nMOSFET结构上的部分二氧化硅层;
步骤8:在nMOSFET结构和锗顶层上进行源、漏和栅的CMOS工艺完成器件的制备。
本发明的有益效果是:
1、采用锗层从硅过渡到III-V层,然后通过低温的砷化镓层获得高的晶格质量;
2、采用超薄层III-V族层抛光,获得平整III-V族表面;
3、结合ART方法实现了高质量Ge材料与III-V族材料的硅基集成。
附图说明
为进一步说明本发明的具体技术内容,以下结合实例及附图对本发明坐进一步描述,其中:
图1是本发明的制备流程图示意图;
图2至图9是本发明各步骤的结构示意图。
具体实施方式
请参阅图1并结合参阅图2至图9,本发明提供一种硅基高迁移率III-V/Ge沟道的CMOS制备方法,包括以下步骤:
步骤1:在清洗好的硅衬底1上,采用超高真空化学气相沉积生长锗层2(参阅图2)。该硅衬底1为偏[011]方向4°的(100)衬底,衬底偏角为了保证在最终的锗层表面形成原子台阶来抑制砷化镓成核时的反向畴,衬底偏角一般在3°到6°;通过锗层来实现晶格常数向砷化镓的过渡,锗层的缺陷密度需要在1×106cm-2以下,表面粗糙度RMS小于0.5nm。
步骤2:将硅衬底1立即放入MOCVD反应室中,第一次退火后,在锗层2上依次生长低温成核砷化镓层3、高温砷化镓层4、在生长半绝缘InGaP层5和砷化镓盖层6(参阅图2),形成样品。其中,第一次退火的温度大于700℃,时间为20-30分钟;之后的第二次退火的温度和生长高温砷化镓层4、半绝缘InGaP层5、砷化镓盖层6和nMOSFET结构7是相同的,均为620-660℃之间,第二次退火在砷烷的保护气氛下进行。生长半绝缘InGaP层5与锗层2是晶格匹配的,其生长速率是0.1nm/s-0.25nm/s,V/III为75-125。其中生长半绝缘InGaP层5时掺杂剂为二茂铁,其流量与半绝缘InGaP层5所用的III族源TMIn和TMGa的流量之和的比大约为1∶1000,数量级在1×10-8mol/min。
步骤3:将样品取出,对砷化镓盖层6进行砷化镓抛光工艺,并清洗MOCVD反应室和样品舟,将样品清洗后放入MOCVD反应室,第二次退火后生长nMOSFET结构7(参阅图2)。其中,砷化镓盖层6的厚度为70-100nm,对其进行抛光时抛去的厚度在50nm以下,达到的粗糙度为0.5nm以下。其中nMOSFET结构7包括依次生长的砷化镓缓冲层、Al0.3Ga0.7As势垒层、In0.25Ga0.75As沟道层、In0.49Ga0.51P刻蚀停止层和GaAs掺杂接触层,并且对Al0.3Ga0.7As势垒层进行硅的delta掺杂,该层为nMOSFET的一种结构,可以优化为其他参数。
步骤4:在nMOSFET结构7的表面,选区ICP刻蚀,从nMOSFET结构7向下刻蚀到锗层2,形成凹槽(参阅图3),并在凹槽内及nMOSFET结构7的表面PECVD生长二氧化硅层8(参阅图3)。其中,选区ICP刻蚀凹槽的图形为平行的,槽宽为500nm,凹槽的间距为500-1000nm,凹槽底部向下刻蚀掉锗层2一定厚度50-100nm;二氧化硅层8在凹槽内的顶部与nMOSFET结构7的顶部持平(参阅图4)。
步骤5:在选区刻蚀的位置再次进行ICP刻蚀二氧化硅层8到锗层2,形成沟槽(参阅图5)。其中,ICP刻蚀二氧化硅层8的刻蚀沟槽的槽宽为100-200nm,槽两侧二氧化硅的厚度相同,沟槽的深度与III-V族材料的厚度有关,但是需要保证沟槽的深宽比大于2,来实现ART方法限制Ge层的位错;沟槽两侧的二氧化硅作为绝缘隔离墙。
步骤6:清洗样品,采用超高真空化学气相沉积的方法,在沟槽内生长锗成核层9和锗顶层10(参阅图6)。其中,锗顶层10的高度高于二氧化硅层8在凹槽内的上表面,高出二氧化硅层8的上表面100-150nm,沟槽内的锗层完全填满。
步骤7:对锗顶层10进行抛光,并去掉nMOSFET结构7上的部分二氧化硅层8(参阅图7)。其中对锗顶层10进行抛光前进行稀释HF腐蚀,使得nMOSFET层7顶部的二氧化硅层8的厚度减少至50nm,抛光锗顶层10与二氧化硅层8齐平(参阅图8)。
步骤8:在nMOSFET结构7和锗顶层10上进行源、漏和栅的CMOS工艺(参阅图9)完成器件的制备。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种硅基高迁移率III-V/Ge沟道的CMOS制备方法,包括以下步骤:
步骤1:在清洗好的硅衬底上,采用超高真空化学气相沉积生长锗层;
步骤2:将硅衬底立即放入MOCVD反应室中,第一次退火后,在锗层上依次生长低温成核砷化镓层、高温砷化镓层、在生长半绝缘InGaP层和砷化镓盖层,形成样品,该第一次退火的温度大于700℃,时间为20-30分钟;
步骤3:将样品取出,对砷化镓盖层进行砷化镓抛光工艺,并清洗MOCVD反应室和样品舟,将样品清洗后放入MOCVD反应室,第二次退火后生长nMOSFET结构,该第二次退火的温度和生长高温砷化镓层、半绝缘InGaP层、砷化镓盖层和nMOSFET结构是相同的,均为620-660℃之间,第二次退火在砷烷的保护气氛下进行;
步骤4:在nMOSFET结构的表面,选区ICP刻蚀,从nMOSFET结构向下刻蚀到锗层,形成凹槽,并在凹槽内及nMOSFET结构的表面PECVD生长二氧化硅层;
步骤5:在选区刻蚀的位置再次进行ICP刻蚀二氧化硅层到锗层,形成沟槽;
步骤6:清洗样品,采用超高真空化学气相沉积的方法,在沟槽内生长锗成核层和锗顶层;
步骤7:对锗顶层进行抛光,并去掉nMOSFET结构上的部分二氧化硅层;
步骤8:在nMOSFET结构和锗顶层上进行源、漏和栅的CMOS工艺,该nMOSFET结构包括依次生长的砷化镓缓冲层、Al0.3Ga0.7As势垒层、In0.25Ga0.75As沟道层、In0.49Ga0.51P刻蚀停止层和GaAs掺杂接触层,并且对Al0.3Ga0.7As势垒层进行硅的delta掺杂,完成器件的制备。
2.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中硅衬底为偏[011]方向4°的(100)衬底。
3.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中生长半绝缘InGaP层与锗层是晶格匹配的,其生长速率是0.1nm/s-0.25nm/s。
4.根据权利要求3所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中生长半绝缘InGaP层时掺杂剂为二茂铁,其流量与半绝缘InGaP层所用的III族源TMIn和TMGa的流量之和的比为1∶1000,数量级在1×10-8mol/min。
5.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中砷化镓盖层的厚度为70-100nm,对其进行抛光时抛去的厚度在50nm以下,达到的粗糙度为0.5nm以下。
6.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中选区ICP刻蚀凹槽的图形为平行的,槽宽为500nm,凹槽的间距为500-1000nm。
7.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中二氧化硅层在凹槽内的顶部与nMOSFET结构的顶部持平。
8.根据权利要求7所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中ICP刻蚀二氧化硅层的刻蚀沟槽的槽宽为200nm,槽两侧二氧化硅的厚度相同。
9.根据权利要求1所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中锗顶层的高度高于二氧化硅层8在凹槽内的上表面,高出二氧化硅层的上表面100nm。
10.根据权利要求9所述的硅基高迁移率III-V/Ge沟道的CMOS制备方法,其中对锗顶层进行抛光前进行稀释HF腐蚀,使得nMOSFET层顶部的二氧化硅层的厚度减少至50nm,抛光锗顶层与二氧化硅层齐平。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310306968.2A CN103390591B (zh) | 2013-07-22 | 2013-07-22 | 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 |
US14/222,392 US8987141B2 (en) | 2013-07-22 | 2014-03-21 | Method of manufacturing Si-based high-mobility group III-V/Ge channel CMOS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310306968.2A CN103390591B (zh) | 2013-07-22 | 2013-07-22 | 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103390591A CN103390591A (zh) | 2013-11-13 |
CN103390591B true CN103390591B (zh) | 2015-11-25 |
Family
ID=49534822
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310306968.2A Active CN103390591B (zh) | 2013-07-22 | 2013-07-22 | 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8987141B2 (zh) |
CN (1) | CN103390591B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102210325B1 (ko) | 2013-09-06 | 2021-02-01 | 삼성전자주식회사 | Cmos 소자 및 그 제조 방법 |
CN106910716B (zh) | 2015-12-22 | 2021-10-15 | Imec 非营利协会 | Si基高迁移率CMOS装置的制造方法及所得装置 |
US10593600B2 (en) | 2016-02-24 | 2020-03-17 | International Business Machines Corporation | Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap |
US10062693B2 (en) * | 2016-02-24 | 2018-08-28 | International Business Machines Corporation | Patterned gate dielectrics for III-V-based CMOS circuits |
US11244315B2 (en) | 2017-03-21 | 2022-02-08 | Intelligent Technologies International, Inc. | Authentication system for controlling access and use based on heartbeat shape |
TWI660465B (zh) * | 2017-07-28 | 2019-05-21 | 新唐科技股份有限公司 | 半導體元件及其製造方法 |
EP3809457A1 (en) | 2019-10-16 | 2021-04-21 | IMEC vzw | Co-integration of iii-v devices with group iv devices |
CN111238461B (zh) * | 2020-03-09 | 2022-05-06 | 中国建筑材料科学研究总院有限公司 | 一种谐振子及其制备方法 |
CN111681950B (zh) * | 2020-07-31 | 2023-10-24 | 广东省大湾区集成电路与系统应用研究院 | 一种半导体结构及其制造方法 |
CN115084308B (zh) * | 2021-03-15 | 2023-07-21 | 中国科学院物理研究所 | 锗衬底-砷化镓/锗异质结薄膜复合结构及其制法和应用 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102570305A (zh) * | 2012-03-06 | 2012-07-11 | 中国科学院半导体研究所 | 基于硅基赝砷化镓衬底的850nm激光器的制备方法 |
CN102664166A (zh) * | 2012-05-31 | 2012-09-12 | 中国科学院上海微系统与信息技术研究所 | 一种cmos器件及其制作方法 |
CN102790054A (zh) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的半导体结构及其制备方法 |
CN103107096A (zh) * | 2013-03-05 | 2013-05-15 | 中国科学院半导体研究所 | 一种硅基III-V族nMOS器件的制作方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4952527A (en) * | 1988-02-19 | 1990-08-28 | Massachusetts Institute Of Technology | Method of making buffer layers for III-V devices using solid phase epitaxy |
US5411914A (en) * | 1988-02-19 | 1995-05-02 | Massachusetts Institute Of Technology | III-V based integrated circuits having low temperature growth buffer or passivation layers |
US5084409A (en) * | 1990-06-26 | 1992-01-28 | Texas Instruments Incorporated | Method for patterned heteroepitaxial growth |
EP1179842A3 (en) * | 1992-01-31 | 2002-09-04 | Canon Kabushiki Kaisha | Semiconductor substrate and method for preparing same |
JP2001127326A (ja) * | 1999-08-13 | 2001-05-11 | Oki Electric Ind Co Ltd | 半導体基板及びその製造方法、並びに、この半導体基板を用いた太陽電池及びその製造方法 |
US6858522B1 (en) * | 2000-09-28 | 2005-02-22 | Skyworks Solutions, Inc. | Electrical contact for compound semiconductor device and method for forming same |
WO2003010805A2 (en) * | 2001-07-23 | 2003-02-06 | Motorola, Inc. | Complementary iii-v structures and devices |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
JP4610858B2 (ja) * | 2003-02-12 | 2011-01-12 | 住友化学株式会社 | 化合物半導体エピタキシャル基板 |
TW200905922A (en) * | 2007-07-30 | 2009-02-01 | Juh-Yuh Su | Reusable substrate structure and method of handling the same |
US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8193523B2 (en) * | 2009-12-30 | 2012-06-05 | Intel Corporation | Germanium-based quantum well devices |
TW201301481A (zh) * | 2011-06-23 | 2013-01-01 | Kopin Corp | 雙極高電子遷移率電晶體及其形成方法 |
US20130048061A1 (en) * | 2011-08-24 | 2013-02-28 | International Business Machines Corporation | Monolithic multi-junction photovoltaic cell and method |
KR101805634B1 (ko) * | 2011-11-15 | 2017-12-08 | 삼성전자 주식회사 | Ⅲ-ⅴ족 배리어를 포함하는 반도체 소자 및 그 제조방법 |
JP6018501B2 (ja) * | 2012-12-27 | 2016-11-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
-
2013
- 2013-07-22 CN CN201310306968.2A patent/CN103390591B/zh active Active
-
2014
- 2014-03-21 US US14/222,392 patent/US8987141B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102790054A (zh) * | 2011-05-16 | 2012-11-21 | 中国科学院上海微系统与信息技术研究所 | 锗和iii-v混合共平面的半导体结构及其制备方法 |
CN102570305A (zh) * | 2012-03-06 | 2012-07-11 | 中国科学院半导体研究所 | 基于硅基赝砷化镓衬底的850nm激光器的制备方法 |
CN102664166A (zh) * | 2012-05-31 | 2012-09-12 | 中国科学院上海微系统与信息技术研究所 | 一种cmos器件及其制作方法 |
CN103107096A (zh) * | 2013-03-05 | 2013-05-15 | 中国科学院半导体研究所 | 一种硅基III-V族nMOS器件的制作方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103390591A (zh) | 2013-11-13 |
US8987141B2 (en) | 2015-03-24 |
US20150024601A1 (en) | 2015-01-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103390591B (zh) | 硅基高迁移率Ⅲ-V/Ge沟道的CMOS制备方法 | |
US9984872B2 (en) | Fabrication and structures of crystalline material | |
US9640395B2 (en) | Reduction of edge effects from aspect ratio trapping | |
CN103258796B (zh) | 硅基高迁移率沟道cmos的制备方法 | |
CN101790790B (zh) | Si衬底上的高空穴迁移率p沟道Ge晶体管结构 | |
EP2299475A1 (en) | Improved fabrication and structures of crystalline material | |
CN103811305B (zh) | 一种硅基半绝缘砷化镓衬底的制备方法 | |
CN102324436B (zh) | 大失配硅基衬底锑化物高电子迁移率晶体管及制造方法 | |
CN103107096B (zh) | 一种硅基III-V族nMOS器件的制作方法 | |
CN102107852B (zh) | 半导体纳米结构和制造方法及其应用 | |
CN109427538B (zh) | 一种异质结构的制备方法 | |
CN103117222B (zh) | ART结构沟槽内生长GaAs材料HEMT器件的方法 | |
CN103311106B (zh) | 低表面粗糙度的硅基砷化镓材料的制备方法 | |
CN103346092B (zh) | 硅基高迁移率InGaAs沟道的环栅MOSFET制备方法 | |
CN102534768B (zh) | 制备硅基砷化镓材料的方法 | |
CN103065973B (zh) | 在Si基上制备InP基n-MOS器件的方法 | |
CN103177971A (zh) | 基于ART结构的硅基沟槽内生长GaAs材料的NMOS器件 | |
CN103137477B (zh) | 在Si基上制备InP基HEMT的方法 | |
CN102243994B (zh) | 倒v型二氧化硅沟槽结构生长硅基砷化镓材料的方法 | |
Clavelier et al. | Review of some critical aspects of Ge and GeOI substrates | |
Waldron et al. | Integration of III-V on Si for high-mobility CMOS | |
CN102543693B (zh) | 锗基赝砷化镓衬底的制备方法 | |
Caymax et al. | Epitaxy of III–V based channels on Si and transistor integration for 12-10nm node CMOS | |
CN102751293B (zh) | 一种SOI三应变平面BiCMOS集成器件及制备方法 | |
Layer et al. | Selective Area Growth of InP on On-Axis Si (001) Substrates with Suppressed Antiphase Boundary Formation |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |