CN102790054A - 锗和iii-v混合共平面的半导体结构及其制备方法 - Google Patents

锗和iii-v混合共平面的半导体结构及其制备方法 Download PDF

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CN102790054A
CN102790054A CN2011101263941A CN201110126394A CN102790054A CN 102790054 A CN102790054 A CN 102790054A CN 2011101263941 A CN2011101263941 A CN 2011101263941A CN 201110126394 A CN201110126394 A CN 201110126394A CN 102790054 A CN102790054 A CN 102790054A
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狄增峰
卞剑涛
张苗
王曦
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Shanghai Institute of Microsystem and Information Technology of CAS
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Abstract

本发明提供了一种锗和Ⅲ-V混合共平面的半导体结构及其制备方法。锗和Ⅲ-V族半导体材料共平面异质集成的半导体结构包含至少一个形成在体硅衬底上的锗衬底，而另一衬底是被形成在锗半导体上的Ⅲ-V族半导体材料。的制备方法包括：制备体硅衬底上的锗半导体层；在锗半导体层上制备Ⅲ-V族半导体材料层；进行第一次光刻，将图形化窗口刻蚀至锗层以形成凹槽；在所述凹槽中制备侧墙；采用选择性外延制备锗薄膜；进行化学机械研磨以获得锗和Ⅲ-V族半导体材料共平面的异质集成半导体结构；去除侧墙及紧靠侧墙处的缺陷锗层部分；实现锗和Ⅲ-V族半导体材料之间的隔离；通过形成MOS结构来制备包含锗沟道PMOS和Ⅲ-V沟道NMOS的高性能CMOS器件。

Description

锗和III-V混合共平面的半导体结构及其制备方法
技术领域
本发明涉及半导体制造领域，更具体地说，本发明涉及一种共平面异质集成半导体结构，尤其涉及一种体硅衬底上锗和III-V族半导体材料共平面异质集成衬底材料，以及根据该半导体结构制备制造而成的高性能CMOS器件。
背景技术
随着半导体技术的发展，特别是当器件特征尺寸进入22nm及以下节点技术时，需要采用高迁移率的半导体材料，如Ge(锗)、III-V族半导体材料等。Ge具有高的电子迁移率和空穴迁移率，但受限于器件工艺因素(Ge的n型掺杂和n型欧姆接触等)，Ge的NMOS(N型金属氧化物半导体)性能一直不理想。然而诸如GaAS之类的III-V族半导体材料具有高电子迁移率，可以制造高性能的NMOS器件。
根据国家半导体路线(ITRS)，需要研制在绝缘衬底或硅基体上同时具有III-V族材料和Ge材料的异质集成高迁移率的半导体衬底材料，以保证集成电路技术继续沿着或超过摩尔定律持续发展。同时，研制在绝缘衬底或硅基体上同时具有III-V族材料和Ge材料的异质集成高迁移率的半导体衬底材料，也可以为实现单片集成的光电集成芯片、MEMS等多种功能芯片的集成化提供高性能的衬底材料。
但是，目前还没有可行的锗和III-V族半导体材料混合共平面的硅基体衬底结构上实现高性能CMOS器件的CMOS器件制造方法。其中，所谓III-V族(化合物)半导体材料指的是元素周期表中III族元素(例如B，Al，Ga，In)和V族元素(例如N，P，As，Sb)所形成的化合物。
因此，希望提出一种体硅衬底上锗和III-V族半导体材料混合共平面的异质集成衬底及其结构的制备方法，并在其上实现高性能CMOS器件。
发明内容
因此，本发明的一个目的就是提供一种体硅衬底上锗和III-V族半导体材料混合共平面的异质集成衬底及其结构的制备方法、以及根据该衬底及其结构制成的高性能CMOS器件。
根据本发明第一方面，提供了一种体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构，尤其是一种体硅衬底上锗和III-V族半导体材料混合共平面的异质集成衬底材料及其制备方法。
在根据本发明的体硅衬底上锗和III-V族半导体材料共平面异质集成的半导体衬底材料中，设有硅支撑衬底，锗半导体层，III-V族半导体材料层，以及锗和III-V族半导体材料之间的隔离介质材料；所述锗半导体层位于硅支撑衬底上，III-V族半导体材料层位于部分锗半导体层之上，顶部与其横向相邻的锗半导体层共平面，锗和III-V族半导体材料之间的隔离介质材料位于体硅衬底之上，其横向结构为两侧分别连接锗半导体层和III-V族半导体材料。
根据本发明的半导体结构包括根据本发明的上述衬底材料，其中，至少包括二种器件，其中，至少器件之一位于锗半导体层上，而另一器件位于III-V族半导体材料层上。
根据本发明的制备方法包括：制备体硅衬底上的锗半导体层；在所述锗半导体层上制备III-V族半导体材料层；进行第一次光刻，将图形化窗口刻蚀至锗层以便形成凹槽；在所述凹槽中制备侧墙；采用选择性外延制备锗薄膜；进行化学机械研磨以获得锗和III-V族半导体材料共平面的异质集成半导体结构；去除侧墙及紧靠侧墙处的缺陷锗层部分；实现锗和III-V族半导体材料之间的隔离；通过形成MOS结构来制备锗沟道PMOS和III-V沟道NMOS。从而，根据本发明的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法在锗和III-V族半导体材料混合共平面的硅基体衬底结构上实现了高性能的CMOS器件。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述III-V族半导体材料层包括GaAs、或AlAs、或AlGaAs、InGaAs等材料。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述侧墙是二氧化硅侧墙或氮化硅侧墙。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述制备体硅衬底上的锗半导体层的步骤包括：采用外延或键合技术在体硅衬底上生长锗半导体层。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述在锗半导体层上制备III-V族半导体材料层的步骤采用外延或键合技术。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述去除侧墙及紧靠侧墙处的缺陷锗层部分的步骤采用浅槽隔离技术。进一步优选地，在所述浅槽隔离技术中进行了第二次光刻。
优选地，在上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法中，所述实现锗和III-V族半导体材料之间的隔离的步骤采用二氧化硅来实现锗和III-V族半导体材料之间的隔离。进一步优选地，所述二氧化硅沉积是通过高密度等离子体沉积技术实现。
根据本发明的第二方面，提供了一种根据本发明第一方面所述的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法制成的高性能CMOS器件。
由于采用了根据本发明第一方面所述的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法，因此，本领域技术人员可以理解的是，根据本发明第二方面的CMOS器件同样能够实现根据本发明的第一方面的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法所能实现的有益技术效果。
附图说明
结合附图，并通过参考下面的详细描述，将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征，其中：
图1是根据本发明实施例的CMOS器件制造方法的流程图。
图2是图1所示的第一步骤S0之后得到的半导体结构示意图。
图3是图1所示的第二步骤S1之后得到的半导体结构示意图。
图4是图1所示的第三步骤S2之后得到的半导体结构示意图。
图5是图1所示的第四步骤S3之后得到的半导体结构示意图。
图6是图1所示的第五步骤S4之后得到的半导体结构示意图。
图7是图1所示的第六步骤S5之后得到的半导体结构示意图。
图8是图1所示的第七步骤S6之后得到的半导体结构示意图。
图9是图1所示的第八步骤S7之后得到的半导体结构示意图。
图10是图1所示的第九步骤S8之后得到的半导体结构示意图。
需要说明的是，附图用于说明本发明，而非限制本发明。注意，表示结构的附图可能并非按比例绘制。并且，附图中，相同或者类似的元件标有相同或者类似的标号。
具体实施方式
为了使本发明的内容更加清楚和易懂，下面结合具体实施例和附图对本发明的内容进行详细描述。
图1是根据本发明实施例的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法的流程图。
如图1所示，根据本发明实施例的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法包括如下步骤：
第一步骤S0，用于制备体硅衬底sub上的锗半导体层；更具体地说，该制备体硅衬底sub上的锗半导体层的步骤例如可以包括：采用外延或键合技术在体硅衬底sub上形成锗半导体层G。图2是图1所示的第一步骤S0之后得到的半导体结构示意图。
第二步骤S1，用于在锗半导体层上制备III-V族半导体材料层X；图3是图1所示的第二步骤S1之后得到的半导体结构示意图。优选地，在锗半导体层上制备III-V族半导体材料层X的步骤采用的是外延技术或键合技术。
需要说明的是，此处所谓III-V族半导体材料指的是元素周期表中III族元素(例如B，Al，Ga，In)和V族元素(例如N，P，As，Sb)所形成的化合物半导体材料。
并且，优选地，在一个具体示例中，该III-V族半导体材料层X中的III-V族半导体材料包括但不限于GaAs、或AlAs、或AlGaAs、InGaAs。并且，在上述III-V族半导体材料采用GaAs、或AlAs、或AlGaAs、InGaAs的情况下，最终所得到的CMOS器件性能最佳。
第三步骤S2，用于进行第一次光刻，将图形化窗口刻蚀至锗层以便形成凹槽；即，第一次光刻以锗层G作为阻止层，其不对锗层G进行光刻。图4是图1所示的第三步骤S2之后得到的半导体结构示意图。
第四步骤S3，用于在所述凹槽中制备侧墙S。图5是图1所示的第四步骤S3之后得到的半导体结构示意图。优选地，在一个具体示例中，所述侧墙S是二氧化硅侧墙或氮化硅侧墙。
第五步骤S4，用于采用选择性外延制备锗薄膜G。图6是图1所示的第五步骤S4之后得到的半导体结构示意图。
第六步骤S5，用于进行化学机械研磨(CMP)以获得锗和III-V族半导体材料共平面的异质集成半导体结构。图7是图1所示的第六步骤S5之后得到的半导体结构示意图。
第七步骤S6，用于去除侧墙及紧靠侧墙处的缺陷锗层部分。图8是图1所示的第七步骤S6之后得到的半导体结构示意图。优选地，在一个具体示例中，去除侧墙及紧靠侧墙处的缺陷锗层部分的步骤采用浅槽隔离技术。进一步优选地，在所述浅槽隔离技术中进行了第二次光刻。
需要说明的是，该第七步骤S6实际上在体硅衬底sub上形成了小沟槽，也就是以体硅衬底sub为底部的开口结构。
第八步骤S7，用于实现锗和III-V族半导体材料之间的隔离Y。图9是图1所示的第八步骤S7之后得到的半导体结构示意图。优选地，在一个具体示例中，实现锗和III-V族半导体材料之间的隔离Y的步骤采用二氧化硅作为隔离物Y来实现锗和III-V族半导体材料之间的隔离。进一步优选地，所述二氧化硅是通过高密度等离子沉积的。
第九步骤S8，用于通过形成MOS结构GT来制备锗沟道PMOS和III-V沟道NMOS。形成MOS结构GT的方法可以采用本领域公知的任何适当的方法，本发明并不对形成MOS结构GT的具体方法或步骤进行限定。并且，附图10中示出了三个MOS结构GT，但是三个MOS结构GT仅仅用于示例，其并不用于对本发明的MOS结构GT的数量和位置间隔进行具体限定。
图10是图1所示的第九步骤S8之后得到的半导体结构示意图。由此可以看出，通过步骤S0至步骤S8，根据本发明实施例的制备方法在锗和III-V族半导体材料混合共平面的硅基体衬底结构上实现了高性能的CMOS器件。
并且，上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法尤其适用于当器件特征尺寸进入22nm及以下节点技术时制造CMOS器件。在器件特征尺寸进入22nm及以下节点技术时，通过上述体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法制成的CMOS器件尤其优于现有技术的CMOS器件制造方法所制成的CMOS器件。
根据本发明的另一实施例，本发明还涉及根据图1所示的体硅衬底上锗和III-V族半导体材料混合共平面的异质集成半导体结构的制备方法的流程制成的CMOS器件，例如一个如图9所示的布置在锗和III-V族半导体材料混合共平面的硅基体衬底结构上的CMOS器件。
可以理解的是，虽然本发明已以较佳实施例披露如上，然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言，在不脱离本发明技术方案范围情况下，都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (12)

1.一种体硅衬底上锗和III-V族半导体材料共平面异质集成的半导体衬底材料，其特征在于设有硅支撑衬底，锗半导体层，III-V族半导体材料层，以及锗和III-V族半导体材料之间的隔离介质材料；
所述锗半导体层位于硅支撑衬底上，III-V族半导体材料层位于部分锗半导体层之上，顶部与其横向相邻的锗半导体层共平面，锗和III-V族半导体材料之间的隔离介质材料位于体硅衬底之上，其横向结构为两侧分别连接锗半导体层和III-V族半导体材料。
2.一种半导体结构，其包括根据权利要求1所述衬底材料，其特征在于至少包括二种器件，其中，至少器件之一位于锗半导体层上，而另一器件位于III-V族半导体材料层上。
3.根据权利要求2所述的半导体结构，其特征在于，锗半导体上的器件为NMOS，III-V族半导体材料层上器件为PMOS。
4.根据权利要求2或3所述的半导体结构，其特征在于，用于NMOS器件的锗半导体层为暴露于表面的锗半导体层部分。
5.一种根据权利要求1所述衬底材料或权利要求2所述半导体结构的制备方法，其特征在于其具体步骤为：
(1)制备体硅衬底上的锗半导体层；
(2)在锗半导体层结构上制备III-V族半导体材料层；
(3)进行第一次光刻，将图形化窗口刻蚀至锗层以便形成凹槽；
(4)在所述凹槽中制备侧墙；
(5)采用选择性外延制备锗薄膜；
(6)进行化学机械研磨以获得锗和III-V族半导体材料共平面的异质集成半导体结构；
(7)去除侧墙及紧靠侧墙处的缺陷锗层部分；
(8)实现锗和III-V族半导体材料之间的隔离；
(9)通过形成栅极结构来制备锗沟道PMOS和III-V沟道NMOS。
6.根据权利要求1所述衬底材料或权利3所述的制备方法，其特征在于，所述III-V族半导体材料包括GaAs、或AlAs、或AlGaAs、InGaAs等。
7.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述III-V族半导体材料形成于锗半导体之上。
8.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述侧墙是二氧化硅侧墙或氮化硅侧墙。
9.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述制备体硅衬底上的锗半导体层的步骤包括：采用外延或键合技术在体硅衬底上生长锗半导体层。
10.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述在所述锗半导体层上制备III-V族半导体材料层的步骤采用外延或键合技术。
11.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述去除侧墙及紧靠侧墙处的缺陷锗层部分的步骤采用浅槽隔离技术。
12.根据权利要求1所述衬底材料或权利要求5所述的制备方法，其特征在于，所述实现锗和III-V族半导体材料之间的隔离的步骤采用二氧化硅来实现锗和III-V族半导体材料之间的隔离。
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