JP2008503104A - 複数の半導体層を備えた半導体デバイス - Google Patents
複数の半導体層を備えた半導体デバイス Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 253
- 239000000463 material Substances 0.000 claims abstract description 42
- 239000013078 crystal Substances 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000203 mixture Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 239000010410 layer Substances 0.000 description 208
- 230000008569 process Effects 0.000 description 14
- 238000002955 isolation Methods 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- -1 for example Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
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- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
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- 150000004767 nitrides Chemical class 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
図中の構成要素は、簡便さ及び明確さのために示され、必ずしも実寸に従い図示されていないことは、当業者にとって明らかである。例えば、図中の幾つかの構成要素の寸法は、本発明の実施例を理解し易くするため、他の構成要素よりも誇張されている。
前述の明細書では、本発明について特定の実施形態を参照して説明してきた。しかし、当業者にとって、以下の特許請求の範囲に示す本発明の範囲から外れることなく、様々な改変及び変更を行えることは明らかである。従って、明細書及び図面は、制限的な意味ではなく、例示的な意味として考慮すべきであり、これらの改変は、本発明の範囲に含められている。
Claims (10)
- 一方が他方の上方に設けられる第一半導体層及び第二半導体層であって、第一半導体層は結晶面、材料組成及び歪みを有し、第二半導体層は結晶面、材料組成及び歪みを有する第一半導体層及び第二半導体層と、
前記第一半導体層の結晶構造に対して配向性を有し、前記第一半導体層内及びその上方に設けられる第一導電型の第一トランジスタと、
前記第一半導体層の結晶構造に対して配向性を有し、前記第二半導体層内及びその上方に設けられる第二導電型の第二トランジスタとを備え、
前記第一及び第二トランジスタは、材料組成、結晶面、配向性及び歪みの組み合わせにより規定される導電特性を有し、
前記第一トランジスタの導電特性は、前記第二トランジスタの導電特性とは異なり、
前記第一トランジスタの導電特性は、第二導電型の導電特性よりも前記第一導電型のトランジスタのキャリア移動度に適しており、
前記第二トランジスタの導電特性は、前記第一トランジスタの導電特性よりも前記第二導電型のトランジスタのキャリア移動度に適している半導体デバイス構造。 - 請求項1記載の半導体デバイス構造は、更に、第一絶縁体層を備え、その絶縁体層上には、前記第一及び第二半導体層が設けられている半導体デバイス構造。
- 請求項2記載の半導体デバイス構造は、更に、前記第一半導体層と前記第二半導体層との間に第二絶縁層を備えている半導体デバイス構造。
- 請求項1記載の半導体デバイス構造において、
前記第一導電型はNチャネルであり、
前記第二導電型はPチャネルであり、
前記第一半導体層の材料組成はシリコンを含み、
前記第二半導体層の材料組成はシリコン又はシリコンゲルマニウムを含む半導体デバイス構造。 - 請求項1記載の半導体デバイス構造は、更に、
第一絶縁層であって、その絶縁層上に前記第一及び第二半導体層が設けられ、
前記第一半導体層と前記第二半導体層との間に設けられる第二絶縁層を備え、
前記第一導電型はN型であり、
前記第二導電型はP型であり、
前記第一トランジスタの歪みは引っ張り性を有し、
前記第二トランジスタの歪みは圧縮性を有し、
前記第二半導体層の結晶面は(100)であり、
前記第二トランジスタの配向性は<100>であり、
前記第一半導体層の材料組成はシリコンを含み、
前記第二半導体層の材料組成はシリコン又はシリコンゲルマニウムを含む半導体デバイス構造。 - 一方が他方の上方に設けられる第一半導体層及び第二半導体層と、
導電特性を有し、第一半導体層内及びその上方に設けられる第一導電型の第一トランジスタと、
第二導電特性を有し、第二半導体層内及びその上方に設けられる第二導電型の第二トランジスタとを備え、
前記第一トランジスタの導電特性は、前記第二導電型のトランジスタよりも前記第一導電型のトランジスタのキャリア移動度に適している半導体デバイス構造。 - 請求項6記載の半導体デバイス構造において、
前記第一トランジスタはN型であり、
前記第一トランジスタの導電特性は、歪みが引っ張り性であり、平面が(100)であり、前記第一半導体層の材料組成がシリコンであることを特徴とする半導体デバイス構造。 - 第一半導体層を提供するステップと、
前記第一半導体層の上方に第二半導体層を形成するステップと、
導電特性を有する第一半導体層内及びその上方に第一導電型の第一トランジスタを形成するステップと、
第二導電特性を有する第二半導体層内及びその上方に第二導電型の第二トランジスタを形成するステップとを備え、
前記第一トランジスタの導電特性は、前記第二導電型のトランジスタよりも、前記第一導電型のトランジスタのキャリア移動度に適している方法。 - 請求項8記載の方法は、更に、
前記第一半導体層の一部が露出されるように前記第二半導体層の一部を除去するステップであって、前記第一トランジスタが前記第一半導体層の露出部分に形成されるステップと、
第一絶縁層を提供するステップであって、その絶縁層の上方に前記第一及び第二半導体層が設けられるステップと、
前記第一及び第二トランジスタを互いに接続する相互接続層を前記第一及び第二トランジスタの上方に形成するステップと、
前記第二トランジスタの少なくとも一つにバイアスを提供するため、前記相互接続層と前記第一半導体層との間にビアを形成するステップと、
前記第一及び第二トランジスタを形成した後、及び前記相互接続層を形成する前に、第三絶縁層を形成するステップとを備える方法。 - 請求項9記載の方法において、
前記第一導電型はN型であり、
前記第二導電型はP型であり、
前記第一トランジスタの導電特性は、前記第一半導体層の結晶面が(100)であり、歪みが引っ張り性であり、前記第一半導体層の材料組成がシリコンであることに特徴を有し、
前記第二トランジスタの導電特性は、歪みが圧縮性であり、前記第二半導体層の結晶面が(100)であり、第二トランジスタの配向性が<100>であることに特徴を有し、
前記第二半導体層の材料組成はシリコン又はシリコンゲルマニウムである方法。
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US10/865,351 US20050275018A1 (en) | 2004-06-10 | 2004-06-10 | Semiconductor device with multiple semiconductor layers |
PCT/US2005/016253 WO2006001915A2 (en) | 2004-06-10 | 2005-05-11 | Semiconductor device with multiple semiconductor layers |
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JP2008503104A true JP2008503104A (ja) | 2008-01-31 |
JP2008503104A5 JP2008503104A5 (ja) | 2008-06-19 |
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US (2) | US20050275018A1 (ja) |
JP (1) | JP2008503104A (ja) |
KR (1) | KR20070024581A (ja) |
CN (1) | CN1973374A (ja) |
TW (1) | TW200620662A (ja) |
WO (1) | WO2006001915A2 (ja) |
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US6995456B2 (en) * | 2004-03-12 | 2006-02-07 | International Business Machines Corporation | High-performance CMOS SOI devices on hybrid crystal-oriented substrates |
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2004
- 2004-06-10 US US10/865,351 patent/US20050275018A1/en not_active Abandoned
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2005
- 2005-05-11 CN CNA2005800188113A patent/CN1973374A/zh active Pending
- 2005-05-11 KR KR1020067025968A patent/KR20070024581A/ko not_active Application Discontinuation
- 2005-05-11 JP JP2007527290A patent/JP2008503104A/ja active Pending
- 2005-05-11 WO PCT/US2005/016253 patent/WO2006001915A2/en active Application Filing
- 2005-06-07 TW TW094118826A patent/TW200620662A/zh unknown
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2006
- 2006-05-09 US US11/382,432 patent/US20060194384A1/en not_active Abandoned
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JPH03285351A (ja) * | 1990-04-02 | 1991-12-16 | Oki Electric Ind Co Ltd | Cmis型半導体装置およびその製造方法 |
JPH04372166A (ja) * | 1991-06-21 | 1992-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH09246507A (ja) * | 1996-03-05 | 1997-09-19 | Citizen Watch Co Ltd | 半導体装置およびその製造方法 |
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JP2009033145A (ja) * | 2007-06-29 | 2009-02-12 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
JP2010161382A (ja) * | 2007-06-29 | 2010-07-22 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
US8354674B2 (en) | 2007-06-29 | 2013-01-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device wherein a property of a first semiconductor layer is different from a property of a second semiconductor layer |
JP2013016789A (ja) * | 2011-06-10 | 2013-01-24 | Sumitomo Chemical Co Ltd | 半導体デバイス、半導体基板、半導体基板の製造方法および半導体デバイスの製造方法 |
JP2013016791A (ja) * | 2011-06-10 | 2013-01-24 | Sumitomo Chemical Co Ltd | 半導体デバイス、半導体基板、半導体基板の製造方法および半導体デバイスの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
WO2006001915A3 (en) | 2006-04-06 |
US20060194384A1 (en) | 2006-08-31 |
KR20070024581A (ko) | 2007-03-02 |
TW200620662A (en) | 2006-06-16 |
WO2006001915A2 (en) | 2006-01-05 |
CN1973374A (zh) | 2007-05-30 |
US20050275018A1 (en) | 2005-12-15 |
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