FR2915318B1 - Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes - Google Patents

Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes

Info

Publication number
FR2915318B1
FR2915318B1 FR0702873A FR0702873A FR2915318B1 FR 2915318 B1 FR2915318 B1 FR 2915318B1 FR 0702873 A FR0702873 A FR 0702873A FR 0702873 A FR0702873 A FR 0702873A FR 2915318 B1 FR2915318 B1 FR 2915318B1
Authority
FR
France
Prior art keywords
portions
making
electronic circuit
active layers
circuit integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0702873A
Other languages
English (en)
Other versions
FR2915318A1 (fr
Inventor
Frederic Boeuf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR0702873A priority Critical patent/FR2915318B1/fr
Priority to US12/104,882 priority patent/US7579254B2/en
Publication of FR2915318A1 publication Critical patent/FR2915318A1/fr
Application granted granted Critical
Publication of FR2915318B1 publication Critical patent/FR2915318B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
FR0702873A 2007-04-20 2007-04-20 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes Expired - Fee Related FR2915318B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0702873A FR2915318B1 (fr) 2007-04-20 2007-04-20 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
US12/104,882 US7579254B2 (en) 2007-04-20 2008-04-17 Process for realizing an integrated electronic circuit with two active layer portions having different crystal orientations

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0702873A FR2915318B1 (fr) 2007-04-20 2007-04-20 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes

Publications (2)

Publication Number Publication Date
FR2915318A1 FR2915318A1 (fr) 2008-10-24
FR2915318B1 true FR2915318B1 (fr) 2009-07-17

Family

ID=38331129

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0702873A Expired - Fee Related FR2915318B1 (fr) 2007-04-20 2007-04-20 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes

Country Status (2)

Country Link
US (1) US7579254B2 (fr)
FR (1) FR2915318B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7755113B2 (en) * 2007-03-16 2010-07-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device
EP1993126B1 (fr) * 2007-05-18 2011-09-21 Semiconductor Energy Laboratory Co., Ltd. Procédés de fabrication d'un substrat semiconducteur
FR2935539B1 (fr) * 2008-08-26 2010-12-10 Commissariat Energie Atomique Circuit cmos tridimensionnel sur deux substrats desalignes et procede de realisation
FR3003685B1 (fr) 2013-03-21 2015-04-17 St Microelectronics Crolles 2 Procede de modification localisee des contraintes dans un substrat du type soi, en particulier fd soi, et dispositif correspondant
CN103456756A (zh) * 2013-09-26 2013-12-18 哈尔滨工程大学 一种有源像素结构及其制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6830962B1 (en) * 2003-08-05 2004-12-14 International Business Machines Corporation Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
US7034362B2 (en) * 2003-10-17 2006-04-25 International Business Machines Corporation Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US6949420B1 (en) * 2004-03-12 2005-09-27 Sony Corporation Silicon-on-insulator (SOI) substrate having dual surface crystallographic orientations and method of forming same
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US20050275018A1 (en) * 2004-06-10 2005-12-15 Suresh Venkatesan Semiconductor device with multiple semiconductor layers
JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法
US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
US7226833B2 (en) * 2004-10-29 2007-06-05 Freescale Semiconductor, Inc. Semiconductor device structure and method therefor
US7235433B2 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device
US7405436B2 (en) * 2005-01-05 2008-07-29 International Business Machines Corporation Stressed field effect transistors on hybrid orientation substrate
US7432149B2 (en) * 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
KR101461206B1 (ko) * 2007-05-17 2014-11-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그의 제조방법
US7547641B2 (en) * 2007-06-05 2009-06-16 International Business Machines Corporation Super hybrid SOI CMOS devices

Also Published As

Publication number Publication date
FR2915318A1 (fr) 2008-10-24
US20080258254A1 (en) 2008-10-23
US7579254B2 (en) 2009-08-25

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Effective date: 20131231