DE69114565D1 - Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung. - Google Patents

Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung.

Info

Publication number
DE69114565D1
DE69114565D1 DE69114565T DE69114565T DE69114565D1 DE 69114565 D1 DE69114565 D1 DE 69114565D1 DE 69114565 T DE69114565 T DE 69114565T DE 69114565 T DE69114565 T DE 69114565T DE 69114565 D1 DE69114565 D1 DE 69114565D1
Authority
DE
Germany
Prior art keywords
manufacturing
memory device
semiconductor memory
volatile semiconductor
volatile
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69114565T
Other languages
English (en)
Other versions
DE69114565T2 (de
Inventor
Hitoshi Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69114565D1 publication Critical patent/DE69114565D1/de
Application granted granted Critical
Publication of DE69114565T2 publication Critical patent/DE69114565T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
DE69114565T 1990-05-11 1991-05-10 Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung. Expired - Lifetime DE69114565T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2119950A JPH088319B2 (ja) 1990-05-11 1990-05-11 不揮発性半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
DE69114565D1 true DE69114565D1 (de) 1995-12-21
DE69114565T2 DE69114565T2 (de) 1996-05-02

Family

ID=14774203

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69114565T Expired - Lifetime DE69114565T2 (de) 1990-05-11 1991-05-10 Verfahren zur Herstellung einer nichtflüchtigen Halbleiterspeicheranordnung.

Country Status (4)

Country Link
EP (1) EP0456256B1 (de)
JP (1) JPH088319B2 (de)
KR (1) KR940007655B1 (de)
DE (1) DE69114565T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5222471A (en) * 1992-09-18 1993-06-29 Kohler Co. Emission control system for an internal combustion engine
DE19704534A1 (de) * 1997-02-06 1998-08-20 Siemens Ag Halbleiterkörper
KR100519163B1 (ko) * 1998-12-30 2005-12-06 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법_
KR100549591B1 (ko) * 2003-11-05 2006-02-08 매그나칩 반도체 유한회사 비휘발성 메모리 소자 및 그의 제조 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6195556A (ja) * 1984-10-17 1986-05-14 Hitachi Ltd 半導体装置
JP2652638B2 (ja) * 1987-08-10 1997-09-10 株式会社デンソー 不揮発性半導体記憶装置の製造方法
JPH01171229A (ja) * 1987-12-25 1989-07-06 Hitachi Ltd 不揮発性半導体記憶装置
JPH0215678A (ja) * 1988-07-01 1990-01-19 Seiko Instr Inc 半導体不揮発性メモリ
JP2906415B2 (ja) * 1988-09-14 1999-06-21 ソニー株式会社 不揮発性メモリ装置及びその製造方法
JPH02122570A (ja) * 1988-10-31 1990-05-10 Sony Corp 不揮発性メモリ及びその製造方法

Also Published As

Publication number Publication date
JPH0417373A (ja) 1992-01-22
EP0456256A3 (en) 1992-04-01
EP0456256A2 (de) 1991-11-13
EP0456256B1 (de) 1995-11-15
KR940007655B1 (ko) 1994-08-22
JPH088319B2 (ja) 1996-01-29
DE69114565T2 (de) 1996-05-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)