DE69723105D1 - Speicher und verfahren zum lesen von speicherelementenuntergruppen - Google Patents

Speicher und verfahren zum lesen von speicherelementenuntergruppen

Info

Publication number
DE69723105D1
DE69723105D1 DE69723105T DE69723105T DE69723105D1 DE 69723105 D1 DE69723105 D1 DE 69723105D1 DE 69723105 T DE69723105 T DE 69723105T DE 69723105 T DE69723105 T DE 69723105T DE 69723105 D1 DE69723105 D1 DE 69723105D1
Authority
DE
Germany
Prior art keywords
memory
groups
reading
sub
memory sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE69723105T
Other languages
English (en)
Other versions
DE69723105T2 (de
Inventor
M Barth
C Stark
Lawrence Lai
S Richardson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25091385&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69723105(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of DE69723105D1 publication Critical patent/DE69723105D1/de
Application granted granted Critical
Publication of DE69723105T2 publication Critical patent/DE69723105T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69723105T 1996-12-20 1997-12-15 Speicher und verfahren zum lesen von speicherelementenuntergruppen Revoked DE69723105T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/771,303 US5748554A (en) 1996-12-20 1996-12-20 Memory and method for sensing sub-groups of memory elements
US771303 1996-12-20
PCT/US1997/023076 WO1998028747A1 (en) 1996-12-20 1997-12-15 Memory and method for sensing sub-groups of memory elements

Publications (2)

Publication Number Publication Date
DE69723105D1 true DE69723105D1 (de) 2003-07-31
DE69723105T2 DE69723105T2 (de) 2004-05-06

Family

ID=25091385

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69723105T Revoked DE69723105T2 (de) 1996-12-20 1997-12-15 Speicher und verfahren zum lesen von speicherelementenuntergruppen

Country Status (6)

Country Link
US (2) US5748554A (de)
EP (1) EP0946943B1 (de)
AU (1) AU5604698A (de)
DE (1) DE69723105T2 (de)
TW (1) TW412749B (de)
WO (1) WO1998028747A1 (de)

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US7254075B2 (en) 2004-09-30 2007-08-07 Rambus Inc. Integrated circuit memory system having dynamic memory bank count and page size
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US7389194B2 (en) * 2005-07-06 2008-06-17 Rambus Inc. Driver calibration methods and circuits
US7660183B2 (en) 2005-08-01 2010-02-09 Rambus Inc. Low power memory device
KR100673694B1 (ko) * 2005-10-10 2007-01-24 주식회사 하이닉스반도체 저전력 소비형 칼럼 디코더를 가지는 반도체 메모리 장치및 그 리드 동작 방법
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
US7471546B2 (en) * 2007-01-05 2008-12-30 International Business Machines Corporation Hierarchical six-transistor SRAM
US7460423B2 (en) * 2007-01-05 2008-12-02 International Business Machines Corporation Hierarchical 2T-DRAM with self-timed sensing
US7499312B2 (en) * 2007-01-05 2009-03-03 International Business Machines Corporation Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line
US7460387B2 (en) * 2007-01-05 2008-12-02 International Business Machines Corporation eDRAM hierarchical differential sense amp
US7835202B2 (en) * 2007-06-26 2010-11-16 Broadcom Corporation Power-saving semiconductor memory
WO2013015893A1 (en) 2011-07-27 2013-01-31 Rambus Inc. Memory with deferred fractional row activation
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
EP2751808A4 (de) 2011-08-30 2015-04-08 Rambus Inc Verteilte unterseitenauswahl
US9116781B2 (en) * 2011-10-17 2015-08-25 Rambus Inc. Memory controller and memory device command protocol
US8929164B2 (en) 2012-03-05 2015-01-06 Micron Technology, Inc. Apparatuses and methods for adjustment of data strobe signals

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Also Published As

Publication number Publication date
USRE37409E1 (en) 2001-10-16
EP0946943A1 (de) 1999-10-06
EP0946943B1 (de) 2003-06-25
TW412749B (en) 2000-11-21
US5748554A (en) 1998-05-05
DE69723105T2 (de) 2004-05-06
AU5604698A (en) 1998-07-17
WO1998028747A1 (en) 1998-07-02

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8331 Complete revocation