DE69734278D1 - Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt - Google Patents

Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt

Info

Publication number
DE69734278D1
DE69734278D1 DE69734278T DE69734278T DE69734278D1 DE 69734278 D1 DE69734278 D1 DE 69734278D1 DE 69734278 T DE69734278 T DE 69734278T DE 69734278 T DE69734278 T DE 69734278T DE 69734278 D1 DE69734278 D1 DE 69734278D1
Authority
DE
Germany
Prior art keywords
manufacturing
nonvolatile semiconductor
polysilicon gate
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69734278T
Other languages
English (en)
Inventor
Roberta Bottini
Libera Giovanna Dalla
Bruno Vajana
Federico Pio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69734278D1 publication Critical patent/DE69734278D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69734278T 1997-07-03 1997-07-03 Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt Expired - Lifetime DE69734278D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP97830334A EP0889520B1 (de) 1997-07-03 1997-07-03 Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt

Publications (1)

Publication Number Publication Date
DE69734278D1 true DE69734278D1 (de) 2006-02-09

Family

ID=8230694

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69734278T Expired - Lifetime DE69734278D1 (de) 1997-07-03 1997-07-03 Herstellungsverfahren eines nichtflüchtigen Halbleiterspeicherbauelementes mit abgeschirmtem Einpolysiliziumgate-Speicherabschnitt

Country Status (4)

Country Link
US (1) US6548354B2 (de)
EP (1) EP0889520B1 (de)
JP (1) JPH1174490A (de)
DE (1) DE69734278D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565919Y2 (ja) * 1991-01-23 1998-03-25 旭光学工業株式会社 レンズ駆動バネ装置
ITMI20022467A1 (it) * 2002-11-20 2004-05-21 St Microelectronics Srl Processo per realizzare un transistore di selezione di byte per
DE10257870B4 (de) * 2002-12-11 2007-10-04 Infineon Technologies Ag Halbleiterstruktur mit einer integrierten Abschirmung
DE102004061921B4 (de) * 2004-12-22 2011-03-10 Texas Instruments Deutschland Gmbh Halbleiterspeichervorrichtung umfassend mehrere Single-Poly-EPROM-Vorrichtungen
US7671401B2 (en) * 2005-10-28 2010-03-02 Mosys, Inc. Non-volatile memory in CMOS logic process
US7759727B2 (en) * 2006-08-21 2010-07-20 Intersil Americas Inc. Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology
US20110216596A1 (en) * 2010-03-04 2011-09-08 Mosys, Inc. Reliability Protection for Non-Volatile Memories
US10038001B1 (en) * 2017-06-16 2018-07-31 Allegro Microsystems, Llc Hybrid electrically erasable programmable read-only memory (EEPROM) systems and methods for forming

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4417325A (en) * 1981-07-13 1983-11-22 Eliyahou Harari Highly scaleable dynamic ram cell with self-signal amplification
DE68920236T2 (de) * 1988-09-01 1995-05-04 Atmel Corp Versiegelte Ladungsspeicheranordnung.
US4970565A (en) 1988-09-01 1990-11-13 Atmel Corporation Sealed charge storage structure
EP0409107B1 (de) 1989-07-18 1996-09-25 Sony Corporation Nichtflüchtige Halbleiterspeicheranordnung und Verfahren zur Herstellung
JPH07130893A (ja) * 1993-11-05 1995-05-19 Sony Corp 半導体装置及びその製造方法
TW360980B (en) * 1994-05-04 1999-06-11 Nippon Precision Circuits Single transistor EEPROM memory device
US5650346A (en) * 1994-08-29 1997-07-22 United Microelectronics Corporation Method of forming MOSFET devices with buried bitline capacitors
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JPH08102531A (ja) * 1994-09-30 1996-04-16 Toshiba Corp 半導体記憶装置及びその製造方法
KR0161402B1 (ko) * 1995-03-22 1998-12-01 김광호 불휘발성 메모리 제조방법
KR100199382B1 (ko) * 1996-06-27 1999-06-15 김영환 플래쉬 메모리 소자의 제조방법
JP3665426B2 (ja) * 1996-07-17 2005-06-29 東芝マイクロエレクトロニクス株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
US20010025980A1 (en) 2001-10-04
EP0889520B1 (de) 2005-09-28
EP0889520A1 (de) 1999-01-07
JPH1174490A (ja) 1999-03-16
US6548354B2 (en) 2003-04-15

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