DE69625755D1 - Nichtflüchtige zwei-Transistor Speicherzelle mit einem einzigen Polysiliziumgate - Google Patents

Nichtflüchtige zwei-Transistor Speicherzelle mit einem einzigen Polysiliziumgate

Info

Publication number
DE69625755D1
DE69625755D1 DE69625755T DE69625755T DE69625755D1 DE 69625755 D1 DE69625755 D1 DE 69625755D1 DE 69625755 T DE69625755 T DE 69625755T DE 69625755 T DE69625755 T DE 69625755T DE 69625755 D1 DE69625755 D1 DE 69625755D1
Authority
DE
Germany
Prior art keywords
volatile
memory cell
polysilicon gate
transistor memory
single polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69625755T
Other languages
English (en)
Other versions
DE69625755T2 (de
Inventor
Patrice M Parris
Yee-Chaung See
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE69625755D1 publication Critical patent/DE69625755D1/de
Application granted granted Critical
Publication of DE69625755T2 publication Critical patent/DE69625755T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
DE69625755T 1995-07-28 1996-07-18 Nichtflüchtige zwei-Transistor Speicherzelle mit einem einzigen Polysiliziumgate Expired - Fee Related DE69625755T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/506,989 US5604700A (en) 1995-07-28 1995-07-28 Non-volatile memory cell having a single polysilicon gate

Publications (2)

Publication Number Publication Date
DE69625755D1 true DE69625755D1 (de) 2003-02-20
DE69625755T2 DE69625755T2 (de) 2003-09-25

Family

ID=24016833

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69625755T Expired - Fee Related DE69625755T2 (de) 1995-07-28 1996-07-18 Nichtflüchtige zwei-Transistor Speicherzelle mit einem einzigen Polysiliziumgate

Country Status (4)

Country Link
US (1) US5604700A (de)
EP (1) EP0756328B1 (de)
JP (1) JP3916695B2 (de)
DE (1) DE69625755T2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892709A (en) * 1997-05-09 1999-04-06 Motorola, Inc. Single level gate nonvolatile memory device and method for accessing the same
US6965123B1 (en) 1997-07-29 2005-11-15 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
US7196929B1 (en) * 1997-07-29 2007-03-27 Micron Technology Inc Method for operating a memory device having an amorphous silicon carbide gate insulator
US6794255B1 (en) * 1997-07-29 2004-09-21 Micron Technology, Inc. Carburized silicon gate insulators for integrated circuits
US6324097B1 (en) * 1999-08-26 2001-11-27 Mosel Vitelic Inc. Single poly non-volatile memory structure and its fabricating method
US6222764B1 (en) * 1999-12-13 2001-04-24 Agere Systems Guardian Corp. Erasable memory device and an associated method for erasing a memory cell therein
JP3808763B2 (ja) * 2001-12-14 2006-08-16 株式会社東芝 半導体メモリ装置およびその製造方法
DE10214898B4 (de) * 2002-04-04 2009-02-05 Infineon Technologies Ag Speicherschaltung
DE10217289B4 (de) * 2002-04-18 2009-04-09 Infineon Technologies Ag Speichervorrichtung und Verfahren zum Betreiben einer Speichervorrichtung
DE10248982B4 (de) * 2002-08-30 2006-10-26 Infineon Technologies Ag Vorrichtung und Verfahren zur Überwachung der Stromaufnahme einer Schaltungsanordnung
US7209392B2 (en) * 2004-07-20 2007-04-24 Ememory Technology Inc. Single poly non-volatile memory
US7098499B2 (en) * 2004-08-16 2006-08-29 Chih-Hsin Wang Electrically alterable non-volatile memory cell
US20060226489A1 (en) * 2005-03-30 2006-10-12 Impinj, Inc. System and methods for retention-enhanced programmable shared gate logic circuit
US7279997B2 (en) 2005-10-14 2007-10-09 Freescale Semiconductor, Inc. Voltage controlled oscillator with a multiple gate transistor and method therefor
US20070085576A1 (en) * 2005-10-14 2007-04-19 Hector Sanchez Output driver circuit with multiple gate devices
JP4849517B2 (ja) * 2005-11-28 2012-01-11 ルネサスエレクトロニクス株式会社 不揮発性メモリセル及びｅｅｐｒｏｍ
US7358823B2 (en) * 2006-02-14 2008-04-15 International Business Machines Corporation Programmable capacitors and methods of using the same
US7626864B2 (en) * 2006-04-26 2009-12-01 Chih-Hsin Wang Electrically alterable non-volatile memory cells and arrays
US7773424B2 (en) * 2008-05-23 2010-08-10 Freescale Semiconductor, Inc. Circuit for and an electronic device including a nonvolatile memory cell and a process of forming the electronic device
US8947938B2 (en) * 2012-09-21 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Two-transistor non-volatile memory cell and related program and read methods
US9640228B2 (en) * 2014-12-12 2017-05-02 Globalfoundries Inc. CMOS device with reading circuit
US9659655B1 (en) * 2016-09-08 2017-05-23 International Business Machines Corporation Memory arrays using common floating gate series devices
US11282844B2 (en) * 2018-06-27 2022-03-22 Ememory Technology Inc. Erasable programmable non-volatile memory including two floating gate transistors with the same floating gate

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
CH625075A5 (de) * 1978-02-22 1981-08-31 Centre Electron Horloger
US4649520A (en) * 1984-11-07 1987-03-10 Waferscale Integration Inc. Single layer polycrystalline floating gate
US4924278A (en) * 1987-06-19 1990-05-08 Advanced Micro Devices, Inc. EEPROM using a merged source and control gate
US5027171A (en) * 1989-08-28 1991-06-25 The United States Of America As Represented By The Secretary Of The Navy Dual polarity floating gate MOS analog memory device
EP0493640B1 (de) * 1990-12-31 1995-04-19 STMicroelectronics S.r.l. EEPROM-Zelle mit einschichtigem Metallgate und mit einem Lese-Interface des externen Schaltkreises, welches isoliert ist vom Schreib/Lösch-Interface des Programmierungsschaltkreises
US5301150A (en) * 1992-06-22 1994-04-05 Intel Corporation Flash erasable single poly EPROM device
US5309009A (en) * 1992-09-14 1994-05-03 Chao Robert L Integrated electrically adjustable analog transistor device
JP2596695B2 (ja) * 1993-05-07 1997-04-02 インターナショナル・ビジネス・マシーンズ・コーポレイション Ｅｅｐｒｏｍ
US5455788A (en) * 1993-08-24 1995-10-03 Honeywell Inc. SRAM to ROM programming connections to avoid parasitic devices and electrical overstress sensitivity

Also Published As

Publication number Publication date
US5604700A (en) 1997-02-18
EP0756328B1 (de) 2003-01-15
JP3916695B2 (ja) 2007-05-16
EP0756328A3 (de) 1997-07-16
JPH09185891A (ja) 1997-07-15
DE69625755T2 (de) 2003-09-25
EP0756328A2 (de) 1997-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee