US5687119A - Semiconductor memory device with floating gate electrode - Google Patents
Semiconductor memory device with floating gate electrode Download PDFInfo
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- US5687119A US5687119A US08/646,152 US64615296A US5687119A US 5687119 A US5687119 A US 5687119A US 64615296 A US64615296 A US 64615296A US 5687119 A US5687119 A US 5687119A
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- floating gate
- memory device
- semiconductor memory
- cell
- insulating film
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which, although it does not incorporate a capacitor, can be used as a dynamic random access memory (DRAM) cell.
- the present invention also relates to a method of manufacturing such a semiconductor device.
- a DRAM memory device is not limited in its cycling, but is inferior in the density aspect because the unit cell of a DRAM is composed of one storage capacitor and one transistor.
- an electrically erasable programmable read only memory (EEPROM) device is composed of one stacked transistor. Through a thin tunnel oxide film, a floating gate is charged with electrons or the charged electrons are discharged from the floating gate, to thereby perform "programming" or "erasure” of the cell. Accordingly, the density of the EEPROM is good, but the cycling is limited to about 10 7 possible programming/erasure occurrences.
- the DRAM and EEPROM will be described below with reference to the attached drawings.
- FIG. 1 is a circuit diagram of a general DRAM cell.
- FIG. 2 is a cross-sectional view showing the structure of the general DRAM cell.
- the conventional DRAM cell is constructed using one bit line (B/L), one word line (W/L), one access transistor (M1), one storage capacitor (Cs), and one sense amplifier (SA).
- a gate (G) of access transistor (M1) is connected to word line (W/L).
- a drain (D) of access transistor (M1) is connected to bit line (B/L).
- a source (S) of access transistor (M1) is connected to a first electrode of storage capacitor (Cs).
- a second electrode of storage capacitor (Cs) is connected to a polysilicon cell plate.
- Bit line (B/L) is connected to one input terminal of sense amplifier (SA).
- Another input terminal of sense amplifier (SA) is connected to a reference voltage (Vref).
- FIG. 2 The structure of the DRAM cell having the aforementioned circuit construction is shown in FIG. 2. That is, a P-type silicon substrate 1 is divided into a field region and an active region, and a field oxide film 2 is formed on the field region. A gate insulating film 3 and a gate electrode 4 are stacked sequentially on the active region of P-type silicon substrate 1. Source/drain regions (S,D), which are N-type impurity regions, are formed in the substrate 1 on both sides of gate electrode 4, thereby forming access transistor (M1).
- S,D Source/drain regions
- M1 access transistor
- first electrode 6 of the capacitor (Cs) is formed on source region (S) of access transistor (M1).
- a dielectric film 7 and a second electrode 8 are stacked on the surface of first electrode 6 of the capacitor (Cs).
- bit line (B/L) is connected to drain region (D) of access transistor (M1).
- Reference numerals 5 and 9 designate insulating films.
- 5V are applied to the bit line connected to drain (D) of access transistor (M1) of the above cell.
- a voltage pulse of 5-6V is applied to the word line connected to gate (G) of access transistor (M1) of the above cell. If so, the access transistor is in an "on” state, so that the potential of the access transistor source of the above cell is raised to 5V.
- the potential of the inversion layer formed in the surface of the P-type silicon region under second electrode 8 will be somewhat lower than 5V. This is because the voltage of 5V applied to second electrode 8 is decreased in some degree through the dielectric film of the storage capacitor located below second electrode 8.
- the electrons accumulated in the inversion layer formed in the P-type silicon substrate surface under second electrode 8 flow into the source region of access transistor (M1), whose electron energy state is low.
- M1 access transistor
- an empty potential well is formed in the surface of the P-type silicon region under second electrode 8.
- Such state shows a logic "1" in the binary system.
- bit line (B/L) connected to the drain of the access transistor of the above cell is grounded.
- a voltage pulse of 5-6 V is applied to word line (W/L) connected to the gate of the access transistor of the above cell.
- the electrons flow from source region (S) of access transistor (M1) having a high electron energy to the empty potential well formed in the surface of the P-type silicon substrate, thereby filling the empty potential well. Accordingly, the electrons are accumulated in the inversion layer formed in the surface of the P-type silicon substrate under the capacitor. Such state shows a logic "0" in the binary system.
- bit line (B/L) is precharged to 0.5Vcc ( ⁇ 2.5V), and then a voltage pulse of 5-6V is applied to the word line (W/L) of the above cell. If so, the electric charges charged in the storage capacitor (Cs) of the above cell flow to bit line (B/L), thereby changing the potential of bit line (B/L).
- SA sense amplifier
- a displacement potential ( ⁇ V) of bit line (B/L) is expressed by the following equation (1):
- Cs represents the static capacity of the storage capacitor (Cs)
- Cb represents the static capacity of the bit line.
- the (+) symbol corresponds to the case where a logic "1" is stored in the cell.
- the (-) symbol corresponds to the case where a logic "0" is stored in the cell.
- a design rule of about 2 mm has been used.
- a design rule of about 0.25 ⁇ m has been used. Accordingly, the cell area has been decreased by about 100 times.
- a trench is formed in the substrate to thereby form the storage capacitor, or a stacked capacitor structure is used to form the storage capacitor.
- the semiconductor manufacturing process becomes complicated. In connection with this, there is a problem in that the semiconductor manufacturing process cost increases substantially.
- FIG. 3 is a circuit diagram of a general flash EEPROM cell.
- FIG. 4 is a cross-sectional view showing the structure of the general flash EEPROM cell.
- the general EEPROM cell is comprised of a floating gate avalanche injection metal oxide semiconductor (FAMOS) having a stacked gate transistor structure.
- a control gate (C,G) of each cell is connected to a word line (W/L).
- a drain (D) of each cell is connected to a bit line (B/L).
- a source (S) of each cell is connected to a common source line (C,S).
- FMOS floating gate avalanche injection metal oxide semiconductor
- each bit line (B/L) is connected to an input terminal of a sense amplifier (SA).
- SA sense amplifier
- Vref reference voltage
- FIG. 4 The structure of the general EEPROM cell having the aforementioned circuit construction is shown in FIG. 4. That is, a floating gate (F,G) and a control gate (C,G) are stacked sequentially on a P-type silicon substrate 1. A source region (S) and a drain region (D) formed from N-type impurity regions are formed in P-type silicon substrate 1 on both sides of floating gate (F,G).
- An insulating film is formed between silicon substrate 1, floating gate (F,G), and control gate (C,G). Between floating gate (F,G) and control gate (C,G), the insulating film is formed to a thickness corresponding to the thickness of a gate insulating film of a general transistor. Between floating gate (F,G) and silicon substrate 1, a tunnel oxide film is formed to a thickness of about 100 ⁇ or less.
- Such general EEPROM is as follows. First of all, in order to write a logic "1" in a cell, 7-8V are applied to bit line (B/L) corresponding to the above cell. A voltage pulse of 12-13V is applied to word line (W/L). The source (S) and substrate 1 are grounded. If so, avalanche breakdown occurs in the P-N junction between drain (D) and substrate 1, thereby generating hot electrons.
- a number of the hot electrons generated as described above obtain an energy level higher than the energy potential height (about 3.2 eV) between the substrate and gate oxide film. Then, from the substrate, the electrons travel over the gate oxide film and enter floating gate (F,G), to be stored therein.
- F,G floating gate
- the threshold voltage of the cell begins to decrease.
- the cell threshold voltage must be 3V or less. Accordingly, such state shows a logic "0" in the binary system.
- the process of reading data stored in the memory cell is as follows. That is, 1-2V are applied to bit line (B/L) connected to drain (D) of the cell. The substrate and source (S) are grounded. Then, a voltage pulse of 3-5V is applied to word line (W/L) connected to control gate (C,G) of the cell.
- bit line (B/L) In the case where a logic "0" is stored in the cell, the cell enters an "ON" state, so that all electric charges on bit line (B/L) are discharged to source (S) through the cell. Thus, the potential of bit line (B/L) is in a ground state.
- Sense amplifier (SA) connected to bit line (B/L) recognizes such potential difference of bit line (B/L), thereby reading the stored data of the cell.
- the number of times of programming/erasure of data is unlimited.
- the possible times of programming/erasure of data is generally limited to 10 7 or less. Therefore, there is a problem in that the flash EEPROM cannot be used in most applications as a substitute for the DRAM.
- the speed of programming and erasure is reduced. If the time of programming and erasure is not controlled, the programming threshold voltage is decreased and the erasure threshold voltage is increased, together with the increase of programming/erasure times of data. Accordingly, a so-called “window-closing" phenomenon occurs, such that the device cannot perform the programming/erasure of data after exceeding a predetermined number of times.
- each cell is composed of one transistor by using the merits of DRAM and EEPROM, so that integration is improved and the number of times that programming/erasure of data can be carried out is not limited. Additional objects and advantages of the invention will be set forth in the description which follows or will be obvious from the description or may be learned by practice of the invention.
- a semiconductor memory device comprising a memory cell having a floating gate electrode for storing an electric charge, and a switching element for charging the floating gate electrode with the electric charge and for performing a switching function so as to discharge the electric charge of the floating gate electrode.
- a method of manufacturing a semiconductor memory device comprising the steps of forming a field insulating film having an island shape on a semiconductor substrate of a first conductivity type; forming an impurity region of a second conductivity type on the semiconductor substrate of the first conductivity type in a column direction between a plurality of the field insulating films; forming a first gate insulating film on an entire surface of the substrate and the filed insulating film; forming a floating gate electrode so that impurity regions of the first conductivity type and second conductivity type are repeated on the first gate insulating film and the field insulating film between a plurality of the impurity regions of the second conductivity type; forming a second gate insulating film on an entire surface of the first gate insulating film and the floating gate electrode; forming a control electrode on the second gate insulating film between the field insulating films in a direction perpendicular with respect to the floating gate electrode; and forming a gate electrode of
- FIG. 1 is a circuit diagram of a general DRAM cell
- FIG. 2 is a cross-sectional view showing the structure of the general DRAM cell
- FIG. 3 is a circuit diagram of a general flash EEPROM cell
- FIG. 4 is a cross-sectional view showing the structure of the general flash EEPROM cell
- FIG. 5 is a circuit diagram of a semiconductor memory device according to the present invention.
- FIG. 6 is a layout diagram of a semiconductor memory device according to an embodiment of the present invention.
- FIG. 7 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line I-I' in FIG. 6;
- FIG. 8 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line II-I' in FIG. 6;
- FIG. 9 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line III-III' in FIG. 6;
- FIG. 10 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line IV-IV' in FIG. 6;
- FIGS. 11a through 11j are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line I-I' in FIG. 6;
- FIGS. 12a through 12j are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line II-II' in FIG. 6;
- FIGS. 13a through 13j are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line III-III'in FIG. 6;
- FIGS. 14a through 14j are cross-sectional views illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line IV-IV' in FIG. 6.
- a plurality of memory cells having a floating gate (F,G) and a control gate (C,G) are arranged.
- stacked transistors (M1,1-Mn,2) for use as data memory there are formed passing transistors Q1,1-Qn,2 which switch so as to charge, with electric charges, each floating gate (F,G) of stacked transistors (M1,1-Mn,2) for use as data memory, and so as to discharge the charged electric charges and perform programming or erasure of the cell.
- control gates (C,G) of each stacked transistor for use as data memory of the same column are connected to a word line (W/L1-W/Ln).
- Drains (D) of each stacked transistor for use as data memory of the same row and sources of each stacked transistor for use as data memory of the neighboring row are connected in common to respective bit lines (B/L1-B/L3).
- an input terminal of a sensing amplifier is connected to each bit line (B/L1-B/L3) and a reference voltage is applied to its other input terminal.
- the end terminal of each bit line (B/L1-B/L3) is arranged to be floating.
- Each passing transistor (QI,1-Qn2) of the same column is connected to a gate line (G/L1-G/Ln). Each passing transistor of the same row is connected in series. A drain terminal of the tip is arranged to be floating.
- FIG. 6, FIG. 7, FIG. 8, FIG. 9 and FIG. 1 The structure of a semiconductor memory device according to an embodiment of the present invention having such circuit construction is shown in FIG. 6, FIG. 7, FIG. 8, FIG. 9 and FIG. 1. That is, as shown in FIG. 6, a plurality of high concentration N-type impurity regions 12, which are to be used as bit lines, are spaced apart by a constant distance and formed in one direction in a P-type silicon substrate. On the P-type silicon substrate between the respective high concentration N-type impurity regions 12, a plurality of floating gate semiconductor layers (polycrystalline silicon) 13 for storing electric charges are formed so as to be isolated from the P-type silicon substrate.
- floating gate semiconductor layers polycrystalline silicon
- control electrodes 14 used as word lines (W/L) are formed spaced apart by a constant distance in the perpendicular direction with respect to floating gate semiconductor layers 13.
- passing gate electrodes 15 for controlling each passing transistor (M1,1-Mn2).
- Each floating gate semiconductor layer 13 under control electrode 14 is formed as a high concentration N-type impurity layer (N + ).
- Each floating gate semiconductor layer 13 under passing gate electrode 15 is formed as a P-type impurity layer (P). Further, in the silicon substrate under the portion where passing gate electrode 15 and floating gate semiconductor layer 13 cross, a field oxide film 16 having an island shape is formed.
- FIG. 7 the cross-section of the control electrode in FIG. 6 is shown in FIG. 7.
- High concentration N-type impurity regions 12 which will be used as bit lines are formed in a P-type silicon substrate 11, being spaced apart by a constant distance.
- a first gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11.
- a floating gate semiconductor layer 13 is formed on first gate insulating film 17 between the respective high concentration N-type impurity regions 12.
- a second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13.
- a control electrode 14 is formed on second gate insulating film 18.
- FIG. 8 The cross-section of the passing gate electrode direction in FIG. 6 is shown in FIG. 8.
- High concentration N-type impurity regions 12, which will be used as bit lines, are formed in P-type silicon substrate 11, being spaced apart by a constant distance.
- a field oxide film 16 having an island shape is formed on P-type silicon substrate 11 at the portion where each floating gate semiconductor layer 13 and each passing get electrode cross.
- First gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11.
- Floating gate semiconductor layer 13 is formed on first gate insulating film 17 between the respective high concentration N-type impurity regions 12.
- Second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13.
- a passing gate electrode 15 is formed on second gate insulating film 18.
- FIG. 9 The cross-section of the floating gate semiconductor layer direction in FIG. 6 is shown in FIG. 9.
- Field oxide film 16 having an island shape is formed on P-type silicon substrate 11 at the portion where the floating gate semiconductor layer and passing gate electrode cross.
- First gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11.
- Floating gate semiconductor layer 13 is formed on first gate insulating film 17.
- Second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13.
- a plurality of control electrodes 14 are formed on second insulating film 18, the control electrodes being spaced apart by a constant distance.
- a plurality of passing gate electrodes 15 are formed on second gate insulating film 18 between the respective control electrodes 14, so as to be isolated by control electrode 14 and insulating film 29.
- FIG. 10 The cross-section of the high concentration N-type impurity region direction in FIG. 6 is shown in FIG. 10.
- High concentration N-type impurity regions 12, which will be used as bit lines, are formed in a P-type silicon substrate 11.
- First gate insulating film 17 and second gate insulating film 18 are formed on the entire surface of p-type silicon substrate 11.
- a plurality of control electrodes 14 are formed on second gate insulating film 18, the control electrodes being spaced apart by a constant distance.
- a plurality of passing gate electrodes 15 are formed on second gate insulating film 18 between the respective control electrodes 14, so as to be isolated by control electrode 14 and insulating film 19.
- FIGS. 11a through 11j, 12a through 12j, 13a through 13j, and 14a through 14j Such description will be provided with reference to FIGS. 11a through 11j, 12a through 12j, 13a through 13j, and 14a through 14j.
- a buffer oxide film 20, a nitride film 21, and a first resist film 22 are formed sequentially on P-type silicon substrate 11.
- a field region having an island shape is defined through an exposure and development process, thereby selectively removing nitride film 21 from the field region.
- P-type silicon substrate 11 is thermally oxidized, thereby forming a field oxide film 16 in the field region. Then, first resist film 22, nitride 21, and oxide film 20 are removed. Alternatively, instead of using field oxide film 16, it is possible to form the channel isolation region by implanting P-type ions.
- a second resist film 23 is deposited. Through the exposure and development process, a bit line region is defined so as to be spaced apart by a constant distance. A high concentration N-type ion is implanted on P-type silicon substrate 11, thereby forming a high concentration N-type impurity region 12. At this time, an oxide film 20a is formed on the portion of the structure where high concentration N-type impurity region 12 is formed.
- first gate insulating film (oxide film) 17 is deposited to a thickness of about 70-200 ⁇ on the entire surface of P-type silicon substrate 11 including field oxide film 16.
- a P-type polycrystalline silicon layer 13a and a third resist film 24 are deposited sequentially on first gate insulating film 17.
- third resist film 24 is patterned so as to expose P-type polycrystalline silicon layer 13a at the portion where a control electrode 14 and a floating gate semiconductor layer 13 cross.
- an N-type impurity ion is implanted on exposed P-type polycrystalline silicon layer 13a.
- the P-type impurity concentration of P-type polycrystalline silicon layer 13a is about 10 15 -10 18 a atoms/cm 3 .
- the N-type impurity ion-implantation concentration is about 10 18 -10 21 atoms/cm 3 .
- third resist film 24 is removed.
- a fourth resist film 25 is deposited on P-type polycrystalline silicon layer 13a.
- a floating gate region is defined through the exposure and development process.
- P-type polycrystalline silicon layer 13a is selectively removed, thereby forming a floating gate semiconductor layer 13 on first gate insulating firm 17 between respective high concentration N-type impurity regions 12.
- FIG. 11(e), FIG. 11(f), FIG. 12(e), FIG. 12(f), FIG. 13(e), FIG. 13(f), FIG. 14(e), and FIG. 14(f) may be modified.
- P-type polycrystalline silicon layer 13a may be deposited and removed selectively, thereby forming floating gate semiconductor layer 13.
- N-type impurity ions may be selectively implanted on the portion where floating gate semiconductor layer 13 and control electrode 14 cross.
- a second gate insulating film 18 is deposited on the entire surface of first gate insulating film 17, including floating gate semiconductor layer 13. Then, a first N-type polycrystalline silicon layer 14a, a cap insulating film nitride film), and nitride film), and a fifth resist film 26 are deposited sequentially.
- An oxide film may be used as second gate insulating film 18.
- a structure wherein nitride film/oxide film are stacked, or a structure wherein oxide film/nitride film/oxide film are stacked, may be used.
- the N-type impurity concentration of first N-type polycrystalline silicon layer 14a is about 10 18 -10 21 atoms/cm 3 .
- a control electrode region is defined through the exposure and development process. Then, cap insulating film 29 and first N-type polycrystalline silicon layer 14a are selectively removed, thereby forming a control electrode 14. Alternatively, instead of using first N-type polycrystalline silicon layer 14a, it is possible to use a metal.
- an insulating film is deposited on the entire surface of second gate insulating film 18, including control electrode 14, and then etched back, thereby forming an insulating sidewall 27 on the sidewall of control electrode 14. At this time, most of exposed second gate insulating film 18 has been removed.
- a third gate insulating film 19 As shown in FIG. 11j, FIG. 12j, FIG. 13j, and FIG. 14j, a third gate insulating film 19, a high concentration second N-type polycrystalline silicon 15a, and a sixth resist film 28 are deposited on first gate insulating film 18 including control electrode 14. Then, a passing gate region is defined through the exposure and development process. Second N-type polycrystalline silicon layer 15a is selectively removed, thereby forming a passing gate electrode 15.
- a metal may be used as the material constituting passing gate electrode 15.
- a voltage of 5V is applied to the gate electrode of all passing transistors (Q1,1-Qn2), to thereby turn on all such passing transistors.
- a voltage corresponding to the data which will be recorded in a memory cell of the lowest row (n) is applied to a source terminal of the passing transistor.
- a voltage of -2 to -7V is applied to the corresponding bit line and the substrate is grounded.
- the data can be recorded by the aforementioned method.
- a second bit line (B/L2) is precharged by 2V in a state where all passing transistors (Q1,1-Qn2) are turned on.
- a third bit line (B/L3) is grounded, and the same voltage as that applied to bit line (B/L2) is applied to a first bit line (B/L1).
- first bit line (B/L1) is floated.
- a voltage is applied to the word line (W/L2) of a memory cell (M2,2) to be read, thereby reading the data through sensing simplifier (SA).
- a logic "1" is recorded in the stacked transistor (M2,2) for use as a data memory, since a channel is not formed between the source and drain of the cell, a voltage of 2V applied to the first bit line is detected by the sensing amplifier and produced. Thus, a logic "1" is read.
- the semiconductor memory device according to the present invention as described above has the following effects.
- the present invention uses a stacked transistor as a memory element, as in the general flash EEPROM.
- the programming or erasure of the cell is performed by using the passing transistor, so as to charge the floating gate of the stacked transistor with electrons or to precharge the charged electrons in the floating gate. Since the capture of electrons is not generated in the gate insulating film, the programming or erasure of the data is not limited.
- the present invention can be used as a DRAM in future applications.
- a capacitor is generally used as a memory element in a DRAM.
- no capacitor is used in the present invention.
- the area of the unit cell can be reduced, thereby improving integration.
- the process is complicated because the capacitor is formed with a trench or crown shape in order to obtain large capacitance in the unit area.
- no capacitor is used in the present invention, thereby simplifying the process.
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US08/879,135 US5950088A (en) | 1995-10-05 | 1997-06-19 | Semiconductor memory device and method of manufacturing the same |
US08/879,317 US5998827A (en) | 1995-10-05 | 1997-06-19 | Semiconductor memory device and method of manufacturing the same |
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US08/879,135 Expired - Lifetime US5950088A (en) | 1995-10-05 | 1997-06-19 | Semiconductor memory device and method of manufacturing the same |
US08/879,317 Expired - Lifetime US5998827A (en) | 1995-10-05 | 1997-06-19 | Semiconductor memory device and method of manufacturing the same |
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US08/879,317 Expired - Lifetime US5998827A (en) | 1995-10-05 | 1997-06-19 | Semiconductor memory device and method of manufacturing the same |
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JP (1) | JP2847507B2 (de) |
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US6054348A (en) * | 1998-05-15 | 2000-04-25 | Taiwan Semiconductor Manufacturing Company | Self-aligned source process |
US6429495B2 (en) * | 1998-06-17 | 2002-08-06 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with address programming circuit |
US6110779A (en) * | 1998-07-17 | 2000-08-29 | Advanced Micro Devices, Inc. | Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride |
TW399332B (en) * | 1998-08-12 | 2000-07-21 | United Microelectronics Corp | The structure of flash memory cell and the manufacturing method thereof |
JP3344563B2 (ja) * | 1998-10-30 | 2002-11-11 | シャープ株式会社 | 半導体装置 |
KR100387267B1 (ko) * | 1999-12-22 | 2003-06-11 | 주식회사 하이닉스반도체 | 멀티 레벨 플래쉬 이이피롬 셀 및 그 제조 방법 |
US6642111B1 (en) * | 2002-07-09 | 2003-11-04 | Powerchip Semiconductor Corp. | Memory device structure and method of fabricating the same |
JP4346322B2 (ja) * | 2003-02-07 | 2009-10-21 | 株式会社ルネサステクノロジ | 半導体装置 |
FR2891398A1 (fr) * | 2005-09-23 | 2007-03-30 | St Microelectronics Sa | Memoire non volatile reprogrammable |
US9431253B1 (en) * | 2015-08-05 | 2016-08-30 | Texas Instruments Incorporated | Fabrication flow based on metal gate process for making low cost flash memory |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5357464A (en) * | 1992-03-02 | 1994-10-18 | Hitachi, Ltd. | Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof |
US5557566A (en) * | 1991-03-30 | 1996-09-17 | Kabushiki Kaisha Toshiba | Semiconductor nonvolatile ram having E2PROM with a floating gate located above the midportion of the transistor channel |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61165896A (ja) * | 1985-01-17 | 1986-07-26 | Matsushita Electronics Corp | フロ−テイングゲ−ト型不揮発性メモリ素子 |
JPS62155568A (ja) * | 1985-12-27 | 1987-07-10 | Nec Corp | 不揮発性半導体記憶装置 |
JPH0817209B2 (ja) * | 1987-10-16 | 1996-02-21 | 松下電子工業株式会社 | 半導体装置 |
JP3114155B2 (ja) * | 1991-08-05 | 2000-12-04 | 日本電信電話株式会社 | アナログメモリ素子 |
US5336937A (en) * | 1992-08-28 | 1994-08-09 | State University Of New York | Programmable analog synapse and neural networks incorporating same |
US5446299A (en) * | 1994-04-29 | 1995-08-29 | International Business Machines Corporation | Semiconductor random access memory cell on silicon-on-insulator with dual control gates |
US5554552A (en) * | 1995-04-03 | 1996-09-10 | Taiwan Semiconductor Manufacturing Company | PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof |
US5541130A (en) * | 1995-06-07 | 1996-07-30 | International Business Machines Corporation | Process for making and programming a flash memory array |
US5753952A (en) * | 1995-09-22 | 1998-05-19 | Texas Instruments Incorporated | Nonvolatile memory cell with P-N junction formed in polysilicon floating gate |
-
1995
- 1995-10-05 KR KR1019950034120A patent/KR0179175B1/ko not_active IP Right Cessation
-
1996
- 1996-03-08 TW TW085102839A patent/TW300338B/zh not_active IP Right Cessation
- 1996-05-07 US US08/646,152 patent/US5687119A/en not_active Expired - Lifetime
- 1996-06-26 CN CNB961086467A patent/CN1163966C/zh not_active Expired - Fee Related
- 1996-08-28 DE DE69631315T patent/DE69631315T2/de not_active Expired - Lifetime
- 1996-08-28 EP EP96113764A patent/EP0767498B1/de not_active Expired - Lifetime
- 1996-10-03 JP JP8281285A patent/JP2847507B2/ja not_active Expired - Fee Related
-
1997
- 1997-06-19 US US08/879,135 patent/US5950088A/en not_active Expired - Lifetime
- 1997-06-19 US US08/879,317 patent/US5998827A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5557566A (en) * | 1991-03-30 | 1996-09-17 | Kabushiki Kaisha Toshiba | Semiconductor nonvolatile ram having E2PROM with a floating gate located above the midportion of the transistor channel |
US5357464A (en) * | 1992-03-02 | 1994-10-18 | Hitachi, Ltd. | Semiconductor memory having writing and reading transistors, method of fabrication thereof, and method of use thereof |
Cited By (17)
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---|---|---|---|---|
US6534812B1 (en) * | 1999-02-04 | 2003-03-18 | Sony Corporation | Memory cell with stored charge on its gate and a resistance element having non-linear resistance elements |
US8399920B2 (en) | 2005-07-08 | 2013-03-19 | Werner Juengling | Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls |
US9536971B2 (en) | 2005-07-08 | 2017-01-03 | Micron Technology, Inc. | Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls |
US8916912B2 (en) | 2005-07-08 | 2014-12-23 | Micron Technology, Inc. | Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls |
US8426273B2 (en) | 2005-08-30 | 2013-04-23 | Micron Technology, Inc. | Methods of forming field effect transistors on substrates |
US8877589B2 (en) | 2005-08-30 | 2014-11-04 | Micron Technology, Inc. | Methods of forming field effect transistors on substrates |
US8389363B2 (en) | 2006-02-02 | 2013-03-05 | Micron Technology, Inc. | Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates |
US8551823B2 (en) | 2006-07-17 | 2013-10-08 | Micron Technology, Inc. | Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines |
US20090239343A1 (en) * | 2006-07-17 | 2009-09-24 | Fernando Gonzalez | Methods Of Forming Lines Of Capacitorless One Transistor DRAM Cells, Methods Of Patterning Substrates, And Methods Of Forming Two Conductive Lines |
US9129847B2 (en) | 2006-07-17 | 2015-09-08 | Micron Technology, Inc. | Transistor structures and integrated circuitry comprising an array of transistor structures |
US8394699B2 (en) | 2006-08-21 | 2013-03-12 | Micron Technology, Inc. | Memory arrays and methods of fabricating memory arrays |
US8446762B2 (en) | 2006-09-07 | 2013-05-21 | Micron Technology, Inc. | Methods of making a semiconductor memory device |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20090016118A1 (en) * | 2007-07-12 | 2009-01-15 | Silicon Storage Technology, Inc. | Non-volatile dram with floating gate and method of operation |
US8391078B2 (en) * | 2008-02-12 | 2013-03-05 | Chip Memory Technology, Inc. | Method and apparatus of operating a non-volatile DRAM |
US20100238728A1 (en) * | 2008-02-12 | 2010-09-23 | Chip Memory Technology, Inc. | Method and apparatus of operating a non-volatile DRAM |
US9570593B2 (en) | 2012-04-20 | 2017-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH09129837A (ja) | 1997-05-16 |
US5998827A (en) | 1999-12-07 |
DE69631315D1 (de) | 2004-02-19 |
CN1163966C (zh) | 2004-08-25 |
JP2847507B2 (ja) | 1999-01-20 |
US5950088A (en) | 1999-09-07 |
KR970024197A (ko) | 1997-05-30 |
TW300338B (en) | 1997-03-11 |
DE69631315T2 (de) | 2004-10-21 |
CN1147674A (zh) | 1997-04-16 |
KR0179175B1 (ko) | 1999-03-20 |
EP0767498A1 (de) | 1997-04-09 |
EP0767498B1 (de) | 2004-01-14 |
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