US20050013106A1 - Peripheral card with hidden test pins - Google Patents

Peripheral card with hidden test pins Download PDF

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Publication number
US20050013106A1
US20050013106A1 US10621882 US62188203A US2005013106A1 US 20050013106 A1 US20050013106 A1 US 20050013106A1 US 10621882 US10621882 US 10621882 US 62188203 A US62188203 A US 62188203A US 2005013106 A1 US2005013106 A1 US 2005013106A1
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circuit board
includes
method according
die
step
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Abandoned
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US10621882
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Hem Takiar
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SanDisk Technologies LLC
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SanDisk Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772Physical layout of the record carrier
    • G06K19/07732Physical layout of the record carrier the record carrier having a housing or construction similar to well-known portable memory devices, such as SD cards, USB or memory sticks
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns, inspection means or identification means
    • H05K1/0268Marks, test patterns, inspection means or identification means for electrical inspection or testing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49004Electrical device making including measuring or testing of device or component part
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49169Assembling electrical component directly to terminal or elongated conductor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49174Assembling terminal to elongated conductor
    • Y10T29/49179Assembling terminal to elongated conductor by metal fusion bonding

Abstract

A peripheral card includes a circuit board, various circuit elements on the circuit board, a set of user terminals, a set of test terminals, and an enclosure that covers a portion of the circuit board and the circuit elements. The enclosure does not cover the user terminals and test terminals. After the peripheral card is tested, the test terminals are covered with a conformal contact coating in order to prevent access to the test terminals.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This Application is related to U.S. patent application Ser. No. ______, “Method For Efficiently Producing Removable Peripheral Cards,” filed Jun. 23, 2003, Hem P. Takiar, Atty. Docket SDK1P014/370, which is incorporated herein by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention is directed to technology for peripheral cards.
  • 2. Description of the Related Art
  • Memory cards are relatively small removable cards that provide data storage. In most cases, but not required in all cases, the memory card is integrated circuit based. These memory cards plug into or are received by ports or connectors on electronic devices, including computing devices, cameras, mobile telephones, PDAs and other devices. One example of a memory card uses non-volatile memory. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories. Some examples of memory cards includes CompactFlash™, MMC™, Smart Media, Secure Digital™, and the Memory Stick.
  • A flash memory card is a memory card that has one or more arrays of flash memory cells. Some flash memory cards also include bit line decoders, word line decoders, a state machine, a controller and other circuitry. In many cases the controller will be implemented in a first semiconductor die, while the array of flash memory cells, bit line decoders, word line decoders, and state machine are implemented in a second semiconductor die. Over time, flash memory arrays have increased density by shrinking the size of an individual memory cell and by implementing greater numbers of memory cells in the array.
  • To maintain product reliability and customer satisfaction, manufacturers of memory cards will test the memory cards during the manufacturing process in order to determine if there are any manufacturing defects. In many cases, the user I/O pins on the memory card connect to the controller. However, a test performed during manufacturing typically seeks to directly access the memory array (bypassing the controller) in order to test each cell in the memory array. Additionally, more pins will allow for more efficient and complete testing of the relevant components of the memory card. Thus, many memory cards will include test pins, in addition to the user I/O pins. To protect the memory card from electrostatic discharge relative to the test pins and to protect the data on the card from being wrongfully accessed via the test pins, the test pins should not be exposed to the user of the memory card after the manufacturing process.
  • One example of a memory card is described in U.S. Pat. No. 6,410,355 (the '355 patent”), incorporated herein by reference in its entirety. In the '355 patent, a memory card using flash memory is manufactured with a set of test pins at one edge of the memory card. After the memory card is tested, the test pins are cut off of the memory card and the memory card is then packaged. While the device of the '355 patent has worked well, there is a need for an improvement. First, the test pins that are cut off use real estate on the circuit board. There is a trend to increase density on circuit boards; therefore, it would be advantageous to not use a portion of the circuit board for components that will not ship to customers. Second, if the memory card fails in the field, there are no test pins to test the device in order to determine why the memory card failed. Such tests following device failure allow a manufacturer of memory cards to improve device reliability and the manufacturing process.
  • Another example of a memory card using flash memory is the recently released Mini-SD Card. In one commercial version of the Mini-SD Card, the memory array is mounted on the top of the circuit board and the controller is mounted on the memory array. User I/O pins and test pins are formed on the bottom of the circuit board. After the memory card is tested, the circuit board (with the controller, memory array and other components) are enclosed by attaching a top lid to a bottom lid. Both the bottom lid and the top lid are made of a hard plastic, and are manufactured from a mold prior to enclosing the circuit board. After the top and bottom lids are made, the top lid is ultra- sonically welded to the bottom lid to enclose the circuit board (with the controller, memory array and other components). The bottom lid has an opening for the user I/O pins. The bottom lid does not have an opening for the test pins; therefore, the test pins are not exposed to users. There will be a small air gap between the bottom lid and the bottom of the circuit board While this design works well, the top and bottom lids are relatively expensive to manufacture. Additionally, the lids are relatively bulky which limits how small the memory cards can be manufactured. The trend in the industry to further decrease the size of memory cards.
  • Thus, there is a need to provide for test pins for a memory card without the limitations described above. Similar issues exist with other types of peripheral cards, such as peripheral cards that implement wireless communication devices, GPS devices, cellular devices, network interfaces, modems, disk storage systems, and other devices.
  • SUMMARY OF THE INVENTION
  • The present invention, roughly described, pertains to technology for a peripheral card with hidden test pins. One embodiment of the present invention includes a circuit board, circuit elements on said circuit board, a set of user terminals on the circuit board that are in communication with at least a subset of the circuit elements, a set of test terminals on said circuit board that are in communication with one or more of the circuit elements, an enclosure that covers a portion of the circuit board without covering the set of user terminals and the set of test terminals, and a conformal contact coating on a first surface of the circuit board covering the test terminals and preventing access to the test terminals.
  • One embodiment of manufacturing such a peripheral card includes adding circuit elements to a circuit board, where the circuit board (at some point in time) includes a set of test terminals. One or more of the circuit elements are tested using the test terminals. The test terminals are subsequently covered with a conformal contact coating in order to prevent access to the test terminals. In one implementation, the test terminals are covered with a conformal contact coating by applying a liquid directly to a first surface of the circuit board. In another implementation, the test terminals are covered with a conformal contact coating by applying a film directly to a first surface of said circuit board.
  • Some embodiments of the present invention will include manufacturing the peripheral cards a batch at a time, followed by singulation of the batch into individualized memory cards. The present invention allows for the covering of the test pins before or after singulation. For example, one implementation includes the steps of adding circuit elements to a plurality of circuit boards of a strip (each of the plurality of circuit boards includes a set of test terminals), separating the connected circuit boards, testing the circuit elements of the circuit boards using the test terminals, and applying a conformal contact coating on a first surface of each of the circuit boards. The conformal contact coating covers the test terminals and prevents access to the test terminals such that a particular circuit board has its test terminals covered after that particular circuit board has been tested.
  • The present invention can be applied to the manufacture of memory cards, including flash memory cards. The technology disclosed herein can also be applied to other peripheral cards. For example, the present invention can be used with removable peripheral cards that include wireless communication devices, GPS devices, cellular devices, network interfaces, modems, disk storage systems, and other devices. The present invention is not limited to any one type of peripheral card and is meant to be used with many different types of peripheral cards.
  • These and other objects and advantages of the present invention will appear more clearly from the following description in which the preferred embodiment of the invention has been set forth in conjunction with the drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a perspective view of the bottom of a memory card according to a first embodiment of the present invention.
  • FIG. 2 is a perspective view of the top of the memory card according to the first embodiment of the present invention.
  • FIG. 3 is a first side view of the memory card according to the first embodiment of the present invention.
  • FIG. 4 is a perspective view of the top of a memory card according to a second embodiment of the present invention.
  • FIG. 5 is a perspective view of the top of a memory card according to a third embodiment of the present invention.
  • FIG. 6 is a perspective view of the top of a memory card according to a fourth embodiment of the present invention.
  • FIG. 7 is a perspective view of the bottom of the memory card according to the fourth embodiment of the present invention.
  • FIG. 8 is a perspective view of the top of a memory card according to a fifth embodiment of the present invention.
  • FIG. 9 is a perspective view of the bottom of the memory card according to the fifth embodiment of the present invention.
  • FIG. 10 is a side view of the memory card according to the fifth embodiment of the present invention.
  • FIG. 11 is a top view of a circuit board used for various embodiments of the present invention.
  • FIG. 12 is a bottom view of the circuit board used for various embodiments of the present invention.
  • FIG. 13 is a cross section of an exemplar circuit board.
  • FIG. 14 is a cross sectional view of one embodiment of a circuit board and various components on the circuit board during the manufacturing process.
  • FIG. 15 is a cross sectional view of one embodiment of a circuit board and various components encapsulated on the circuit board during the manufacturing process.
  • FIG. 16 is a cross sectional view of one embodiment of a circuit board and various components on the circuit board, with a conformal contact coating applied to a surface of the circuit board.
  • FIG. 17 is a flow chart describing one embodiment of a process for manufacturing a memory card according to the present invention.
  • FIG. 18 is a plan view of a strip of memory cards prior to singulation.
  • FIG. 19 is a perspective view of the top of the memory card according to an additional embodiment of the present invention.
  • FIG. 20 is a perspective view of the bottom of the memory card according to the embodiment of FIG. 19.
  • FIG. 21 is a perspective view of the top of the memory card according to an additional embodiment of the present invention.
  • FIG. 22 is a perspective view of the bottom of the memory card according to the embodiment of FIG. 21.
  • DETAILED DESCRIPTION
  • FIGS. 1-10 depict various embodiments of a memory card. For example, FIG. 1 is a perspective view of the bottom of a memory card according to a first embodiment of the present invention. FIG. 2 is a perspective view of the top of the memory card according to the first embodiment of the present invention. FIG. 3 is a side view of the memory card according to the first embodiment of the present invention. The memory card of FIGS. 1-3 includes a top surface 10, a bottom surface, a front surface 12, a back surface 14 and two side surfaces. One of the side surfaces has an angle portion 16. Top surface 10 has a raised portion 18 adjacent to back surface 14. Raised portion 18 allows the memory card to be more easily grabbed by a human hand (or mechanical device) and also provides additional room to store passive devices such as capacitors and/or resistors. Note that raised portion 18 of FIG. 1 has a curved profile. The bottom surface includes a first portion 22 and a second portion 24. Second portion 24 is raised from first portion 22. First portion 22 includes a set of user I/O pins 26 and corresponds to a bottom surface of a circuit board, as discussed below.
  • In one implementation, the memory card is 12 mm wide and 15 mm long. The angled portion is at a forty five degree angle. The thickness of the memory card is 0.9 mm at second portion 24, 1.0 mm at raised portion 18 and 0.8 mm at first portion 22. In another embodiment, the thickness of the memory card is 0.8 mm at second portion 24, 1.0 mm at raised portion 18 and 0.7 mm at first portion 22. In other embodiments, other dimensions can also be used.
  • In one embodiment, a label will be placed on the top surface. This label can be a sticker or can be ink which is pad printed.
  • FIG. 4 is a perspective view of the top of a memory card according to a second embodiment of the present invention. The second embodiment includes a raised portion 1 8a that has a straight profile. FIG. 5 is a perspective view of the top of a memory card according to a third embodiment of the present invention which does not include a raised portion 18.
  • FIG. 6 is a perspective view of the top of a memory card according to a fourth embodiment of the present invention. FIG. 7 is a perspective view of the bottom of the memory card according to the fourth embodiment of the present invention. The fourth embodiment includes notch 30. The notch is used to secure the card in position when connected to a host device.
  • FIG. 8 is a perspective view of the top of the memory card according to a fifth embodiment of the present invention. FIG. 9 is a perspective view of the bottom of the memory card according to the fifth embodiment of the present invention. FIG. 10 is a side view of the memory card according to the fifth embodiment of the present invention. The fifth embodiment of the present invention implements a different orientation than the other embodiments described above. For example, the top surface of the memory card in the fifth embodiment includes a raised portion 54 adjacent back edge 52, which runs along the length as opposed to the width of the memory card. The memory card of the fifth embodiment includes a front surface 50 that also runs along the length of the memory card. The bottom surface of the memory card includes a first portion 54 and second portion 56. First portion 54 includes a set of user I/O pins 58 and corresponds to a bottom surface of a circuit board, as discussed below. Second portion 56 is raised from first portion 54.
  • FIG. 11 provides a top view of a circuit board used for various embodiments of the present invention. FIG. 11 shows circuit board 200. Mounted on circuit board 200 are first die 202 and second die 204. In one embodiment, die 202 includes a flash memory array with associated circuitry and die 204 includes a controller. In some embodiments, the memory card may include more than one memory array. In embodiments that include a peripheral card other than a memory card, the dies can be components other than or in addition to memory arrays and controllers. Note that die 202 includes contacts 212 (e.g. die bond pads) which are used to connect die 202 to other components. Similarly, die 204 includes contacts 214 (e.g. die bond pads) to connect die 204 to other components. Circuit board 200 also includes passive components 220, which could include capacitors and/or resistors. Circuit board 200 includes a number of conductive traces (not shown) which interconnect the devices mounted on the circuit board. Connecting regions (not depicted) are provided on the circuit board so that the leads from dies can be connected to the circuit board by conventional wire bonding. In other embodiments, other means different than wire bonding can be used to connect the dies to the circuit board.
  • FIG. 12 shows the bottom of circuit board 200. In one embodiment, the bottom of circuit board 200 includes user I/O pins 230 and test pins 232. FIG. 12 depicts eight user I/O pins 230 and sixteen test pins 232; however, different numbers of pins can also be used. The test pins 232 can include data pins and/or power pins. The test pins are used to test one or more of the components of the memory card. For example, the test pins can be used to test each of the cells of the memory array. The user I/O pins 230 are used by a host device connected to the memory card in order to communicate with the memory card. For example, the user I/O pins 230 can be used to communicate with the controller on die 204. Note that in order to have a small package, one embodiment of the present invention includes mounting the integrated circuits on a first surface of the circuit board (e.g. the top surface) and forming the terminals (user I/O pins and test pins) on a conductive layer on another surface of the circuit board (e.g. the bottom surface).
  • FIG. 13 shows a cross sectional view of circuit board 200. FIG. 13 shows five layers 260, 262, 264, 266, and 268. Other embodiments have less than or more than five layers. Layer 260, the middle layer, is an insulating core layer. Layers 262 and 264 are routing layers, which include conductive metal traces. Layers 266 and 268 include solder masks. Connections between layers (such as layers 262 and 264) can be made by conductive vias. In one embodiment, the circuit board is a printed circuit board. In another embodiment, the circuit board is a lead frame. Other types of circuit boards may also be used within the spirit of the present invention.
  • FIGS. 14-16 graphically depict the manufacturing process for creating the memory card according one embodiment of the present invention. FIG. 14 is a side view of the memory card during the manufacturing process, prior to encapsulation. FIG. 14 depicts circuit board 200. Mounted on circuit board 200 is die 202. Mounted on die 202 is die 204. FIG. 14 shows die 202 and die 204 wire bonded to circuit board 200. FIG. 14 also shows passive devices 220, which can be capacitors and/or resistors. In one embodiment, die 202 is mounted on circuit board 200 using an adhesive material. The adhesive material may be an epoxy adhesive, soft solder or any other adhesive material for mounting a die to a substrate. Die 204 is mounted on die 202 by way of an adhesive material applied to the top surface of die 202 and the bottom surface of die 204. More information about stacking two dies on top of each other can be found in U.S. Pat. No. 5,502,289, incorporated herein by reference in its entirety. In one embodiment, the passive devices are surface mounted using solder.
  • FIG. 15 shows the memory card of FIG. 14 after encapsulation. That is, using an injection mold process or a transfer mold process, molding material 280 is used to encapsulate the components of the memory card. Note that the encapsulation covers the side surfaces, front surface, back surface, and top surface of circuit board 200. The encapsulation also covers all the components mounted on the top surface of circuit board 200. The bottom surface of circuit board 200, which includes user I/O pins 230 and test pins 232, is not covered by the encapsulation.
  • Subsequent to encapsulation, a conformal contact coating 290 is applied to a portion of the bottom surface of circuit board 200 in order to cover test pins 232. The conformal contact coating does not cover user I/O pins 230. FIG. 16 depicts the memory card after the conformal contact coating 290 has been applied. For example, the conformal contact coating 290 is applied to portion 24 (see FIG. 1) of the bottom surface of the memory card, but not to portion 22 of the memory card. The conformal contact coating protects the test pins from electrostatic discharge and protects the data in the memory from unwanted access via the test pins by blocking the test pins. The coating is a conformal contact coating because it conforms to the shape of the surface it is being applied to and it is in direct contact to that surface. Some other memory cards may use a lid to cover the bottom of the circuit board. That lid is not in contact with the bottom surface of the circuit board. Rather, an air gap will exist between the bottom lid and circuit board. Additionally, because the lid is prefabricated it will not conform to the shape of the bottom surface of the bottom of the circuit board.
  • In one embodiment, the application of the conformal contact coating includes applying a liquid directly to the bottom surface of the circuit board. The coating then dries to a solid. In another embodiment, the coating is applied as a film directly to the bottom surface of the circuit board. Examples of coatings include photoresist, solder mask, epoxy, thermoplastic, and polyimide. One specific example of a suitable coating is the PSR-400 Solder Mask from Taiyo America, Inc., www.taivo-america.com. Examples of a film include mylar with an adhesive or polyimide with an adhesive. An example of a suitable polyimide is Kapton, by DuPont. One example of how to apply a liquid coating is to use a screen printing process.
  • FIG. 17 is a flowchart depicting one embodiment of a process for manufacturing a memory card according to the present invention. In step 400, vias are drilled in the circuit board. In step 402, a top pattern is applied to circuit board 200 to add the conductive traces and connection regions discussed above. In step 404, a bottom pattern is applied to the bottom surface of circuit board 200 to add the user I/O pins 230, 232 test pins and conductive traces. In step 406, solder mask is added to the top surface of circuit board 200. In step 408, the solder mask is added to the bottom surface of circuit board 200. In step 410, first die 202 is mounted to circuit board 200. In step 412, second die 204 is mounted to circuit board 200. In step 414, passive devices 220 are mounted to circuit board 200. In step 416, wire bonds are added to connect dies 202 and 204 to circuit board 200. In one embodiment, protective coatings are applied to the wire bonds and/or the dies. In step 418, circuit board 200 and the components mounted on circuit board 200 are subject to a transfer mold process so that the circuit board and its components are encapsulated, as described above. However, the encapsulation process of step 418 does not cover the bottom surface of circuit board 200.
  • In one embodiment, a memory card is manufactured as a unitary structure. In that case, step 420 is skipped and the process of FIG. 17 proceeds to step 422. However, in other embodiments the memory cards are produced a batch at a time. That is, a strip of memory cards are produced at one time and then a singulation process is performed to cut the strip into individualized memory cards. In the case where the memory cards are produced at a batch at a time, step 420 includes cutting the strip to separate the various memory cards. Step 420 is referred to as singulation.
  • In step 422, the memory cards are tested. In step 424, the test pins are covered, as described above, by applying the conformal contact coating to a portion of the bottom surface of the circuit board 200 (e.g. bottom portion 24 of FIG. 1).
  • Step 422 includes testing the memory cards. During the manufacturing process, the manufacturer may perform a bum-in test of the memory card to verify that each of the memory cells in the memory array are functional. The manufacturer may then program the memory card to avoid bad memory cells. For example, the memory array may include a portion of memory that stores addresses for bad memory cells and pointers to replacement memory cells. In some embodiments, the other components of the memory card may also be tested. Note that FIG. 17 shows that the devices are tested and receive the conformal contact coating after singulation. In another embodiment, step 420 is performed after to step 422; therefore, the various devices are tested and receive the conformal contact coating prior to singulation.
  • FIG. 18 is a plan view of a strip of memory cards prior to singulation. FIG. 18 shows strip 500. On top of strip 500 are various instances of the memory cards. Each memory card is depicted in dashed lines. In one embodiment, strip 500 includes 100 memory cards (5 wide, 20 long). Note that other numbers of memory cards can also be manufactured on a strip. Strip 500 is manufactured by performing steps 400-418 simultaneously for each of the memory cards on the strip. That is, the steps are performed on the strip as a whole. Step 420 is performed by cutting the strip into separate devices. According to one aspect of the present invention, the memory cards are not fully rectangular in their shape. Therefore, the singulation of the strip into individual memory cards includes nonlinear (e.g. curvilinear) sawings. Such sawing can be performed efficiently with a very thin saw with high precision and detail, such that the sawing action is very fine. Examples of the sawing devices include, for example, a water jet cutting device, a laser cutting apparatus, a water guided laser, a dry media cutting device, and a diamond coated wire. Water jet cutting may be the preferred cutting method given its small cutting width (e.g. 50 microns), its ability to shape small features and its rapid cutting rate.
  • If the memory card fails after it is in use, then the failed memory card can be debugged by removing the conformal contact coating and using the test pins to test the memory card.
  • FIG. 19 is a perspective view of the top of the memory card according to an additional embodiment of the present invention. FIG. 20 is a perspective view of the bottom of the memory card according to the embodiment of FIG. 19. Card 600 depicted in FIGS. 19 and 20 includes rounded notches 602 and 604, raised portion 606 and angled portion 608. Bottom surface 612 includes pins 620 and portion 622. Portion 622 is raised from surface 612 and covers the test pins as described herein.
  • FIG. 21 is a perspective view of the top of the memory card according to an additional embodiment of the present invention. FIG. 22 is a perspective view of the bottom of the memory card according to the embodiment of FIG. 21. Card 700 depicted in FIGS. 21 and 22 includes notch 702, raised portion 706 and angled portion 708. Bottom surface 712 includes pins 720 and portion 722. Portion 722 is raised from surface 712 and covers the test pins as described herein.
  • The description above specifically discusses memory cards. One set of embodiments of the present invention specifically pertain to flash memory cards, which include one or more memory arrays that utilize flash memory technology. The embodiments explained above pertaining to memory cards are for example purposes and are not mean to limit the invention. The technology disclosed herein can also be applied to other peripheral cards that connect to a computing device and are controlled or operated with the computing device. One example of a removable peripheral card is a PCMCIA card. Examples of applications, in addition to memory systems, that can be implemented on peripheral cards include wireless communication devices, GPS devices, cellular devices, network interfaces, modems, disk storage systems, etc. The present invention is not limited to any one type of peripheral card and is meant to be used with many different types of peripheral cards.
  • The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.

Claims (51)

  1. 1. A method of making a memory card card, comprising the steps of:
    adding circuit elements to a circuit board, said circuit board includes a set of test terminals;
    testing one or more of said circuit elements using said test terminals; and
    covering said test terminals with a conformal contact coating in order to prevent access to said test terminals.
  2. 2. A method according to claim 1, wherein:
    said step of covering includes applying a liquid directly to a first surface of said circuit board.
  3. 3. A method according to claim 2, wherein:
    said liquid includes a solder mask.
  4. 4. A method according to claim 2, wherein:
    said liquid includes a photoresist.
  5. 5. A method according to claim 2, wherein:
    said liquid includes a thermoplastic.
  6. 6. A method according to claim 2, wherein:
    said liquid includes an epoxy.
  7. 7. A method according to claim 2, wherein:
    said liquid includes polyimide.
  8. 8. A method according to claim 2, wherein:
    said liquid is applied using a screen printing process.
  9. 9. A method according to claim 1, wherein:
    said step of covering includes applying a film directly to a first surface of said circuit board.
  10. 10. A method according to claim 9, wherein:
    said film includes an adhesive on one surface.
  11. 11. A method according to claim 9, wherein:
    said film includes mylar.
  12. 12. A method according to claim 9, wherein:
    said film includes polyimide.
  13. 13. A method according to claim 1, wherein:
    said step of adding circuit elements includes adding a flash memory array to said circuit board.
  14. 14. A method according to claim 1, wherein:
    said step of adding circuit elements includes mounting a first die on said circuit board and mounting a second die on said first die.
  15. 15. A method according to claim 14, wherein:
    said first die includes a flash memory array and said second die includes a controller.
  16. 16. A method according to claim 14, wherein:
    said first die is wire bonded to said circuit board; and
    said second die is wire bonded to said circuit board.
  17. 17. A method according to claim 1, wherein:
    said circuit board includes a conductive layer and a first portion of said conductive layer forms said test terminals.
  18. 18. A method according to claim 17, wherein:
    a second portion of said conductive layer forms user terminals;
    said user terminals are positioned on an outside surface of said memory card; and
    said user terminals are in communication with at least a subset of said circuit elements.
  19. 19. A method according to claim 1, wherein:
    said step of adding circuit elements includes performing a transfer mold process to encapsulate said circuit elements without covering said test terminals.
  20. 20. A method according to claim 1, wherein:
    said step of covering is performed after said circuit board is removed from a strip of circuit boards.
  21. 21. A method according to claim 1, wherein:
    said step of covering is performed before said circuit board is removed from a strip of circuit boards.
  22. 22. A method according to claim 1, wherein:
    said memory card is a flash memory card.
  23. 23. A method according to claim 22, wherein:
    said step of covering includes applying a liquid directly to a first surface of said circuit board.
  24. 24. A method according to claim 22, wherein:
    said step of covering includes applying a film directly to a first surface of said circuit board.
  25. 25. A method of making a peripheral card, comprising the steps of:
    adding circuit elements to a plurality of circuit boards of a strip of circuit boards, each of said plurality of circuit boards includes a set of test terminals;
    separating said connected circuit boards;
    testing said circuit elements of said circuit boards using said test terminals; and
    applying a conformal contact coating on a first surface of each of said circuit boards to cover said test terminals and prevent access to said test terminals such that a particular circuit board has its test terminals covered after said particular circuit board has been tested.
  26. 26. A method according to claim 25, wherein:
    said step of separating is performed after said step of applying.
  27. 27. A method according to claim 25, wherein:
    said step of separating is performed prior to said step of applying.
  28. 28. A method according to claim 25, wherein:
    said step of applying includes applying a liquid directly to a first surface of said circuit boards.
  29. 29. A method according to claim 25, wherein:
    said step of applying includes applying a film directly to a first surface of said circuit boards.
  30. 30. A method according to claim 25, wherein:
    said step of adding circuit elements includes mounting a first die on a first circuit board and mounting a second die on said first die;
    said first die includes a flash memory array and said second die includes a controller;
    said first die is wire bonded to said first circuit board; and
    said second die is wire bonded to said first circuit board.
  31. 31. A method according to claim 25, wherein:
    said peripheral card is a memory card.
  32. 32. A peripheral card manufactured according to a process comprising the steps of:
    adding circuit elements to a circuit board, said circuit board includes a set of test terminals;
    testing one or more of said circuit elements using said test terminals; and
    applying a conformal contact coating on a first surface of said circuit board to cover said test terminals and prevent access to said test terminals.
  33. 33. A peripheral card according to claim 32, wherein:
    said step of applying includes applying a liquid directly to a first surface of said circuit board.
  34. 34. A peripheral card according to claim 32, wherein:
    said step of applying includes applying a film directly to a first surface of said circuit board.
  35. 35. A peripheral card according to claim 32, wherein:
    said circuit board includes a first die mounted on said circuit board and a second die mounted on said first die;
    said first die includes a flash memory array and said second die includes a controller;
    said first die is wire bonded to said circuit board; and
    said second die is wire bonded to said circuit board.
  36. 36. A peripheral card according to claim 32, wherein:
    said circuit board includes a conductive layer;
    a first portion of said conductive layer forms said test terminals;
    a second portion of said conductive layer forms user terminals;
    said user terminals are positioned on an outside surface of said peripheral card; and
    said circuit elements are encapsulated by a transfer mold process without covering said test terminals.
  37. 37. A peripheral card according to claim 32, wherein:
    said peripheral card is a memory card.
  38. 38. A peripheral card, comprising:
    a circuit board;
    circuit elements on said circuit board;
    a set of user terminals on said circuit board, said user terminals are in communication with at least a subset of said circuit elements;
    a set of test terminals on said circuit board, said test terminals are in communication with one or more of said circuit elements;
    an enclosure that covers a portion of said circuit board and said circuit elements without covering said set of user terminals and said set of test terminals; and
    a conformal contact coating on a first surface of said circuit board covering said test terminals and preventing access to said test terminals.
  39. 39. A peripheral card according to claim 38, wherein:
    said conformal contact coating is applied as a liquid directly to said first surface of said circuit board.
  40. 40. A peripheral card according to claim 38, wherein:
    said conformal contact coating includes a film that is applied directly to said first surface of said circuit board.
  41. 41. A peripheral card according to claim 38, wherein:
    said circuit elements board include a first die mounted on said circuit board and a second die mounted on said first die.
  42. 42. A peripheral card according to claim 41, wherein:
    said first die is wire bonded to said circuit board; and
    said second die is wire bonded to said circuit board.
  43. 43. A peripheral card according to claim 42, wherein:
    said first die includes a flash memory array and said second die includes a controller.
  44. 44. A peripheral card according to claim 41, wherein:
    said first die includes a flash memory array and said second die includes a controller.
  45. 45. A peripheral card according to claim 38, wherein:
    said circuit board includes a conductive layer;
    a first portion of said conductive layer forms said test terminals;
    a second portion of said conductive layer forms said user terminals; and
    said user terminals are positioned on an outside surface of said peripheral card.
  46. 46. A peripheral card according to claim 38, wherein:
    said peripheral card is a memory card.
  47. 47. A method performed for a peripheral card, comprising the steps of:
    testing one or more circuit elements of a first peripheral card using one or more test terminals of said first peripheral card; and
    covering said test terminals with a conformal contact coating in order to prevent access to said test terminals.
  48. 48. A method according to claim 47, wherein:
    said step of covering includes applying a liquid directly to said first peripheral card.
  49. 49. A method according to claim 47, wherein:
    said step of covering includes applying a film directly to said first peripheral card.
  50. 50. A method according to claim 47, wherein:
    said circuit elements include a flash memory array.
  51. 51. A method according to claim 47, wherein:
    said first peripheral card is a memory card.
US10621882 2003-07-17 2003-07-17 Peripheral card with hidden test pins Abandoned US20050013106A1 (en)

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Application Number Priority Date Filing Date Title
US10621882 US20050013106A1 (en) 2003-07-17 2003-07-17 Peripheral card with hidden test pins

Applications Claiming Priority (19)

Application Number Priority Date Filing Date Title
US10621882 US20050013106A1 (en) 2003-07-17 2003-07-17 Peripheral card with hidden test pins
US10782969 US7307848B2 (en) 2003-07-17 2004-02-20 Memory card with raised portion
US10851466 US7416132B2 (en) 2003-07-17 2004-05-20 Memory card with and without enclosure
TW93119088A TWI251785B (en) 2003-07-17 2004-06-29 Memory card with raised portion
TW93119109A TWI248619B (en) 2003-07-17 2004-06-29 Peripheral card with hidden test pins
JP2006520195A JP2007531083A (en) 2003-07-17 2004-06-30 Memory card with a raised portion
PCT/US2004/021253 WO2005010812A1 (en) 2003-07-17 2004-06-30 Peripheral card with hidden test pins
KR20067001155A KR20060063896A (en) 2003-07-17 2004-06-30 Peripheral card with hidden test pins
PCT/US2004/020898 WO2005010808A3 (en) 2003-07-17 2004-06-30 Memory card with raised portion
JP2006520207A JP2007531920A (en) 2003-07-17 2004-06-30 Peripheral card with a hidden test pin
EP20040756368 EP1649410A2 (en) 2003-07-17 2004-06-30 Memory card with raised portion
CN 200480020546 CN100589121C (en) 2003-07-17 2004-06-30 Memory card with raised portion
EP20040777413 EP1649413A1 (en) 2003-07-17 2004-06-30 Peripheral card with hidden test pins
KR20067001156A KR101199600B1 (en) 2003-07-17 2004-06-30 Memory card with raised portion
CN 200480020545 CN1823341A (en) 2003-07-17 2004-06-30 Memory card with raised portion
US10952591 US7336498B2 (en) 2003-07-17 2004-09-28 Memory card with push-push connector
US10952609 US7306160B2 (en) 2003-07-17 2004-09-28 Memory card with adapter
US10995989 US7306161B2 (en) 2003-07-17 2004-11-23 Memory card with chamfer
US11930909 US7864540B2 (en) 2003-07-17 2007-10-31 Peripheral card with sloped edges

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US29186546 Continuation-In-Part USD525248S1 (en) 2003-07-17 2003-07-17 Memory card
US29194064 Continuation-In-Part USD523435S1 (en) 2003-07-17 2003-11-19 Memory card

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US29186546 Continuation-In-Part USD525248S1 (en) 2003-07-17 2003-07-17 Memory card
US29194064 Continuation-In-Part USD523435S1 (en) 2003-07-17 2003-11-19 Memory card
US10782969 Continuation US7307848B2 (en) 2003-07-17 2004-02-20 Memory card with raised portion
US10851466 Continuation-In-Part US7416132B2 (en) 2003-07-17 2004-05-20 Memory card with and without enclosure

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US20050013106A1 true true US20050013106A1 (en) 2005-01-20

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US10621882 Abandoned US20050013106A1 (en) 2003-07-17 2003-07-17 Peripheral card with hidden test pins
US10782969 Active 2024-01-08 US7307848B2 (en) 2003-07-17 2004-02-20 Memory card with raised portion

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EP (1) EP1649413A1 (en)
JP (1) JP2007531920A (en)
KR (1) KR20060063896A (en)
CN (2) CN1823341A (en)
WO (1) WO2005010812A1 (en)

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