DE602005021196D1 - Halbleiterbauelement und eine Methode zur dessen Herstellung - Google Patents

Halbleiterbauelement und eine Methode zur dessen Herstellung

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Publication number
DE602005021196D1
DE602005021196D1 DE602005021196T DE602005021196T DE602005021196D1 DE 602005021196 D1 DE602005021196 D1 DE 602005021196D1 DE 602005021196 T DE602005021196 T DE 602005021196T DE 602005021196 T DE602005021196 T DE 602005021196T DE 602005021196 D1 DE602005021196 D1 DE 602005021196D1
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Germany
Prior art keywords
production
semiconductor device
semiconductor
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DE602005021196T
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English (en)
Inventor
Yosuke Shimamune
Akira Katakami
Akiyoshi Hatada
Masashi Shima
Naoyoshi Tamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Application filed by Fujitsu Semiconductor Ltd filed Critical Fujitsu Semiconductor Ltd
Publication of DE602005021196D1 publication Critical patent/DE602005021196D1/de
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
DE602005021196T 2004-12-28 2005-04-12 Halbleiterbauelement und eine Methode zur dessen Herstellung Active DE602005021196D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004380619A JP4369359B2 (ja) 2004-12-28 2004-12-28 半導体装置

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DE602005021196D1 true DE602005021196D1 (de) 2010-06-24

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Country Status (7)

Country Link
US (8) US7791064B2 (de)
EP (1) EP1677360B1 (de)
JP (1) JP4369359B2 (de)
KR (1) KR100657395B1 (de)
CN (1) CN100470838C (de)
DE (1) DE602005021196D1 (de)
TW (1) TWI258218B (de)

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JP4369359B2 (ja) 2004-12-28 2009-11-18 富士通マイクロエレクトロニクス株式会社 半導体装置
US7335959B2 (en) * 2005-01-06 2008-02-26 Intel Corporation Device with stepped source/drain region profile
JP2006351581A (ja) * 2005-06-13 2006-12-28 Fujitsu Ltd 半導体装置の製造方法
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof
JP4984665B2 (ja) * 2005-06-22 2012-07-25 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US8105908B2 (en) * 2005-06-23 2012-01-31 Applied Materials, Inc. Methods for forming a transistor and modulating channel stress
US7494858B2 (en) * 2005-06-30 2009-02-24 Intel Corporation Transistor with improved tip profile and method of manufacture thereof
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