TWI715311B - 具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法 - Google Patents

具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法 Download PDF

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TWI715311B
TWI715311B TW108142879A TW108142879A TWI715311B TW I715311 B TWI715311 B TW I715311B TW 108142879 A TW108142879 A TW 108142879A TW 108142879 A TW108142879 A TW 108142879A TW I715311 B TWI715311 B TW I715311B
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drain
layer
silicon
substrate
metal oxide
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TW108142879A
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TW202121690A (zh
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張翼
張懋中
莊絜晰
林雨潔
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國立交通大學
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Priority to TW108142879A priority Critical patent/TWI715311B/zh
Priority to CN201911236326.3A priority patent/CN111029400B/zh
Priority to US17/007,967 priority patent/US11271109B2/en
Priority to DE102020128550.7A priority patent/DE102020128550A1/de
Priority to KR1020200146851A priority patent/KR102521609B1/ko
Priority to JP2020188266A priority patent/JP7019218B2/ja
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Publication of TWI715311B publication Critical patent/TWI715311B/zh
Publication of TW202121690A publication Critical patent/TW202121690A/zh

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Abstract

一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法，乃在金屬氧化物矽半導體場效電晶體結構中，於矽（100）基板上製作百奈米級孔洞，此百奈米級孔洞可隨後將矽基板之（111）晶面暴露，而有利於選擇性區域成長高品質的三五族材料，藉由其寬能隙的特性，三五族材料作為汲極結構可以有效彌補金屬氧化物矽半導體場效電晶體在高頻應用功率功能之不足，也可解決因元件持續微縮所產生之擊穿問題。

Description

具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法
本發明係關於一種金屬氧化物矽半導體場效電晶體，特別是有關於一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法。
三五族化合物半導體，例如氮化鎵（GaN）材料，具備許多優異的物理特性，例如：高擊穿電壓、寬能隙、高電子飄移速度等等，適合應用於高電流、高耐壓、高速度之電子元件。近年來，各國研究團隊利用有機金屬化學氣相沉積（MOCVD）於矽（100）基板上選擇性成長（selective area growth，SAG）奈米等級尺寸之氮化鎵磊晶層，以實現異質整合三五族材料於矽製程中，然而，其多應用於LED相關用途。
金屬氧化物半導體場效電晶體（MOSFET）依摩爾定律微其閘極至10nm以下，從而在數位開關和邏輯功能方面具有卓越的性能。但是，微縮也限制了CMOS器件的運作動態範圍和功率處理能力。例如，深度微縮後的MOSFET具有非常低的汲極擊穿電壓（>2V），嚴重限制其信號擺幅小於1V。因此，蜂窩基站和微波通信不得不使用外部連結之III-V HBT RF功率放大器。然而，當電信（5G / 6G）必須轉向更高的毫米波頻率以獲得更廣的帶寬和更高的數據速率時，這種趨勢必無法繼續。在mm-Wave無線電/雷達波段，外接功率放大器/開關的信號損耗相當嚴重, 無法達成高線性度和高效能的嚴格系統需求，特別是不能滿足蓄電有限之智能手機的通話時間要求。此外，超大規模CMOS VLSI限制了混合信號SoC系統的工作動態範圍，尤其是雷達、成像器和其他探測器/傳感器的分辨率（resolution）。
而已知的金屬氧化物矽半導體場效電晶體大多選擇使用矽鍺（SiGe）作為汲極材料。例如，美國專利第6218711號是選擇性成長SiGe材料凸起於源極/汲極，並且提高兩極之位置以解決短通道效應（short channel effect），不過SiGe材料的擊穿電壓更低，更是無法達成高動態範圍（high dynamic range）之電路需求。
有鑑於此，本發明的主要目的在於提供一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法，利用選擇性成長三五族材料於具有（111）晶面暴露的矽基板，來製作高磊晶品質的三五族汲極結構，藉由其具有寬能隙特性，有效彌補矽金屬氧化物半導體場效電晶體在高頻應用功率功能之不足，同時可改善因為元件持續微縮所產生之擊穿問題。
為了實現上述目的，本發明提出一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其包含一基板，基板是由矽基板、絕緣層和半導體層所構成，其中，矽基板具有（100）晶面之主表面，在主表面上形成有絕緣層，在絕緣層上形成有半導體層，在半導體上設有介電層，在介電層上設有金屬閘極。而金屬閘極之一側下方的半導體層內設有源極，金屬閘極之另一側且穿過半導體層來延伸至矽基板內形成有一百奈米級孔洞，此百奈米級孔洞的壁面是由一側壁和在側壁之下延伸的一傾斜表面所構成，傾斜表面暴露矽基板之（111）晶面。緩衝層形成於百奈米級孔洞之傾斜表面上。將三五族汲極選擇性的形成於百奈米級孔洞內。
另外，本發明也提出一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其步驟是先提供一基板，基板包括底部的矽基板，矽基板具有（100）晶面的主表面，且在主表面設置有絕緣層，於絕緣層上設置有半導體層；形成一假閘極於半導體層上；利用假閘極作為遮罩對於半導體層進行離子摻雜，以形成位於假閘極下方之一通道區域以及分別位於通道區域兩側的二淺摻雜區域，並在二淺摻雜區域分別設置一汲極位置和一源極位置；對於汲極位置進行選擇性蝕刻，以形成百奈米級孔洞，此百奈米級孔洞穿過半導體層而延伸至矽基板內，百奈米級孔洞的壁面是由側壁和在側壁之下延伸經V-grooved程序的傾斜表面所構成，傾斜表面暴露矽基板之（111）晶面；再使用有機金屬化學氣相沉積方式將緩衝層成長於傾斜表面上，再將三五族磊晶層形成於百奈米級孔洞中，同時進行矽摻雜，以形成一三五族汲極；然後，對於源極位置進行重離子摻雜，以形成源極；去除假閘極；在去除假閘極後所露出的半導體層上形成介電層；最後，在介電層上形成金屬閘極。
根據本發明所提供的具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法，利用選擇性磊晶技術，將三五族材料整合到CMOS之汲極區域中，與其他的先進矽電晶體相比，三五族材料作為汲極結構可大幅度增進CMOS之擊穿電壓與電流。而本發明通過選擇性磊晶成長汲極的方法，可以獲得高品質低缺陷之三五族汲極結構於超大型積體電路（VLSI）的系統單晶片（SoC）應用上，並達成前所未有的高動態範圍之功能。
底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
本發明主要提供一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體（Si MOSFET）及其製造方法，以下之實施例則以在絕緣層上矽（Silicon-on-Insulator，SOI）基板上製作氮化鎵汲極為例來進行詳細說明，但本發明並不限於此實施例。請參照第1A圖～第1F圖，為本發明實施例提供的具有氮化鎵汲極之金屬氧化物矽半導體場效電晶體的製造方法中對應各步驟的剖視結構圖。此製造方法包括以下步驟：
如第1A圖所示，首先提供一基板100，本實施例是採用SOI基板，此基板100包括矽基板10、絕緣層20和半導體層30。其中，矽基板10具有（100）晶面的主表面11，絕緣層20位於主表面11上，半導體層30位於絕緣層20上。具體而言，絕緣層20可為氮化矽層、二氧化矽層或由氮化矽層和二氧化矽層所堆疊而成的多層結構，絕緣層20的厚度為100奈米。
如第1B圖所示，形成假閘極(dummy gate)40於半導體層30上，假閘極40較佳是由多晶矽所構成。然後，圖案化假閘極40，再利用假閘極40作為硬遮罩對於半導體層30進行離子摻雜，本實施例中是以磷離子進行N型摻雜，以分別定義出位於假閘極40下方之P型的通道區域31以及分別位於通道區域31兩側的二個N型的淺摻雜區域32、33。再於半導體層30上形成覆蓋於假閘極40上的介電層41。
在此，利用模擬淺汲極(LDD)長度之結果，在前述的一個淺摻雜區域32設置一汲極位置321，另一個淺摻雜區域33設置一源極位置331。
接著，如第1C圖所示，在汲極位置321進行選擇性蝕刻，以形成百奈米級孔洞50。
本實施例之百奈米級孔洞50的形成步驟，請依序參照第2A~2D圖，包括先設計百奈米級孔洞圖案，使用電子束微影技術(electron beam Lithography)將介電層41進行圖案化，以使用此介電層41作為硬遮罩，如第2A圖所示，利用反應離子蝕刻(Reactive-ion etching，RIE)方式於基板100中形成百奈米級孔洞50。
如第2B圖所示，再使用電漿化學氣相沉積(Plasma enhanced chemical vapor deposition，PECVD)方式於百奈米級孔洞50的壁面成長一層預定厚度之氮化層60；具體而言，此氮化層60為氮化矽(SiNx)，氮化層60的厚度為200奈米。此步驟中，百奈米級孔洞50於基板100中的深度約為250奈米；實際應用上，百奈米級孔洞50於基板100中的深度可介於100-500奈米的範圍。
然後，如第2C圖所示，利用感應耦合型電漿(Inductively coupled plasma，ICP)蝕刻方式移除百奈米級孔洞50底壁51之氮化層54，使暴露下方之矽基板10之(100)晶面，並留下百奈米級孔洞50側壁(sidewall)52之氮化層54。
再如第2D圖所示，使用側壁52之氮化層54作為阻擋層，利用氫氧化鉀(KOH)作為蝕刻液，加熱至80℃，時間持續110秒，濕蝕刻由百奈米級孔洞50底壁所暴露的矽基板10之(100)晶面，直至暴露出具有矽基板10之(111)晶面的傾斜表面53。此步驟中，將第2C圖中的百奈米級孔洞50的底壁51往下侵蝕出一V形槽，前述有關百奈米級孔洞50於基板100中的深度需進一步定義為百奈米級孔洞50之側壁52於基板100中的長度，其介於100-500奈米的範圍，並不涵蓋V形槽的部份。
在百奈米級孔洞50製作完成之後，再如第1D圖所示，使用有機金屬化學氣相沉積(MOCVD)方式於百奈米級孔洞50中成長氮化鋁(AlN)緩衝層60，再成長氮化鎵(GaN)磊晶層，同時進行矽摻雜，以形成氮化鎵汲極70；具體而言，矽摻雜的方法是於氮化鎵磊晶層成長時藉由引入以矽烷(Sillane，SiH4)稀釋於氫氣中所形成的摻雜氣體，來增加並控制矽原子於氮化鎵中之摻雜濃度，藉以獲得一理想之氮化鎵汲極70。再藉由蝕刻移除一部分的介電層41，並使餘留下來介電層41環繞於假閘極40的側壁。
之後，如第1E圖所示，再對於源極位置331進行重離子摻雜，以形成重摻雜區域34，從而定義出源極80。本實施例中是摻雜高濃度的N型離子，例如磷離子，迫使於通道區域31中產生電子的流動。
然後，如第1F圖所示，藉由蝕刻製程移除假閘極40，而露出底下的半導體層30，並在去除假閘極40後所露出的半導體層30上形成介電層 90，最後，在介電層90上形成金屬閘極91，即完成具有氮化鎵汲極之金屬氧化物矽半導體場效電晶體的製作。
如圖所示，根據本發明之實施例所揭露之具有氮化鎵汲極之金屬氧化物矽半導體場效電晶體，是由基板100、介電層90、金屬閘極91、源極80、百奈米級孔洞50和氮化鎵汲極70所構成。其中，基板100由底部往頂部依序包括矽基板10、絕緣層20和半導體層30，且矽基板10具有(100)晶面之主表面11。半導體層30上依序設有介電層90和金屬閘極91，源極80位於金屬閘極91一側下方的半導體層30內，氮化鎵汲極70則形成於金屬閘極91另一側的百奈米級孔洞50中。百奈米級孔洞50依序穿過半導體層30和絕緣層20後延伸至矽基板10中，百奈米級孔洞50的壁面是由側壁52和連接於側壁52並由側壁52往下延伸之傾斜表面53所構成；其中，傾斜表面53乃具有矽基板10之(111)晶面。而氮化鋁緩衝層60形成於百奈米孔洞50之傾斜表面53上，氮化鎵汲極70則形成於百奈米級孔洞50內並位於氮化鋁緩衝層60上。
在本發明之實施例中，百奈米級孔洞50的側壁52大略垂直於矽基板10之(100)晶面的主表面11，側壁52底部所連接的傾斜表面53構成一V形槽；就未涵蓋V形槽的情況下，百奈米級孔洞50的側壁52位於基板100中的長度約為250-700奈米的範圍。
本發明之實施例利用選擇性成長高品質之氮化鎵於矽基板上成功製作汲極，並完成此Si-MOSFET元件，即可利用氮化鎵的材料特性，在汲極得到高擊穿電壓。如第5圖所示，此氮化鎵汲極於矽基板表面呈現為大約5.27微米(μm)長和1.20微米寬之長方形圖案；其剖面結構如第6圖所示，氮化鎵汲極於百奈米級孔洞的底部中央為高度晶格缺陷區域，於兩側壁至表面部位則成長為高度結晶區域。另外，雖然上述實施例之汲極結構是利用假 閘極來對SOI基板進行N型摻雜而獲得，但相同的汲極結構也可設計於一般非SOI之矽基板。
進一步說明，本發明之實施例於矽(100)基板上利用V-grooved程序濕蝕刻製造矽(100)基板的(111)晶面，其提供了氮化鋁緩衝層和氮化鎵磊晶層較佳的成核晶面，而單晶之六方晶體氮化鎵(h-GaN)可由(111)晶面上方開始成長，其結晶過程的晶格差排(dislocaiton)將會終結於百奈米級孔洞之側壁，當兩側壁所成長的六方晶體氮化鎵於百奈米級孔洞中間合併時，可獲得高結晶度的立方晶體氮化鎵(c-GaN)，此選擇性成長技術能夠有效的控制及設計氮化鎵磊晶層之尺寸與形狀，而成長時通入適當之矽烷可以調控矽於氮化鎵磊晶層之摻雜濃度，其摻雜濃度可以控制垂直漏電流，而得以獲得理想之寬能隙氮化鎵汲極，並能成功整合於矽金屬氧化物半導體場效應電晶體中來完全取代原來的MOSFET汲極。進一步有關氮化鎵磊晶層之晶格結構分析的詳細內容，請參照中華民國發明專利申請案第108117447號所述的氮化鎵異質整合於矽基板之半導體結構及其製造方法，在此以參照的方式將其引入本文，恕不贅述。
再進一步說明，本發明之實施例乃通過使用異質氮化鎵的汲極來取代傳統Si CMOS中均勻的矽汲極，以解決MOSFET的低汲極擊穿電壓的問題。本發明之實施例先通過V形槽優先蝕刻的技術(V-Grooved preferential etching)去除原來的矽汲極材料，以停留和露出其側壁的(111)表面來成長氮化鎵磊晶層。然後，使用獨特的選擇性側向沉積技術，從側壁上開始成長六邊晶體氮化鎵(h-氮化鎵)到中心和頂部接觸面合併為立方晶體氮化鎵(c-氮化鎵)來重新製成汲極。這種異質材料生長方法可以順利地轉換CMOS柵極至汲極載流子傳輸通道，不僅可以保持器件的高速性能，而且由於氮化 鎵相較於矽具有更寬的能隙(氮化鎵和矽的能隙分別為3.4eV、1.1eV)，而大大的降低其電子碰撞電離係數(<1/106)，並提高其擊穿電壓。
接著，以下模擬分析具有GaN汲極之MOSFET元件的電壓與電場特性，以瞭解其元件的表現。
請參照第3圖，其顯示LD(Lateral diffusion，橫向擴散)-GaN汲極MOSFET的能帶圖，相較於矽(或是矽鍺)汲極的能帶圖，氮化鎵擁有較高的能隙，因此能夠預期其在承受擊穿電壓之表現應該優於傳統之Si或SiGe材料。
再請參照第4圖，其顯示以TCAD模擬具有不同漂移區(Drift Region)長度L的LD-GaN汲極MOSFET的橫向電場。其中，曲線(a)和曲線(b)顯示了LD-GaN汲極MOSFET在不同淺摻雜汲極(LDD)偏置長度時，通道/LDD PN結的橫向電場大小；而曲線(a)和曲線(b)代表將漂移區長度L分別拉長至100nm和40nm，x軸是通道方向(channel direction)，而漂移區長度L是指閘極至汲極之間的距離，並以閘極邊緣為0.00的基準位置(見第1F圖)。如圖所示，峰值(最大)橫向電場為3.6MV/cm，發生在汲極側的閘極邊緣，然而，當LDD偏移長度從0nm增加為10nm時，最大的橫向電場雖不會改變，其電場的大小卻有明顯減小，並且進一步移動到閘極-汲極重疊區域中。
與其他的先進矽電晶體相比，GaN汲極結構解決了因為元件微縮而造成之擊穿(breakdown)問題。現在可以在Si CMOS上實現許多過去只有在III-V技術領域才能完成的應用。然而，在矽基板上成長具有高質量的複合材料是困難的，例如通過鍵合或外延生長。處理CMOS和其他III-V器件在交叉污染和不同的熱循環要求方面也可能存在問題。為了在沒有上述問題的情況下獲得化合物半導體的益處，需要嵌入式III-V/矽奈米電子器件。本 發明通過結合氮化鎵作為汲極結構，可以獲得具有非常高的擊穿能力的RF MOSFET。本發明的主要概念是用寬能隙半導體氮化鎵取代矽(或應變Si)MOSFET汲極區域。
在過去幾年中，利用小面積奈米異質外延(NHE)材料合成，以及長寬比捕獲(ART)原理，已經被證明了選擇性氮化鎵沉積為MOSFET汲極的可行性，並證明利用選擇性沉積的氮化鎵可以有效的減少缺陷，並得到高質量的氮化鎵。這對於器件/電路性能是至關重要的。在此所提出的器件能成為5G應用的下一代高壓/功率RF電晶體最有效的競爭者。
除了寬能隙之材料特性以外，氮化鎵亦有高電子遷移電子遷移率，作為高頻元件之開發與薄膜磊晶成長已有相當充足之研究，而本發明有別於傳統之薄膜磊晶成長，是以選擇性磊晶成長之技術沉積氮化鎵的方式獲得氮化鎵汲極。目前在GaN汲極材料成長方面已成功將GaN異質磊晶成長在SiO2/Si基板之百奈米級孔洞，由TEM結果顯示為高品質低缺陷之GaN磊晶。利用此技術製作之MOSFET可以有效彌補矽MOSFET在高頻應用功率功能之不足，也同時改善MOSFET原本低擊穿電壓的缺點。
當然，本發明應用的範圍也包含將氮化鎵以外的寬能隙三五族材料選擇性成長於矽(100)基板上，且利用選擇性蝕刻方式產生較低的晶格不匹配的矽(111)晶面而得以成長高品質的三五族材料作為汲極，以將三五族汲極成功整合於金屬氧化物矽半導體場效電晶體上。
綜上所述，根據本發明所揭露的具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法，藉由三五族材料的寬能隙特性加上選擇性磊晶技術，來獲得高品質低缺陷之三五族汲極結構，可改善擊穿電壓與垂直漏電流的問題，以期未來整合於Si MOSFET後，解決因元件持續微縮所產生之低元件擊穿電壓問題，並能運用在最先進的矽VLSI平台上，支 持許多高動態範圍的系統單晶片(SoC)之應用，尤其是高線性度、高效率、高頻功率放大器和高精度模擬或類比電路，如5G和RF/microwave/Micro-Wave雷達和無線電高線性/效率之發射器、高分辨率類比/數位轉換器等。
進一步地，本發明更可有效提升臨界電壓值，具高電流及高轉導值，降低元件待機時之功耗，以及提供數位邏輯電路之應用，可以符合未來氮化鎵元件應用之需求。
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
100:基板
10:矽基板
11:主表面
20:絕緣層
30:半導體層
31:通道區域
32:淺摻雜區域
321:汲極位置
33:淺摻雜區域
331:源極位置
34:重摻雜區域
40:假閘極
41:介電層
50:百奈米級孔洞
51:底壁
52:側壁
53:傾斜表面
54:氮化層
60:氮化鋁緩衝層
70:氮化鎵汲極
80:源極
90:介電層
91:金屬閘極
L:漂移區長度
第1A圖～第1F圖為本發明實施例提供的具有氮化鎵汲極之互補式金屬氧化物矽半導體場效電晶體的製造方法中對應各步驟的剖視結構圖。 第2A圖～第2D圖為本發明實施例中百奈米級孔洞的製造方法中對應各步驟的剖視結構圖。 第3圖為一種GaN汲極MOSFET的能帶圖。 第4圖為具有不同漂移區長度的GaN汲極MOSFET的橫向電場。 第5圖為本發明之實施例的GaN汲極結構之掃描電子顯微鏡（SEM）影像。 第6圖為本發明之實施例的GaN汲極結構之穿透式電子顯微鏡（TEM）影像。
100:基板
10:矽基板
11:主表面
20:絕緣層
30:半導體層
31:通道區域
34:重摻雜區域
41:介電層
50:百奈米級孔洞
52:側壁
53:傾斜表面
60:氮化鋁緩衝層
70:氮化鎵汲極
80:源極
90:介電層
91:金屬閘極
L:漂移區長度

Claims (12)

  1. 一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，包含： 一基板，包括一矽基板、一絕緣層和一半導體層，該矽基板具有（100）晶面之一主表面，該絕緣層位於該主表面上，該半導體層位於該絕緣層上； 一介電層，位於該半導體層上； 一金屬閘極，位於該介電層上； 一源極，位於該金屬閘極之一側下方的該半導體層內； 一百奈米級孔洞，位於該金屬閘極之另一側並穿過該半導體層來延伸至該矽基板內，該百奈米級孔洞的壁面是由一側壁和在該側壁之下延伸的一傾斜表面所構成，該傾斜表面暴露該矽基板之（111）晶面，且一緩衝層形成於該傾斜表面上；以及 一三五族汲極，形成於該百奈米級孔洞中。
  2. 如請求項1所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其中該絕緣層為一氮化矽層、一二氧化矽層或由前述兩者堆疊而成的多層結構。
  3. 如請求項1所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其中該絕緣層的厚度為100奈米。
  4. 如請求項1所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其中該百奈米級孔洞之該側壁於該基板中的長度為100-500奈米。
  5. 如請求項1所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其中該側壁係垂直於該（100）晶面之主表面。
  6. 如請求項1所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體，其中該三五族汲極為一氮化鎵汲極，且包含立方晶體氮化鎵。
  7. 一種具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，包含下列步驟： 提供一基板，該基板包括一矽基板、一絕緣層和一半導體層，該矽基板具有（100）晶面之一主表面，該絕緣層位於該主表面上，該半導體層位於該絕緣層上基板； 形成一假閘極（dummy gate）於該半導體層上； 利用該假閘極作為硬遮罩對於該半導體層進行離子摻雜，以形成位於該假閘極下方之一通道區域以及分別位於該通道區域兩側的二淺摻雜區域，分別設置一汲極位置和一源極位置於該些淺摻雜區域； 對於該汲極位置進行選擇性蝕刻，以形成一百奈米級孔洞，該百奈米級孔洞穿過該半導體層而延伸至該矽基板內，該百奈米級孔洞的壁面是由一側壁和在該側壁之下延伸的一傾斜表面所構成，該傾斜表面暴露該矽基板之（111）晶面； 使用有機金屬化學氣相沉積方式先成長一緩衝層於該傾斜表面上，再形成一三五族磊晶層於該百奈米級孔洞中，同時進行矽摻雜，以形成一三五族汲極； 對於該源極位置進行重離子摻雜，以形成一源極； 去除該假閘極，露出該半導體層； 在去除該假閘極後所露出的該半導體層上形成一介電層；以及 在該介電層上形成一金屬閘極。
  8. 如請求項7所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其中該絕緣層為一氮化矽層、一二氧化矽層或由前述兩者堆疊而成的多層結構。
  9. 如請求項7所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其中該絕緣層的厚度為100奈米。
  10. 如請求項7所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其中該百奈米級孔洞之該側壁於該基板中的長度為100-500奈米。
  11. 如請求項7所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其中該側壁係垂直於該（100）晶面之主表面。
  12. 如請求項7所述之具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體的製造方法，其中該三五族汲極為一氮化鎵汲極，且包含立方晶體氮化鎵。
TW108142879A 2019-11-26 2019-11-26 具有寬能隙三五族汲極之金屬氧化物矽半導體場效電晶體及其製造方法 TWI715311B (zh)

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