WO2016013554A1 - 結晶性半導体膜および板状体ならびに半導体装置 - Google Patents
結晶性半導体膜および板状体ならびに半導体装置 Download PDFInfo
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- WO2016013554A1 WO2016013554A1 PCT/JP2015/070752 JP2015070752W WO2016013554A1 WO 2016013554 A1 WO2016013554 A1 WO 2016013554A1 JP 2015070752 W JP2015070752 W JP 2015070752W WO 2016013554 A1 WO2016013554 A1 WO 2016013554A1
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Classifications
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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- C—CHEMISTRY; METALLURGY
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/448—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
- C23C16/4481—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by evaporation using carrier gas in contact with the source material
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02367—Substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H—ELECTRICITY
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Definitions
- the present invention relates to a crystalline semiconductor film and a plate-like body useful for a semiconductor device, and a semiconductor device using the crystalline semiconductor film or the plate-like body.
- a semiconductor device using gallium oxide (Ga 2 O 3 ) having a large band gap has been attracting attention as a next-generation switching element that can achieve high breakdown voltage, low loss, and high heat resistance. Application is expected.
- the gallium oxide can control the band gap by using mixed crystals of indium and aluminum, respectively.
- Patent Document 1 describes a highly crystalline conductive ⁇ -Ga 2 O 3 thin film to which a dopant (tetravalent tin) is added.
- a dopant tetravalent tin
- the thin film described in Patent Document 1 cannot maintain sufficient pressure resistance, and contains a large amount of carbon impurities, and the semiconductor characteristics including conductivity are still not satisfactory. It was still difficult to use in the device.
- Patent Document 2 discloses a Ga 2 O 3 based semiconductor device in which a p-type ⁇ - (Al x ′′ Ga 1-x ′′ ) 2 O 3 single crystal film is formed on an ⁇ -Al 2 O 3 substrate.
- ⁇ -Al 2 O 3 is an insulator and there are problems in the quality of the crystal, so that there are many restrictions on application to the semiconductor element, and MBE
- MBE MBE
- ion implantation and heat treatment at a high temperature are required. Therefore, it is difficult to realize p-type ⁇ -Al 2 O 3 itself.
- the semiconductor element itself was difficult to realize.
- Non-Patent Document 2 describes that an ⁇ -Ga 2 O 3 thin film can be formed on sapphire by MBE.
- the crystal grows up to a film thickness of 100 nm at a temperature of 450 ° C. or lower, it is described that the crystal quality deteriorates when the film thickness is larger than that, and a film having a film thickness of 1 ⁇ m or more cannot be obtained. Therefore, an ⁇ -Ga 2 O 3 thin film having a film thickness of 1 ⁇ m or more and no deterioration in crystal quality has been awaited.
- Patent Document 3 describes a method of producing an oxide crystal thin film by mist CVD using bromide or iodide of gallium or indium.
- Patent Documents 4 to 6 describe a multilayer structure in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are stacked on a base substrate having a corundum crystal structure.
- Patent documents 3 to 6 are all patent publications or patent publications by the applicant of the present application. However, at the time of filing, a crystal thin film having a thickness of 1 ⁇ m or more could not be obtained. Further, none of the films obtained by the methods described in Patent Documents 3 to 6 were actually peelable from the substrate.
- An object of the present invention is to provide a semiconductor film, a plate-like body, and a semiconductor device, which have excellent semiconductor characteristics, particularly leakage current, and are excellent in pressure resistance and heat dissipation.
- the inventors of the present invention have created a crystalline semiconductor film that contains an oxide semiconductor having a corundum structure as a main component and has a thickness of 1 ⁇ m or more. succeeded in. Further, the present inventors have further studied and succeeded in manufacturing a plate-like body containing an oxide semiconductor having a corundum structure as a main component. In addition, the inventors of the present invention manufactured a semiconductor device using the crystalline semiconductor film or the plate-like body, and the obtained semiconductor device has suppressed leakage current and is excellent in pressure resistance and heat dissipation. After obtaining the above findings and obtaining the various findings described above, further studies were made to complete the present invention.
- the crystalline semiconductor film and the plate-like body of the present invention are excellent in semiconductor characteristics, and the semiconductor device of the present invention is suppressed in leakage current and excellent in pressure resistance and heat dissipation.
- FIG. 1 It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the metal semiconductor field effect transistor (MESFET) of this invention. It is a figure which shows typically a suitable example of the high electron mobility transistor (HEMT) of this invention. It is a figure which shows typically a suitable example of the metal oxide film semiconductor field effect transistor (MOSFET) of this invention.
- FIG. 1 shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky
- FIG. 7 is a schematic diagram for explaining a part of the manufacturing process of the metal oxide semiconductor field effect transistor (MOSFET) of FIG. 6. It is a figure which shows typically an example of the metal oxide film semiconductor field effect transistor (MOSFET) of this invention. It is a figure which shows typically a suitable example of the electrostatic induction transistor (SIT) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the high electron mobility transistor (HEMT) of this invention.
- MOSFET metal oxide semiconductor field effect transistor
- MOSFET metal oxide film semiconductor field effect transistor
- JFET junction field effect transistor
- IGBT insulated gate bipolar transistor
- LED light emitting element
- LED light emitting element
- the crystalline semiconductor film of the present invention is a crystalline semiconductor film containing an oxide semiconductor having a corundum structure as a main component, and is not particularly limited as long as the film thickness is 1 ⁇ m or more. Is preferably 2 ⁇ m or more, more preferably 3 ⁇ m or more, and most preferably 5 ⁇ m or more. In the present invention, the film thickness is preferably 7.6 ⁇ m or more. When the film thickness is 7.6 ⁇ m or more, the crystalline semiconductor film can be self-supporting.
- the film thickness is more preferably 10 ⁇ m or more, and a multilayer film (for example, a laminate of an n ⁇ type semiconductor layer and an n + type semiconductor layer) having the same main component with a film thickness of 10 ⁇ m or more. It is most preferable because the semiconductor characteristics are further improved.
- the shape of the crystalline semiconductor film is not particularly limited, and may be a quadrangular shape, a circular shape, or a polygonal shape.
- the surface area of the crystalline semiconductor film is not particularly limited, and in the present invention, it is preferably 3 mm square or more (9 mm 2 or more), more preferably 5 mm square or more (25 mm 2 or more), and a diameter of 50 mm. The above is most preferable. In the present invention, by using the mist CVD method under specific conditions, the crystalline semiconductor film of 3 mm square or more, which could not be achieved conventionally, can be easily obtained.
- the crystalline semiconductor film may be a single crystal film or a polycrystalline film. However, in the present invention, the crystalline semiconductor film may contain a polycrystal. Is preferred.
- the oxide semiconductor is not particularly limited as long as it is an oxide semiconductor having a corundum structure. Examples of the oxide semiconductor include a metal oxide semiconductor containing one or more metals selected from Al, Ga, In, Fe, Cr, V, Ti, Rh, Ni, Co, and the like. .
- the oxide semiconductor preferably contains one or more elements selected from indium, aluminum and gallium as a main component, and contains at least indium and / or gallium as a main component. More preferably, it contains at least gallium as a main component.
- the “main component” means that the oxide semiconductor having the corundum structure is preferably 50% or more, more preferably 70% in terms of atomic ratio with respect to all components of the crystalline semiconductor film. As mentioned above, it means that 90% or more is contained, and it means that it may be 100%.
- a preferable composition in the case where the oxide semiconductor is ⁇ -type In X Al Y Ga Z O 3 is not particularly limited as long as the object of the present invention is not impaired, but gallium in the metal element contained in the crystalline semiconductor film
- the total atomic ratio of indium and aluminum is preferably 0.5 or more, and more preferably 0.8 or more.
- a preferable composition in the case where the oxide semiconductor includes gallium is such that the atomic ratio of gallium in the metal element included in the crystalline semiconductor film is preferably 0.5 or more, and is 0.8 or more. Is more preferable.
- the crystalline semiconductor film may contain a dopant.
- the dopant is not particularly limited as long as the object of the present invention is not impaired.
- Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or p-type dopants.
- the concentration of the dopant may usually be about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm 3 , and the concentration of the dopant is set to a low concentration of about 1 ⁇ 10 17 / cm 3 or less, for example.
- an n-type dopant an n-type semiconductor or the like can be used.
- the dopant can be contained at a high concentration of about 1 ⁇ 10 20 / cm 3 or more, for example, in the case of an n-type dopant, an n + -type semiconductor or the like can be obtained.
- the n-type dopant is preferably germanium, silicon, titanium, zirconium, vanadium or niobium.
- the concentration of zirconium, vanadium or niobium is preferably about 1 ⁇ 10 13 to 5 ⁇ 10 17 / cm 3, and more preferably about 1 ⁇ 10 15 to 1 ⁇ 10 17 / cm 3 .
- the concentration of germanium, silicon, titanium, zirconium, vanadium or niobium in the crystalline semiconductor film is set. It is preferably about 1 ⁇ 10 20 / cm 3 to 1 ⁇ 10 23 / cm 3 , more preferably about 1 ⁇ 10 20 / cm 3 to 1 ⁇ 10 21 / cm 3 .
- a crystalline semiconductor film having superior electrical characteristics than when tin is used as a dopant can do.
- the crystalline semiconductor film may be formed directly on the base substrate or may be formed via another layer.
- a corundum structure crystal thin film having a different composition, a crystal thin film other than the corundum structure, an amorphous thin film, or the like can be given.
- the structure may be a single layer structure or a multi-layer structure. Two or more crystal phases may be mixed in the same layer.
- the crystalline semiconductor film is configured by laminating an insulating thin film and a conductive thin film, for example, but is not limited to this in the present invention.
- the composition of an insulating thin film and an electroconductive thin film may be the same, or may mutually differ.
- the ratio of the thickness of the insulating thin film to the conductive thin film is not particularly limited.
- the ratio of (thickness of the conductive thin film) / (thickness of the insulating thin film) is 0.001 to 100. 0.1 to 5 is more preferable.
- This more preferable ratio is specifically, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 3, 4, 5 and illustrated here It may be within a range between any two of the numerical values.
- the crystalline semiconductor film is formed on the underlying substrate as it is or via another layer by a mist CVD method using a susceptor, an abnormal grain inhibitor, or the like shown in FIG. 19 or FIG. Can be stacked.
- the base substrate is not particularly limited as long as it serves as a support for the crystalline semiconductor film.
- the substrate may be an insulator substrate, a semiconductor substrate, or a conductive substrate, but the base substrate is preferably an insulator substrate, and has a metal film on the surface. It is also preferable that In the present invention, it is also preferable that the base substrate is a substrate containing a crystal having a corundum structure as a main component or a substrate containing a crystal having a ⁇ -gallia structure as a main component.
- the substrate containing a crystal having a corundum structure as a main component is not particularly limited as long as the composition ratio in the substrate includes 50% or more of the crystal having a corundum structure, but in the present invention, 70% or more. It is preferable that it is contained, and more preferably 90% or more.
- the substrate whose main component is a crystal having a corundum structure include a sapphire substrate (eg, c-plane sapphire substrate), an ⁇ -type gallium oxide substrate, and the like.
- the substrate mainly composed of a crystal having a ⁇ -gallia structure as long as the composition ratio in the substrate includes 50% or more of the crystal having a ⁇ -gallia structure.
- a substrate mainly composed of a crystal having a ⁇ -gallia structure for example, a ⁇ -Ga 2 O 3 substrate, or Ga 2 O 3 and Al 2 O 3 and Al 2 O 3 is more than 0 wt% and 60 wt%. % Or less of a mixed crystal substrate.
- examples of other base substrates include substrates having a hexagonal crystal structure (eg, SiC substrate, ZnO substrate, GaN substrate). It is preferable to form the crystalline semiconductor film on the substrate having a hexagonal crystal structure directly or via another layer (eg, buffer layer).
- the thickness of the base substrate is not particularly limited in the present invention, but is preferably 50 to 2000 ⁇ m, more preferably 200 to 800 ⁇ m.
- the metal film may be provided on a part or all of the substrate surface, and a mesh-like or dot-like metal film is provided. May be.
- the thickness of the metal film is not particularly limited, but is preferably 10 to 1000 nm, more preferably 10 to 500 nm.
- the constituent material of the metal film include platinum (Pt), gold (Au), palladium (Pd), silver (Ag), chromium (Cr), copper (Cu), iron (Fe), and tungsten (W).
- the metal is preferably uniaxially oriented.
- the uniaxially oriented metal may be any metal as long as it has a single crystal orientation in a certain direction such as the film thickness direction and the film in-plane direction, or the film thickness direction. Including.
- the film is preferably uniaxially oriented in the film thickness direction. As for the orientation, it can be confirmed by X-ray diffraction method whether or not the orientation is uniaxial.
- a peak derived from a crystal plane that is uniaxially oriented in the same crystal powder in which the integral intensity ratio between a peak derived from a uniaxially oriented crystal plane and a peak derived from another crystal plane is randomly aligned If the ratio is larger (preferably more than double, more preferably more than an order of magnitude) compared to the integrated intensity ratio between the peak and the peak derived from other crystal planes, it should be determined as being uniaxially oriented. Can do.
- the base substrate includes a sapphire substrate (eg, c-plane sapphire substrate), an ⁇ -type gallium oxide substrate, a ⁇ -Ga 2 O 3 substrate or Ga 2 O 3 and Al 2 O 3, and Al 2 A mixed crystal substrate in which O 3 is more than 0 wt% and not more than 60 wt% or these substrates on which a metal film is formed on the surface is preferable.
- a sapphire substrate eg, c-plane sapphire substrate
- an ⁇ -type gallium oxide substrate e.g, a ⁇ -Ga 2 O 3 substrate or Ga 2 O 3 and Al 2 O 3, and Al 2
- Al 2 A mixed crystal substrate in which O 3 is more than 0 wt% and not more than 60 wt% or these substrates on which a metal film is formed on the surface is preferable.
- the mist CVD method includes, for example, a step (1) of generating a mist by atomizing a raw material by an ultrasonic vibrator, a step (2) of supplying a carrier gas, and the mist held by a susceptor by a carrier gas.
- a film forming method including the step (3) of forming a film by transporting it to the underlying substrate.
- examples of the mist method include a mist / epitaxy method and a mist CVD method.
- the step (1) is not particularly limited as long as the raw material is atomized to generate mist.
- a mist generator that atomizes the raw material to generate mist can be used.
- the mist generator is not particularly limited as long as it can atomize the raw material and generate mist, and may be a known one, but in the present invention, the raw material is atomized by ultrasonic to generate mist. It is preferable to do so.
- the raw materials will be described later.
- the step (2) is not particularly limited as long as a carrier gas is supplied.
- the carrier gas is not particularly limited as long as it is in a gaseous state capable of transporting mist generated by atomizing the raw material onto the substrate.
- oxygen gas, nitrogen gas, argon gas, forming gas, etc. are mentioned.
- the step (3) is not particularly limited as long as the mist can be transported to the base substrate held on the susceptor by a carrier gas and deposited.
- a tubular furnace that can transport mist to the substrate by a carrier gas and form a film in a supply pipe can be suitably used.
- the film when the film is formed in the supply pipe in the step (3), it is preferable to form the crystalline semiconductor film by using, for example, the susceptor shown in FIG. 19 or 20 as the susceptor.
- FIG. 19 shows one mode of the susceptor.
- a susceptor 51 shown in FIG. 19 includes a mist acceleration unit 52, a substrate holding unit 53, and a support unit 54.
- the support portion 54 has a rod shape, and is configured to change the angle in the middle so that the contact angle of the support portion 54 with the supply pipe 55 is about 90 °. With such a configuration, the stability of the susceptor 51 is improved, but in the present invention, the shape of the support portion 54 is not particularly limited, and various shapes can be used as appropriate.
- FIG. 19A shows a cross section in the supply pipe from the upstream side of the mist to the downstream side to the substrate, and the outer peripheral shape of the substrate side surface of the supply pipe is substantially semicircular, It can be seen that the shapes are substantially the same along the inner circumference of the supply pipe.
- FIG. 19B shows a cross section of the supply pipe, the substrate, and the susceptor when the upstream of the mist is on the left and the downstream is on the right.
- the susceptor 51 is provided with an inclined mist accelerating portion 52 so that the settled mist can be accelerated and conveyed to the substrate.
- FIG. 20 shows the region of the susceptor and the substrate shown in FIG. 19 as the substrate / susceptor region 61 and the region where unreacted mist is discharged as the discharge region 62 in the supply pipe 55.
- the relationship between the total area and the area of the discharge area can be understood.
- the susceptor region and the The total area with the substrate is preferably larger than the area of the discharge region.
- a doping process can be performed using a dopant when forming the crystalline semiconductor film.
- the doping treatment is usually performed with the raw material including an abnormal grain inhibitor.
- a crystalline semiconductor film having excellent surface smoothness can be obtained by performing a doping treatment including an abnormal grain inhibitor in the raw material.
- the doping amount is not particularly limited as long as it does not hinder the object of the present invention, but is preferably 0.01 to 10%, more preferably 0.1 to 5% in terms of molar ratio in the raw material.
- the abnormal grain inhibitor refers to an agent having an effect of suppressing generation of particles by-produced in the film formation process, and particularly if the surface roughness (Ra) of the crystalline semiconductor film can be set to 0.1 ⁇ m or less, for example.
- it is preferable that it is an abnormal grain inhibitor composed of at least one selected from Br, I, F and Cl. Introducing Br or I into the film as an abnormal grain inhibitor for stable film formation can suppress the deterioration of the surface roughness due to abnormal grain growth.
- the amount of the abnormal grain inhibitor added is not particularly limited as long as abnormal grains can be suppressed.
- the volume ratio in the raw material solution is preferably 50% or less, more preferably 30% or less, and more preferably 1 to 30%. Most preferably within the range.
- the abnormal grain inhibitor in such a preferable range, it can function as an abnormal grain inhibitor, and thus the growth of abnormal grains in the crystalline semiconductor film can be suppressed and the surface can be smoothed.
- the method for forming the crystalline semiconductor film is not particularly limited as long as the object of the present invention is not hindered.
- a raw material obtained by combining a gallium compound and, if desired, an indium compound or an aluminum compound according to the composition of the crystalline semiconductor film is used. It can be formed by reacting. Accordingly, the crystalline semiconductor film can be grown on the base substrate from the base substrate side.
- the gallium compound may be a gallium compound that is changed to a gallium compound immediately before film formation using gallium metal as a starting material.
- gallium compound examples include organometallic complexes of gallium (e.g., acetylacetonate complex) and halides (e.g., fluoride, chloride, bromide, iodide, etc.).
- organometallic complexes of gallium e.g., acetylacetonate complex
- halides e.g., fluoride, chloride, bromide, iodide, etc.
- a halide eg, fluoride, chloride, bromide or iodide.
- the crystalline semiconductor film can be made substantially free of carbon by forming a film by mist CVD using a halide as a raw material compound.
- the raw material fine particles generated from the raw material solution in which the raw material compound is dissolved are supplied to the film formation chamber, and the raw material compound is reacted in the film formation chamber using the susceptor. Can be formed.
- the solvent of the raw material solution is not particularly limited, but is preferably water, hydrogen peroxide solution or an organic solvent.
- the above raw material compound is usually reacted in the presence of a dopant raw material.
- the dopant raw material is preferably included in the raw material solution and finely divided together with the raw material compound or separately.
- the crystalline semiconductor film contains less carbon than the dopant, and preferably, the crystalline semiconductor film can be substantially free of carbon.
- the crystalline semiconductor film of the present invention preferably contains halogen (preferably Br) because a favorable semiconductor structure is formed.
- halogen preferably Br
- the dopant raw material include tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, which are simple metals or compounds (eg, halides, oxides, etc.).
- the film thickness can be set to 1 ⁇ m or more by appropriately adjusting the film formation time.
- annealing may be performed after film formation.
- the temperature of annealing treatment is not specifically limited, 600 degreeC or less is preferable and 550 degreeC or less is more preferable.
- the carrier concentration of the crystalline semiconductor film can be adjusted more suitably.
- the annealing treatment time is not particularly limited as long as the object of the present invention is not impaired, but is preferably 10 seconds to 10 hours, more preferably 10 seconds to 1 hour.
- the base substrate can be peeled from the crystalline semiconductor film.
- the peeling means is not particularly limited as long as the object of the present invention is not impaired, and may be a known means. Examples of the peeling means include a means for peeling by applying a mechanical impact, a means for peeling by applying heat and applying thermal stress, a means for peeling by applying vibration such as ultrasonic waves, a means for peeling by etching, etc. Is mentioned.
- the peeling the crystalline semiconductor film can be obtained as a free-standing film. Note that in the case where the base substrate is a substrate on which a metal film is formed, only the substrate portion may be peeled off, or the metal film may remain on the surface of the semiconductor layer. By leaving the metal film on the surface of the semiconductor layer, the electrode formation on the semiconductor surface can be made easy and good.
- the film formation may be repeated, and by repeatedly performing the film formation, the film thickness can be increased, and a plate-like body containing an oxide semiconductor having a corundum structure as a main component can also be obtained.
- a crystalline semiconductor film may be formed again on the self-supporting film.
- a plate-like body having a thickness of 7.6 ⁇ m or more, preferably 10 ⁇ m or more, more preferably 15 ⁇ m or more, and most preferably 50 ⁇ m or more can be obtained.
- the plate-like body can be used not only as a semiconductor layer but also as a substrate.
- the crystalline semiconductor film or the plate-like body has a semiconductor structure useful for a semiconductor device.
- the crystalline semiconductor film or the plate-like body may be processed as it is or as desired. It can be used for a semiconductor device as a semiconductor structure after being processed.
- the semiconductor structure of the present invention may be used in the semiconductor device as it is, or another layer (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer). , Buffer layer or other intermediate layer, etc.) may be formed.
- the semiconductor structure of the present invention is useful for various semiconductor devices, and particularly useful for power devices.
- the semiconductor device is classified into a horizontal element in which electrodes are formed on one side of a semiconductor layer (horizontal device) and a vertical element (vertical device) having electrodes on both sides of the semiconductor layer.
- the semiconductor structure can be suitably used for both a horizontal device and a vertical device. Among them, it is preferable to use the semiconductor structure for a vertical device.
- the semiconductor device examples include a Schottky barrier diode (SBD), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), and an electrostatic induction transistor ( SIT), junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), or light emitting diode.
- the semiconductor device is preferably an SBD, MOSFET, SIT, JFET or IGBT, and more preferably an SBD, MOSFET or SIT.
- the semiconductor device may not include a p-type semiconductor layer.
- n-type semiconductor layer such as an n + type semiconductor or an n ⁇ type semiconductor
- n + type semiconductor or an n ⁇ type semiconductor such as an n + type semiconductor or an n ⁇ type semiconductor
- other layers for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers
- buffer layer buffer layer and the like may be omitted as appropriate.
- FIG. 1 shows an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 1 includes an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, and an ohmic electrode 105b.
- the material of the Schottky electrode and the ohmic electrode may be a known electrode material.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxidation
- a metal oxide conductive film such as zinc indium (IZO), an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof.
- the formation of the Schottky electrode and the ohmic electrode can be performed by a known means such as a vacuum deposition method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are stacked, and patterning using a photolithography technique is performed on the layer made of Mo and the layer made of Al. Can be done.
- the SBD using the semiconductor structure is excellent for high withstand voltage and large current, has a high switching speed, and is excellent in withstand voltage and reliability.
- FIG. 2 shows an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 2 further includes an insulator layer 104 in addition to the configuration of the SBD of FIG. More specifically, an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, an ohmic electrode 105b, and an insulator layer 104 are provided.
- Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2, and Si 3 N 4. However, in the present invention, it preferably has a corundum structure. By using an insulator having a corundum structure for the insulator layer, a function of semiconductor characteristics at the interface can be satisfactorily exhibited.
- the insulator layer 104 is provided between the n ⁇ type semiconductor layer 101 and the Schottky electrode 105a.
- the insulator layer can be formed by known means such as sputtering, vacuum deposition, or CVD.
- the formation and material of the Schottky electrode and the ohmic electrode are the same as those in the case of the SBD in FIG. 1.
- a sputtering method a vacuum evaporation method, a pressure bonding method, a CVD method
- Metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag Or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), metal oxide conductive films such as zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or An electrode made of a mixture of these can be formed.
- the SBD of FIG. 3 is an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 3 differs greatly from the configuration of the SBD of FIGS. 1 and 2 in that it has a trench structure and includes a semi-insulator layer 103.
- the SBD of FIG. 3 includes an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, an ohmic electrode 105b, and a semi-insulator layer 103, and greatly reduces leakage current while maintaining withstand voltage. The on-resistance can be greatly reduced.
- the semi-insulator layer 103 only needs to be formed of a semi-insulator.
- the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), and cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- FIG. 4 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention.
- the MESFET in FIG. 4 includes an n ⁇ type semiconductor layer 111a, an n + type semiconductor layer 111b, a buffer layer (buffer layer) 118, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.
- the material of the gate electrode, the drain electrode and the source electrode may be a known electrode material.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Metals such as Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) And metal oxide conductive films such as zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
- the gate electrode, the drain electrode, and the source electrode can be formed by a known means such as a vacuum deposition method or a sputtering method.
- the semi-insulator layer 114 may be any semi-insulator, and examples of the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- FIG. 5 shows an example of a photoelectron mobility transistor (HEMT) according to the present invention.
- the HEMT in FIG. 5 includes an n-type semiconductor layer 121a having a wide band gap, an n-type semiconductor layer 121b having a narrow band gap, an n + type semiconductor layer 121c, a semi-insulator layer 124, a buffer layer 128, a gate electrode 125a, a source electrode 125b, A drain electrode 125c is provided.
- the material of the gate electrode, the drain electrode and the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- the gate electrode, the drain electrode, and the source electrode can be formed by a known means such as a vacuum deposition method or a sputtering method.
- the n-type semiconductor layer under the gate electrode is composed of at least a wide band gap layer 121a and a narrow layer 121b, and the semi-insulator layer 124 only needs to be composed of a semi-insulator.
- the semi-insulator include those containing a semi-insulator dopant such as ruthenium (Ru) and iron (Fe) and those not subjected to doping treatment.
- Ru ruthenium
- Fe iron
- MOSFET Metal Organic Semiconductor
- FIG. 6 An example in which the semiconductor device of the present invention is a MOSFET is shown in FIG.
- the MOSFET in FIG. 6 is a trench type MOSFET and includes an n ⁇ type semiconductor layer 131a, n + type semiconductor layers 131b and 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c.
- an n + type semiconductor layer 131c is formed on the n ⁇ type semiconductor layer 131a, and a source electrode 135b is formed on the n + type semiconductor layer 131c.
- a plurality of trenches are formed in the n ⁇ type semiconductor layer 131a and the n + type semiconductor layer 131c so as to penetrate the n + semiconductor layer 131c and reach the middle of the n ⁇ type semiconductor layer 131a. ing.
- a gate electrode 135a is embedded through a gate insulating film 134 having a thickness of 10 nm to 1 ⁇ m.
- the n ⁇ type is applied.
- a channel layer is formed on the side surface of the semiconductor layer 131a, and electrons are injected into the n ⁇ type semiconductor layer 131a and turned on.
- the voltage of the gate electrode is set to 0 V, the channel layer cannot be formed, and the n ⁇ type semiconductor layer 131a is filled with the depletion layer, and the turn-off is performed.
- FIG. 7 shows a part of the manufacturing process of the MOSFET of FIG.
- an etching mask is provided in predetermined regions of the n ⁇ type semiconductor layer 131a and the n + type semiconductor layer 131c, and the reactive ions are further formed using the etching mask as a mask.
- a trench groove having a depth reaching from the surface of the n + type semiconductor layer 131c to the middle of the n ⁇ type semiconductor layer 131a is formed by performing anisotropic etching by an etching method or the like. .
- a gate having a thickness of, for example, 50 nm to 1 ⁇ m is formed on the side and bottom surfaces of the trench groove by using known means such as a thermal oxidation method, a vacuum deposition method, a sputtering method, and a CVD method.
- a gate electrode material 135a such as polysilicon is formed in the trench groove to have a thickness equal to or less than the thickness of the n ⁇ type semiconductor layer by using a CVD method, a vacuum deposition method, a sputtering method, or the like.
- a source electrode 135b is formed on the n + type semiconductor layer 131c, and a drain electrode 135c is formed on the n + type semiconductor layer 131b.
- a power MOSFET can be manufactured.
- the electrode material of the source electrode and the drain electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti.
- tin oxide zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- IZO zinc indium oxide
- organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- FIG. 6 shows an example of a trench type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET forms.
- the trench resistance in FIG. 6 may be dug down to a depth reaching the bottom surface of the n ⁇ type semiconductor layer 131a to reduce the series resistance.
- An example of a lateral MOSFET is shown in FIG.
- n ⁇ type semiconductor layer 131a includes an n ⁇ type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, a drain electrode 135c, and a buffer layer. 138 and a semi-insulator layer 139. As shown in FIG. 8, by burying the n + type semiconductor layer in the n ⁇ type semiconductor layer, it is possible to flow a current better than other lateral MOSFETs.
- FIG. 9 shows an example where the semiconductor device of the present invention is SIT.
- the SIT in FIG. 9 includes an n ⁇ type semiconductor layer 141a, n + type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
- an n + type semiconductor layer 141c is formed on the n ⁇ type semiconductor layer 141a, and a source electrode 145b is formed on the n + type semiconductor layer 141c.
- a plurality of trench grooves are formed in the n ⁇ type semiconductor layer 141a so as to penetrate the n + semiconductor layer 141c and reach a depth halfway through the n ⁇ semiconductor layer 141a.
- a gate electrode 145a is formed on the n ⁇ type semiconductor layer in the trench. 9, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, the n ⁇ type is applied.
- a channel layer is formed in the semiconductor layer 141a, and electrons are injected into the n ⁇ type semiconductor layer 141a and turned on. In the off state, when the voltage of the gate electrode is set to 0V, the channel layer is not formed, and the n ⁇ type semiconductor layer 141a is filled with the depletion layer, and the turn-off is performed.
- a well-known means can be used for manufacture of SIT shown by FIG.
- an etching mask is provided in predetermined regions of the n ⁇ type semiconductor layer 141a and the n + type semiconductor layer 141c in the same manner as the MOSFET manufacturing process shown in FIG.
- anisotropic etching is performed by, for example, reactive ion etching or the like, and a trench groove having a depth reaching from the surface of the n + type semiconductor layer 141c to the middle of the n ⁇ type semiconductor layer 141a.
- a gate electrode material such as polysilicon, for example, is formed in the trench groove below the thickness of the n ⁇ type semiconductor layer by CVD, vacuum deposition, sputtering, or the like. Then, by using a known means such as a vacuum deposition method, a sputtering method, a CVD method or the like, a source electrode 145b is formed on the n + type semiconductor layer 141c, and a drain electrode 145c is formed on the n + type semiconductor layer 141b, respectively.
- the SIT shown in FIG. 9 can be manufactured.
- the electrode material of the source electrode and the drain electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ),
- a p-type semiconductor is not used.
- the present invention is not limited to this, and a p-type semiconductor may be used. Examples using p-type semiconductors are shown in FIGS. These semiconductor devices can be manufactured in the same manner as in the above example.
- the p-type semiconductor is the same material as the n-type semiconductor and may include a p-type dopant or may be a different p-type semiconductor.
- FIG. 10 shows a suitable Schottky barrier diode (SBD) including an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a p type semiconductor layer 102, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.
- SBD Schottky barrier diode
- FIG. 11 shows a preferred example of a trench Schottky barrier diode (SBD) including an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a p type semiconductor layer 102, a Schottky electrode 105a, and an ohmic electrode 105b. Show. According to the trench type SBD, the leakage current can be greatly reduced while maintaining the withstand voltage, and the on-resistance can be significantly reduced.
- SBD trench Schottky barrier diode
- HEMT high electron mobility transistor
- FIG. 13 shows an n ⁇ type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a p type semiconductor layer 132, a p + type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a,
- MOSFET metal oxide semiconductor field effect transistor
- the p + type semiconductor layer 132a may be a p type semiconductor layer or the same as the p type semiconductor layer 132.
- FIG. 14 includes an n ⁇ type semiconductor layer 141a, a first n + type semiconductor layer 141b, a second n + type semiconductor layer 141c, a p type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
- JFET junction field effect transistor
- FIG. 15 shows an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n + -type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.
- IGBT gate type bipolar transistor
- the semiconductor light emitting element of FIG. 16 includes an n-type semiconductor layer 161 on the second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161.
- a p-type semiconductor layer 162 is stacked on the light emitting layer 163.
- a light-transmitting electrode 167 that transmits light generated by the light-emitting layer 163 is provided over the p-type semiconductor layer 162, and a first electrode 165 a is stacked over the light-transmitting electrode 167.
- 16 may be covered with a protective layer except for the electrode portion.
- an oxide conductive material containing indium (In) or titanium (Ti) can be given. More specifically, for example, In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2, a mixed crystal of two or more thereof, or a material doped with these may be used.
- a translucent electrode can be formed by providing these materials by known means such as sputtering. Moreover, after forming the translucent electrode, thermal annealing for the purpose of making the translucent electrode transparent may be performed.
- the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and a current is passed through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 through both of them.
- the light emitting layer 163 emits light.
- Examples of the material of the first electrode 165a and the second electrode 165b include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Metals such as Hf, W, Ir, Zn, In, Pd, Nd, or Ag or alloys thereof, metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO) Examples thereof include a conductive film, an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof.
- the electrode formation method is not particularly limited, and is a wet method such as a printing method, a spray method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, a CVD method or a plasma CVD method. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods such as the above.
- FIG. 17 Another mode of the light-emitting element is shown in FIG.
- an n-type semiconductor layer 161 is stacked on a substrate 169, and the n-type semiconductor exposed by cutting out part of the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161.
- a second electrode 165b is stacked on a portion of the layer 161 on the exposed surface of the semiconductor layer.
- the mist CVD apparatus 19 used in this example will be described with reference to FIG.
- the mist CVD apparatus 19 includes a susceptor 21 on which the substrate 20 is placed, a carrier gas supply means 22 for supplying a carrier gas, and a flow rate adjusting valve 23 for adjusting the flow rate of the carrier gas sent from the carrier gas supply means 22.
- a mist generating source 24 for storing the raw material solution 24a, a container 25 for containing water 25a, an ultrasonic transducer 26 attached to the bottom surface of the container 25, a supply pipe 27 made of a quartz tube having an inner diameter of 40 mm,
- a heater 28 is provided around the supply pipe 27.
- the susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal plane. Both the supply pipe 27 and the susceptor 21 are made of quartz, so that impurities derived from the apparatus are prevented from being mixed into the film formed on the substrate 20.
- a susceptor 51 shown in FIG. 19 was used as the susceptor 21. Note that the inclination angle of the susceptor is 45 °, and the total area of the substrate and the susceptor in the supply pipe is set so that the susceptor region gradually increases and the discharge region gradually decreases as shown in FIG. As shown in FIG. 20, the susceptor region was configured to be larger than the discharge region.
- a c-plane sapphire substrate having a side of 10 mm and a thickness of 600 ⁇ m is placed on the susceptor 21 as the substrate 20, and the heater 28 is operated to raise the temperature in the supply pipe 27 to 500 ° C. The temperature was raised.
- the flow rate adjusting valve 23 is opened, the carrier gas is supplied from the carrier gas supply means 22 into the supply pipe 27, the atmosphere of the supply pipe 27 is sufficiently replaced with the carrier gas, and then the flow rate of the carrier gas is 5 L / min. Adjusted. Oxygen gas was used as the carrier gas.
- the ultrasonic vibrator 26 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 24a through the water 25a, whereby the raw material solution 24a was atomized to generate raw material fine particles.
- the raw material fine particles were introduced into the supply pipe 27 by the carrier gas, reacted in the supply pipe 27, and formed a film on the substrate 20 by the CVD reaction on the film formation surface of the substrate 20.
- the phase of the obtained film was identified. Identification was performed by performing a 2 ⁇ / ⁇ scan at an angle of 15 to 95 degrees using an XRD diffractometer. The measurement was performed using CuK ⁇ rays. As a result, the obtained film was ⁇ -Ga 2 O 3 .
- the obtained crystalline semiconductor film had a thickness of 3.5 ⁇ m.
- Hall effect measurement was performed by the van der pauw method.
- the frequency of the applied magnetic field was 50 mHz at room temperature.
- the carrier density was 4.33 ⁇ 10 18 (1 / cm 2 ), and the mobility was 19 (cm 2 / V ⁇ s).
- Example 2 The atomic ratio of germanium to gallium bromide and germanium oxide is 1E-7, 1E-6, 8E-5, 4E-4, 2E-3, 1E-2, 2E-1, and 8E-1, respectively.
- a raw material solution was prepared. At this time, 10% by volume of the 48% hydrobromic acid solution was contained.
- Film formation was performed under the same film formation conditions as in Example 1, and quantitative analysis of the impurity concentration was performed using SIMS, with the incident ion species being oxygen, an output of 3 kV, and 200 nA. The result is shown in FIG. As shown in FIG. 21, the dopant content in the liquid and the doping amount in the crystal film have a correlation, and the doping concentration in the formed film can be easily controlled by adjusting the dopant content in the liquid. I found out that I can do it.
- n + semiconductor layer was doped with germanium in the same manner as in condition 1 except that the concentration of germanium oxide was changed to 1.0 ⁇ 10 ⁇ 3 mol / L instead of 5.0 ⁇ 10 ⁇ 3 mol / L.
- An ⁇ -Ga 2 O 3 film was formed on a c-plane sapphire substrate, and then an undoped ⁇ -Ga 2 O 3 film was formed on the film as an n-semiconductor layer.
- the n-semiconductor layer was formed by depositing in the same manner as described above except that nothing was doped.
- the film thickness of the obtained crystalline semiconductor film was 7.6 ⁇ m, and the film formation time was 180 minutes. Then, as shown in FIG.
- sputtering is performed to form an ohmic electrode 105b made of Ti on the n + semiconductor layer 101b and a shot made of Pt on the n ⁇ semiconductor layer 101a.
- Each of the key electrodes 105a was provided to produce an SBD.
- the obtained SBD was subjected to SIMS analysis (Cs 3 kV 200 nA Ap16% Raster400). The results are shown in FIG.
- germanium is not included until about 1500 seconds in the sputtering time on the horizontal axis, and germanium is uniformly included from after about 1500 seconds to about 4000 seconds. It can be seen that the n + type semiconductor layer and the n ⁇ type semiconductor layer are well formed.
- Example 4 The aqueous solution was adjusted so that gallium bromide and tetraethyl orthosilicate were each in a mass ratio of 100: 1. At this time, 10% by volume of the 48% hydrobromic acid solution was contained. The concentration of silicon bromide was 1.0 ⁇ 10 ⁇ 3 mol / L. Film formation was performed for 90 minutes under conditions of a film formation temperature of 500 ° C., a carrier gas of nitrogen, and a flow rate of 5 L / min. The other film formation conditions were the same as in Example 1. The obtained film was subjected to 2 ⁇ / ⁇ scanning at an angle of 15 ° to 95 ° using an XRD diffractometer to identify phases. For the measurement, CuK ⁇ rays were used.
- the obtained film was ⁇ -Ga 2 O 3 .
- the film thickness was 2.5 ⁇ m.
- SIMS analysis Cs 3kV 200nA Ap16% Raster400 was performed about the obtained film
- Example 5 A crystalline semiconductor film was formed in the same manner as in Example 3. After film formation, the crystalline semiconductor film was peeled from the substrate by ultrasonic vibration. The obtained film was subjected to 2 ⁇ / ⁇ scanning at an angle of 15 ° to 95 ° using an XRD diffractometer to identify phases. For the measurement, CuK ⁇ rays were used. As a result, the obtained film was ⁇ -Ga 2 O 3 . The film thickness was 7.6 ⁇ m and the film formation time was 180 minutes. The obtained self-supporting film was structurally evaluated using an X-ray diffractometer. As an X-ray diffraction result, an X-ray diffraction image is shown in FIG. As is clear from FIG. 25, it can be seen that the substrate has no diffraction spots and is a self-supporting film.
- Example 6 As shown in FIG. 26, an SBD was manufactured using tungsten as the Schottky electrode 175a and indium as the ohmic electrode 175b on the self-supporting film 171 obtained in Example 5. The obtained SBD was evaluated for current-voltage characteristics. The results are shown in FIG.
- Example 7 In the same manner as in Example 1, a crystalline semiconductor film was formed for a long time. The obtained film was subjected to 2 ⁇ / ⁇ scanning at an angle of 15 ° to 95 ° using an XRD diffractometer to identify phases. For the measurement, CuK ⁇ rays were used. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, the film thickness is 50 ⁇ m, and when the film thickness is 50 ⁇ m, it is no longer a film but a plate shape.
- Example 8> A crystalline semiconductor film was formed in the same manner as in Example 1. The obtained film was subjected to 2 ⁇ / ⁇ scanning at an angle of 15 ° to 95 ° using an XRD diffractometer to identify phases. For the measurement, CuK ⁇ rays were used. As a result, the obtained film was ⁇ -Ga 2 O 3 . The film thickness was 1.9 ⁇ m. Using the obtained film as it was, a MESFET was fabricated as shown in FIG. The MESFET of FIG. 28 includes a gate electrode 185a, a source electrode 185b, a drain electrode 185c, an n-type semiconductor layer 181 and a substrate 189.
- the n-type semiconductor layer 181 is ⁇ -Ga 2 O 3
- the gate electrode 185a is made of platinum (Pt)
- the source electrode 185b and the drain electrode 185c are each made of a titanium (Ti) gold (Au) alloy.
- FIG. 29 shows the DC characteristics of the manufactured MESFET. As is clear from FIG. 29, there was almost no leakage current, and in particular, a result of about 0.5 nA was obtained at a gate voltage of ⁇ 25V. Further, since led to 519 ⁇ A at a gate voltage 1V, was a relatively high value of the on-off ratio is also 10 6.
- the mist CVD apparatus 1 used in this example will be described with reference to FIG.
- the mist CVD apparatus 1 includes a carrier gas source 2a for supplying a carrier gas, a flow rate adjusting valve 3a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 2a, and a carrier gas for supplying a carrier gas (dilution).
- An installed hot plate 8 and an exhaust port 11 for discharging mist, droplets and exhaust gas after thermal reaction are provided.
- a substrate 10 is installed on the hot plate 8.
- the ultrasonic vibrator 6 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 4a through the water 5a, whereby the raw material solution 4a was atomized to generate the mist 4b.
- the mist 4b is introduced into the film forming chamber 7 by the carrier gas through the supply pipe 9, and the mist thermally reacts in the film forming chamber 7 at 550 ° C. under atmospheric pressure.
- An n + layer was formed on top.
- the second layer except that germanium oxide is not used, the same raw material solution as the first layer is used, and the n ⁇ layer is formed as the second layer on the n + layer under the same conditions as the first layer. Formed.
- the film formation time was 4 hours 30 minutes.
- the second layer was regrown under the same conditions as described above using the mist CVD apparatus of FIG.
- the film formation time was 120 minutes.
- the film thickness of the crystalline semiconductor film was 11.9 ⁇ m in total, of which the film thickness of the n + layer was 3.8 ⁇ m and the film thickness of the n ⁇ layer was 8.1 ⁇ m.
- the phases of the obtained film were identified using an XRD diffractometer, all of the obtained films were ⁇ -Ga 2 O 3 .
- Electrode formation After the sapphire substrate was peeled from the ⁇ -Ga 2 O 3 film, gold was formed on the n ⁇ layer as a Schottky electrode, and Ti / Au was formed on the n + layer as an ohmic electrode by vapor deposition. Produced.
- the ultrasonic vibrator 6 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 4a through the water 5a, whereby the raw material solution 4a was atomized to generate the mist 4b. .
- the mist 4b is introduced into the film forming chamber 7 by the carrier gas through the supply pipe 9, and the mist thermally reacts in the film forming chamber 7 at 550 ° C. under atmospheric pressure. A buffer layer was formed thereon.
- the film formation time was 30 minutes.
- the ultrasonic vibrator 6 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 4a through the water 5a, whereby the raw material solution 4a was atomized to generate the mist 4b.
- the mist 4b is introduced into the film forming chamber 7 by the carrier gas through the supply pipe 9, and the mist thermally reacts in the film forming chamber 7 at 500 ° C. under atmospheric pressure. A buffer layer was formed thereon.
- the film formation time was 300 minutes.
- the obtained release film had a large area of 5 mm square or more. Further, as is clear from FIG. 35, a 1 mm square high-quality ⁇ -Ga 2 O 3 film can be cut out.
- the crystalline semiconductor film and plate-like body of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts / electric equipment parts, optical / electrophotographic related apparatuses, industrial members, etc. Since it has excellent characteristics, it is particularly useful for semiconductor devices.
- semiconductors for example, compound semiconductor electronic devices
- electronic parts / electric equipment parts for example, electronic parts / electric equipment parts
- optical / electrophotographic related apparatuses for example, optical / electrophotographic related apparatuses, industrial members, etc. Since it has excellent characteristics, it is particularly useful for semiconductor devices.
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Abstract
Description
そのため、膜厚が1μm以上であり、結晶の品質も劣化していないα-Ga2O3薄膜が待ち望まれていた。
特許文献4~6には、コランダム型結晶構造を有する下地基板上に、コランダム型結晶構造を有する半導体層と、コランダム型結晶構造を有する絶縁膜とが積層された多層構造体が記載されている。
なお、特許文献3~6はいずれも本出願人による特許または特許出願に関する公報であるが、出願時には、膜厚1μm以上の結晶薄膜を得ることはできていなかった。また、特許文献3~6記載の方法で得られた膜は、いずれも実際には、基板から剥離できるものではなかった。
また、本発明者らは、さらに検討を重ねて、コランダム構造を有する酸化物半導体を主成分として含む板状体の製造にも成功した。
また、本発明者らは、前記結晶性半導体膜または前記板状体を用いて半導体装置を製造し、得られた半導体装置が、リーク電流が抑制されており、耐圧性および放熱性に優れていることを見出し、上記した各種知見を得た後、さらに検討を重ねて、本発明を完成させるに至った。
下地基板は、上記の結晶性半導体膜の支持体となるものであれば特に限定されない。絶縁体基板であってもよいし、半導体基板であってもよいし、導電性基板であってもよいが、前記下地基板が、絶縁体基板であるのが好ましく、表面に金属膜を有する基板であるのも好ましい。本発明においては、前記下地基板が、コランダム構造を有する結晶物を主成分として含む基板、またはβ-ガリア構造を有する結晶物を主成分として含む基板であるのも好ましい。コランダム構造を有する結晶物を主成分として含む基板は、基板中の組成比で、コランダム構造を有する結晶物を50%以上含むものであれば、特に限定されないが、本発明においては、70%以上含むものであるのが好ましく、90%以上であるのがより好ましい。コランダム構造を有する結晶を主成分とする基板としては、例えば、サファイア基板(例:c面サファイア基板)や、α型酸化ガリウム基板などが挙げられる。β-ガリア構造を有する結晶物を主成分とする基板は、基板中の組成比で、β-ガリア構造を有する結晶物を50%以上含むものであれば、特に限定されないが、本発明においては、70%以上含むものであるのが好ましく、90%以上であるのがより好ましい。β-ガリア構造を有する結晶物を主成分とする基板としては、例えばβ-Ga2O3基板、又はGa2O3とAl2O3とを含みAl2O3が0wt%より多くかつ60wt%以下である混晶体基板などが挙げられる。その他の下地基板の例としては、六方晶構造を有する基板(例:SiC基板、ZnO基板、GaN基板)などが挙げられる。六方晶構造を有する基板上には、直接または別の層(例:緩衝層等)を介して、前記結晶性半導体膜を形成するのが好ましい。下地基板の厚さは、本発明においては特に限定されないが、好ましくは、50~2000μmであり、より好ましくは200~800μmである。
なお、下地基板が、表面に金属膜が形成されている基板である場合には、基板部分のみを剥離してもよく、金属膜が半導体層表面に残っていてもよい。金属膜を半導体層表面に残すことで、半導体表面上の電極形成が容易かつ良好なものとすることができる。
本発明においては、上記のようにして成膜することにより、厚さが7.6μm以上、好ましくは10μm以上、より好ましくは15μm以上、最も好ましくは50μm以上の板状体を得ることができる。前記板状体は、半導体層として用いることができるだけでなく、基板としても用いることができる。
図1は、本発明に係るショットキーバリアダイオード(SBD)の一例を示している。図1のSBDは、n-型半導体層101a、n+型半導体層101b、ショットキー電極105aおよびオーミック電極105bを備えている。
図4は、本発明に係る金属半導体電界効果トランジスタ(MESFET)の一例を示している。図4のMESFETは、n-型半導体層111a、n+型半導体層111b、緩衝層(バッファ層)118、半絶縁体層114、ゲート電極115a、ソース電極115bおよびドレイン電極115cを備えている。
図5は、本発明に係る光電子移動度トランジスタ(HEMT)の一例を示している。図5のHEMTは、バンドギャップの広いn型半導体層121a、バンドギャップの狭いn型半導体層121b、n+型半導体層121c、半絶縁体層124、緩衝層128、ゲート電極125a、ソース電極125bおよびドレイン電極125cを備えている。
図5のHEMTでは、ゲート電極下に良好な空乏層が形成されるので、ドレイン電極からソース電極に流れる電流を効率よく制御することができる。また、本発明においては、さらにリセス構造とすることで、ノーマリーオフを発現することができる。
本発明の半導体装置がMOSFETである場合の一例を図6に示す。図6のMOSFETは、トレンチ型のMOSFETであり、n-型半導体層131a、n+型半導体層131b及び131c、ゲート絶縁膜134、ゲート電極135a、ソース電極135bおよびドレイン電極135cを備えている。
図9は、本発明の半導体装置がSITである場合の一例を示す。図9のSITは、n-型半導体層141a、n+型半導体層141b及び141c、ゲート電極145a、ソース電極145bおよびドレイン電極145cを備えている。
図9のSITのオン状態では、前記ソース電極145bと前記ドレイン電極145cとの間に電圧を印可し、前記ゲート電極145aに前記ソース電極145bに対して正の電圧を与えると、前記n-型半導体層141a内にチャネル層が形成され、電子が前記n-型半導体層141aに注入され、ターンオンする。オフ状態は、前記ゲート電極の電圧を0Vにすることにより、チャネル層ができなくなり、n-型半導体層141aが空乏層で満たされた状態になり、ターンオフとなる。
本発明の半導体装置が発光ダイオード(LED)である場合の一例を図16に示す。図16の半導体発光素子は、第2の電極165b上にn型半導体層161を備えており、n型半導体層161上には、発光層163が積層されている。そして、発光層163上には、p型半導体層162が積層されている。p型半導体層162上には、発光層163が発生する光を透過する透光性電極167を備えており、透光性電極167上には、第1の電極165aが積層されている。なお、図16の半導体発光素子は、電極部分を除いて保護層で覆われていてもよい。
1.成膜装置
図18を用いて、本実施例で用いたミストCVD装置19を説明する。ミストCVD装置19は、基板20を載置するサセプタ21と、キャリアガスを供給するキャリアガス供給手段22と、キャリアガス供給手段22から送り出されるキャリアガスの流量を調節するための流量調節弁23と、原料溶液24aが収容されるミスト発生源24と、水25aが入れられる容器25と、容器25の底面に取り付けられた超音波振動子26と、内径40mmの石英管からなる供給管27と、供給管27の周辺部に設置されたヒーター28を備えている。サセプタ21は、石英からなり、基板20を載置する面が水平面から傾斜している。供給管27とサセプタ21をどちらも石英で作製することにより、基板20上に形成される膜内に装置由来の不純物が混入することを抑制している。
なお、サセプタ21として、図19に示されるサセプタ51を用いた。なお、サセプタの傾斜角を45°とし、供給管内の基板・サセプタの総面積を、図19に示される通り、サセプタ領域を徐々に大きくなるようにし、排出領域を徐々に狭くなるようにし、図20に示される通り、サセプタ領域を排出領域よりも大きくなるように構成した。
臭化ガリウムと酸化ゲルマニウムをガリウムに対するゲルマニウムの原子比が1:0.05となるように水溶液を調整した。この際、48%臭化水素酸溶液を体積比で10%を含有させた。条件1では、酸化ゲルマニウムの濃度は、5.0×10-3mol/Lとした。
この原料溶液24aをミスト発生源24内に収容した。
次に、基板20として、1辺が10mmの正方形で厚さ600μmのc面サファイア基板をサセプタ21上に設置させ、ヒーター28を作動させて供給管27内の温度を500℃にまで昇温させた。次に、流量調節弁23を開いてキャリアガス供給手段22からキャリアガスを供給管27内に供給し、供給管27の雰囲気をキャリアガスで十分に置換した後、キャリアガスの流量を5L/minに調節した。キャリアガスとしては、酸素ガスを用いた。
次に、超音波振動子26を2.4MHzで振動させ、その振動を、水25aを通じて原料溶液24aに伝播させることによって、原料溶液24aを微粒子化させて、原料微粒子を生成した。
この原料微粒子が、キャリアガスによって供給管27内に導入され、供給管27内で反応して、基板20の成膜面でのCVD反応によって基板20上に膜を形成した。
得られた膜の相の同定をした。同定は、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことによって行った。測定は、CuKα線を用いて行った。その結果、得られた膜は、α-Ga2O3であった。また、得られた結晶性半導体膜の膜厚は3.5μmであった。
臭化ガリウムと酸化ゲルマニウムをガリウムに対するゲルマニウムの原子比が1E-7、1E-6、8E-5、4E-4、2E-3、1E-2、2E-1、8E-1となるようにそれぞれ原料溶液を調整した。この際、48%臭化水素酸溶液を体積比で10%を含有させた。実施例1と同様の成膜条件で成膜を行い、SIMSを用いて、入射イオン種は酸素、出力3kV、200nAで不純物濃度の定量分析を行った。その結果を図21に示す。図21に示すように、液中ドーパント含有割合と、結晶膜中のドーピング量が相関関係を有し、液中ドーパント含有割合を調整することによって、形成される膜中のドーピング濃度を容易に制御することができることが分かった。
酸化ゲルマニウムの濃度を5.0×10-3mol/Lに代えて1.0×10-3mol/Lにしたこと以外は、条件1と同様にして、n+半導体層として、ゲルマニウムをドーピングしたα-Ga2O3膜をc面サファイア基板上に成膜し、ついで、膜上に、n-半導体層として、ドーピングしていないα-Ga2O3膜を成膜した。n-半導体層の形成については、何もドーピングしなかったこと以外は、上記と同様にして成膜することにより行った。得られた結晶性半導体膜の膜厚は7.6μmであり、成膜時間は180分であった。そして、図22に示すように、n-半導体層101aの一部をエッチングした後、スパッタリングで、n+半導体層101b上にTiからなるオーミック電極105bを、n-半導体層101a上にPtからなるショットキー電極105aをそれぞれ設けて、SBDを作製した。
得られたSBDにつき、SIMS分析(Cs 3kV 200nA Ap16% Raster400)を行った。結果を図23に示す。図23から明らかなように、横軸のスパッタリング時間で1500秒を過ぎたあたりまではゲルマニウムが含まれておらず、また、1500秒を過ぎたあたりから4000秒あたりまではゲルマニウムが均一に含まれており、n+型半導体層およびn-型半導体層が良好に形成されていることが分かる。
臭化ガリウム、オルトケイ酸テトラエチルをそれぞれ物質量比で100:1となるように水溶液を調整した。この際、48%臭化水素酸溶液を体積比で10%を含有させた。臭化ケイ素の濃度は、1.0×10-3mol/Lとした。成膜温度500℃、キャリアガスは窒素、流量は5L/minの条件で90分間成膜を行った。なお、その他の成膜条件は、実施例1と同様にして成膜した。得られた膜につき、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことにより、相の同定を行った。なお、測定には、CuKα線を用いた。その結果、得られた膜は、α-Ga2O3であった。膜厚は2.5μmであった。
また、得られた膜につき、SIMS分析(Cs 3kV 200nA Ap16% Raster400)を行った。結果を図24に示す。ケイ素が良好にドーピングされていることがわかる。なお、電気特性等もゲルマニウム含有の実施例1と同等の性能を示した。
実施例3と同様にして、結晶性半導体膜を成膜した。成膜後、超音波振動により、結晶性半導体膜を基板から剥離した。得られた膜につき、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことにより、相の同定を行った。なお、測定には、CuKα線を用いた。その結果、得られた膜は、α-Ga2O3であった。膜厚は7.6μmであり、成膜時間は180分であった。
また、得られた自立膜につき、X線回折装置を用いて、構造評価した。X線回折結果として、X線回折像を図25に示す。図25からも明らかなように、基板の回折斑点が存在せず、自立膜であることが分かる。
図26に示すように、実施例5で得られた自立膜171に、ショットキー電極175aとしてタングステンを、オーミック電極175bとしてインジウムをそれぞれ用いて、SBDを作製した。得られたSBDにつき、電流電圧特性を評価した。結果を図27に示す。
実施例1と同様にして、結晶性半導体膜を長時間成膜した。得られた膜につき、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことにより、相の同定を行った。なお、測定には、CuKα線を用いた。その結果、得られた膜は、α-Ga2O3であった。また、膜厚は50μmであり、膜厚が50μmになると、もはや膜ではなく板状となる。
実施例1と同様にして、結晶性半導体膜を成膜した。得られた膜につき、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことにより、相の同定を行った。なお、測定には、CuKα線を用いた。その結果、得られた膜は、α-Ga2O3であった。また、膜厚は1.9μmであった。得られた膜をそのまま用いて、図28に示す通り、MESFETを作製した。図28のMESFETは、ゲート電極185a、ソース電極185b、ドレイン電極185c、n型半導体層181および基板189を備えている。n型半導体層181はα-Ga2O3であり、ゲート電極185aは白金(Pt)からなり、ソース電極185bおよびドレイン電極185cは、それぞれチタン(Ti)金(Au)合金から形成されている。作製したMESFETのDC特性を図29に示す。図29から明らかな通り、リーク電流がほとんどなく、特に、ゲート電圧-25Vで0.5nA程度という結果を得た。また、ゲート電圧1Vで519μAに至ったので、オン・オフ比も106という比較的高い値であった。
9-1.成膜装置
図30を用いて、本実施例で用いたミストCVD装置1を説明する。ミストCVD装置1は、キャリアガスを供給するキャリアガス源2aと、キャリアガス源2aから送り出されるキャリアガスの流量を調節するための流量調節弁3aと、キャリアガス(希釈)を供給するキャリアガス(希釈)源2bと、キャリアガス(希釈)源2bから送り出されるキャリアガス(希釈)の流量を調節するための流量調節弁3bと、原料溶液4aが収容されるミスト発生源4と、水5aが入れられる容器5と、容器5の底面に取り付けられた超音波振動子6と、成膜室7と、ミスト発生源4から成膜室7までをつなぐ供給管9と、成膜室7内に設置されたホットプレート8と、熱反応後のミスト、液滴および排気ガスを排出する排気口11とを備えている。なお、ホットプレート8上には、基板10が設置されている。
臭化ガリウムと酸化ゲルマニウムを水に混合し、ガリウムに対するゲルマニウムの原子比が1:0.01となるように水溶液を調整し、この際、臭化水素酸を体積比で10%を含有させ、これを原料溶液とした。
上記2.で得られた原料溶液4aをミスト発生源4内に収容した。次に、基板10として、4インチのサファイア基板をホットプレート8上に設置し、ホットプレート8を作動させて成膜室7内の温度を550℃にまで昇温させた。次に、流量調節弁3a、3bを開いて、キャリアガス源であるキャリアガス供給手段2a、2bからキャリアガスを成膜室7内に供給し、成膜室7の雰囲気をキャリアガスで十分に置換した後、キャリアガスの流量を5.0L/分に、キャリアガス(希釈)の流量を0.5L/分にそれぞれ調節した。なお、キャリアガスとして酸素を用いた。
次に、超音波振動子6を2.4MHzで振動させ、その振動を、水5aを通じて原料溶液4aに伝播させることによって、原料溶液4aを霧化させてミスト4bを生成させた。このミスト4bが、キャリアガスによって、供給管9内を通って、成膜室7内に導入され、大気圧下、550℃にて、成膜室7内でミストが熱反応して、基板10上にn+層が形成された。また、2層目として、酸化ゲルマニウムを用いていないこと以外は、1層目と同じ原料溶液を用いて、n+層上に、1層目と同じ条件で、2層目としてn-層を形成した。なお、成膜時間は4時間30分間であった。
また、図18のミストCVD装置を用いて、2層目を上記と同条件で再成長させた。成膜時間は120分であった。結晶性半導体膜の膜厚は計11.9μmであり、うち、n+層の膜厚は、3.8μmであり、n-層の膜厚は、8.1μmであった。なお、XRD回折装置を用いて、得られた膜の相の同定を行ったところ、得られた膜はいずれもα-Ga2O3であった。
サファイア基板をα-Ga2O3膜から剥離した後、n-層上にショットキー電極として金を、n+層上にオーミック電極としてTi/Auを、それぞれ蒸着により形成し、SBDを作製した。
また、得られたSBDにつき、電流電圧特性を評価した。順方向での結果を図31に示し、逆方向での結果を図32に示す。結果から明らかなとおり、半導体の電気特性に優れており、特に、逆バイアス時の耐圧は300Vを超え、本発明品は、良好なダイオード特性を有していることがわかる。
10-1.成膜装置
実施例9と同様に、図30に示される成膜装置を用いた。
0.05Mの鉄アセチルアセトナート水溶液に、塩酸を体積比で1.5%含有させ、これをバッファ層用原料溶液とした。
上記10-2.で得られたバッファ層用原料溶液4aをミスト発生源4内に収容した。次に、基板10として、サファイア基板をホットプレート8上に設置し、ホットプレート8を作動させてヒーターの温度を550℃にまで昇温させた。次に、流量調節弁3a、3bを開いて、キャリアガス源であるキャリアガス供給手段2a、2bからキャリアガスを成膜室7内に供給し、成膜室7の雰囲気をキャリアガスで十分に置換した後、キャリアガスの流量を2.0L/分に、キャリアガス(希釈)の流量を0.5L/分にそれぞれ調節した。なお、キャリアガスとして窒素を用いた。
次に、超音波振動子6を2.4MHzで振動させ、その振動を、水5aを通じて原料溶液4aに伝播させることによって、原料溶液4aを霧化させてミスト4bを生成させた。このミスト4bが、キャリアガスによって、供給管9内を通って、成膜室7内に導入され、大気圧下、550℃にて、成膜室7内でミストが熱反応して、基板10上にバッファ層が形成された。なお、成膜時間は30分間であった。
0.05Mの臭化ガリウム水溶液を用意し、この際、臭化水素酸を体積比で20%を含有させ、さらに、ガリウムに対してスズが8原子%となるように臭化スズを加え、これを原料溶液とした。
上記10-5.で得られた原料溶液4aをミスト発生源4内に収容した。次に、基板10として、バッファ層付きのサファイア基板をホットプレート8上に設置し、ホットプレート8を作動させてヒーターの温度を500℃にまで昇温させた。次に、流量調節弁3a、3bを開いて、キャリアガス源であるキャリアガス供給手段2a、2bからキャリアガスを成膜室7内に供給し、成膜室7の雰囲気をキャリアガスで十分に置換した後、キャリアガスの流量を1.0L/分に、キャリアガス(希釈)の流量を0.5L/分にそれぞれ調節した。なお、キャリアガスとしてフォーミングガス(H2:N2=5:95)を用いた。
次に、超音波振動子6を2.4MHzで振動させ、その振動を、水5aを通じて原料溶液4aに伝播させることによって、原料溶液4aを霧化させてミスト4bを生成させた。このミスト4bが、キャリアガスによって、供給管9内を通って、成膜室7内に導入され、大気圧下、500℃にて、成膜室7内でミストが熱反応して、基板10上にバッファ層が形成された。なお、成膜時間は300分間であった。
濃塩酸でバッファ層を溶かして、上記10-4.で得た膜を基板から剥離した。得られた膜の膜厚は4μmであった。また、X線回折装置を用いて、膜の同定を行ったところ、α-Ga2O3であった。XRDの結果を図33に示す。図33から明らかなとおり、サファイア基板のピークもバッファ層のピークもなく、α-Ga2O3のきれいな剥離膜であることがわかる。また、得られたα-Ga2O3膜をレーザーで1mm角に切り出した。切り出す前のα-Ga2O3膜の写真を図34に示し、切り出した後のα-Ga2O3膜を図35に示す。図34から明らかなように、得られた剥離膜は、5mm角以上の大面積を有していた。また、図35からも明らかな通り、1mm角の良質なα-Ga2O3膜を切り出すことができる。
2a キャリアガス源
2b キャリアガス(希釈)源
3a 流量調節弁
3b 流量調節弁
4 ミスト発生源
4a 原料溶液
4b ミスト
5 容器
5a 水
6 超音波振動子
7 成膜室
8 ホットプレート
9 供給管
10 基板
11 排気口
19 ミストCVD装置
20 基板
21 サセプタ
22 キャリアガス供給手段
23 流量調節弁
24 ミスト発生源
24a 原料溶液
25 容器
25a 水
26 超音波振動子
27 成膜室
28 ヒーター
51 サセプタ
52 ミスト加速手段
53 基板保持部
54 支持部
55 供給管
61 基板・サセプタ領域
62 排出領域
101a n-型半導体層
101b n+型半導体層
102 p型半導体層
103 半絶縁体層
104 絶縁体層
105a ショットキー電極
105b オーミック電極
109 基板
111a n-型半導体層
111b n+型半導体層
114 半絶縁体層
115a ゲート電極
115b ソース電極
115c ドレイン電極
118 緩衝層
121a バンドギャップの広いn型半導体層
121b バンドギャップの狭いn型半導体層
121c n+型半導体層
123 p型半導体層
124 半絶縁体層
125a ゲート電極
125b ソース電極
125c ドレイン電極
128 緩衝層
129 基板
131a n-型半導体層
131b 第1のn+型半導体層
131c 第2のn+型半導体層
132 p型半導体層
134 ゲート絶縁膜
135a ゲート電極
135b ソース電極
135c ドレイン電極
138 緩衝層
139 半絶縁体層
141a n-型半導体層
141b 第1のn+型半導体層
141c 第2のn+型半導体層
142 p型半導体層
145a ゲート電極
145b ソース電極
145c ドレイン電極
151 n型半導体層
151a n-型半導体層
151b n+型半導体層
152 p型半導体層
154 ゲート絶縁膜
155a ゲート電極
155b エミッタ電極
155c コレクタ電極
161 n型半導体層
162 p型半導体層
163 発光層
165a 第1の電極
165b 第2の電極
167 透光性電極
169 基板
171 α-Ga2O3層
175a タングステン電極
175b インジウム電極
181 n型半導体層
185a ゲート電極
185b ソース電極
185c ドレイン電極
189 基板
Claims (14)
- コランダム構造を有する酸化物半導体を主成分として含む結晶性半導体膜であって、膜厚が1μm以上であることを特徴とする結晶性半導体膜。
- 前記酸化物半導体が、ガリウム、インジウムおよびアルミニウムから選ばれる1種または2種以上の酸化物を主成分として含む請求項1記載の結晶性半導体膜。
- 膜厚が、7.6μm以上である請求項1または2に記載の結晶性半導体膜。
- 自立膜である請求項1~3のいずれかに記載の結晶性半導体膜。
- コランダム構造を有する酸化物半導体を主成分として含むことを特徴とする板状体。
- 厚さが50μm以上である請求項5記載の板状体。
- 前記酸化物半導体が、ガリウム、インジウムおよびアルミニウムから選ばれる1種または2種以上の酸化物を主成分として含む請求項5または6に記載の板状体。
- 基板である請求項5~7のいずれかに記載の板状体。
- 請求項1~4のいずれかに記載の結晶性半導体膜または請求項5~8のいずれかに記載の板状体を含むことを特徴とする半導体構造。
- 請求項9記載の半導体構造を備えることを特徴とする半導体装置。
- 縦型デバイスである請求項10記載の半導体装置。
- パワーデバイスである請求項10または11に記載の半導体装置。
- ショットキーバリアダイオード(SBD)、金属半導体電界効果トランジスタ(MESFET)、高電子移動度トランジスタ(HEMT)、金属酸化膜半導体電界効果トランジスタ(MOSFET)、静電誘導トランジスタ(SIT)、接合電界効果トランジスタ(JFET)、絶縁ゲート型バイポーラトランジスタ(IGBT)または発光ダイオード(LED)である請求項10~12のいずれかに記載の半導体装置。
- コランダム構造を有する酸化物半導体を主成分として含む結晶性半導体膜であって、膜厚が1μm以上であり、かつ表面積が9mm2以上であることを特徴とする結晶性半導体膜。
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JP2016535940A JP6281146B2 (ja) | 2014-07-22 | 2015-07-21 | 結晶性半導体膜および板状体ならびに半導体装置 |
EP20200067.5A EP3783666A1 (en) | 2014-07-22 | 2015-07-21 | Crystalline semiconductor film, sheet like object, and semiconductor device |
CN201580032796.1A CN106415845B (zh) | 2014-07-22 | 2015-07-21 | 结晶性半导体膜和板状体以及半导体装置 |
KR1020197025453A KR102125822B1 (ko) | 2014-07-22 | 2015-07-21 | 결정성 반도체막 및 판상체 및 반도체장치 |
CN201911118416.2A CN110828552B (zh) | 2014-07-22 | 2015-07-21 | 结晶性半导体膜和板状体以及半导体装置 |
KR1020187030849A KR102018329B1 (ko) | 2014-07-22 | 2015-07-21 | 결정성 반도체막 및 판상체 및 반도체장치 |
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