WO2007129545A1 - 耐熱性基板内蔵回路配線板 - Google Patents

耐熱性基板内蔵回路配線板 Download PDF

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Publication number
WO2007129545A1
WO2007129545A1 PCT/JP2007/058587 JP2007058587W WO2007129545A1 WO 2007129545 A1 WO2007129545 A1 WO 2007129545A1 JP 2007058587 W JP2007058587 W JP 2007058587W WO 2007129545 A1 WO2007129545 A1 WO 2007129545A1
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WO
WIPO (PCT)
Prior art keywords
substrate
heat
built
wiring board
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/058587
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English (en)
French (fr)
Japanese (ja)
Inventor
Takashi Kariya
Toshiki Furutani
Takeshi Kawanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to EP07742023A priority Critical patent/EP2015623B1/en
Priority to JP2008514421A priority patent/JPWO2007129545A1/ja
Priority to CN2007800071626A priority patent/CN101395978B/zh
Publication of WO2007129545A1 publication Critical patent/WO2007129545A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a circuit wiring board with a built-in heat-resistant substrate, and more particularly, to a circuit wiring board with a built-in heat-resistant substrate suitable for a package substrate on which an IC chip is mounted.
  • Japanese Patent Application Laid-Open No. 2002-344142 discloses a multilayer printed wiring board for mounting an IC chip, in which an interlayer resin insulation layer and a conductor layer are alternately stacked on a resinous core substrate having a through-hole conductor.
  • a multilayer printed wiring board in which conductor layers are connected by via-hole conductors is disclosed.
  • JP 2001-102479 discloses an interposer for electrically connecting an IC chip and a package substrate.
  • the interposer body 20 in FIG. 2 is silicon, and an IC chip electrode is connected to a via conductor 27 penetrating the silicon, and a wiring layer is formed on a silicon substrate opposite to the IC.
  • Patent Document 1 JP 2002-344142
  • Patent Document 2 JP 2001-102479
  • An object of the present invention is to provide a heat-resistant circuit board built-in circuit wiring board capable of realizing finer. Another purpose is to increase the yield of electronic components and reduce the manufacturing cost of electronic components by incorporating a wiring layer of electronic components (eg, IC chips) onto a heat-resistant substrate. Another object is to reduce the coefficient of thermal expansion of the entire circuit wiring board with a built-in heat-resistant substrate.
  • a wiring board particularly a circuit wiring board with a built-in heat-resistant substrate.
  • it improves the electrical connection reliability between the built-in heat-resistant board and the built-in wiring board with built-in heat-resistant board, and prevents peeling between the two to prevent the insulation layer of the built-in wiring board
  • the purpose is to prevent cracks in the conductor layer.
  • the inventors of the present invention are a heat-resistant substrate built-in wiring board comprising a heat-resistant board and a built-in wiring board containing the heat-resistant board.
  • a substrate is formed on the core substrate, a through-hole conductor that conducts between the front and back surfaces of the core substrate, and the core substrate, and an interlayer resin insulation layer and a conductor layer are alternately laminated, and each conductor interlayer
  • the idea was to form a circuit board with a built-in heat-resistant substrate consisting of a build-up wiring layer connected by via-hole conductors.
  • a build-up wiring layer can be formed on the surface of the Si substrate having excellent flatness, so that it is thinner than the resin substrate with unevenness. Conductor circuits with excellent wiring and thickness accuracy can be formed, and fine pitch circuit wiring boards can be realized.
  • the build-up wiring layer is formed on the mirror-finished surface, the wiring variation is reduced and the impedance variation can be reduced.
  • the density can be increased and the size can be reduced, and the thickness can be reduced by reducing the number of layers.
  • passive elements such as L (inductor), C (capacitor), R (resistor), VRM (DC-DC converter) should be formed on the core substrate surface, build-up wiring layer or in the build-up wiring layer. This makes it possible to enhance the power supply and eliminate noise. Furthermore, by forming part of the rewiring layer on the IC side on the heat-resistant substrate side, it is possible to improve IC yield and manufacturing cost.
  • connection pad of the heat resistant substrate can be connected by plating or the like, and the reliability can be improved. Further, since it differs from an interposer such as that disclosed in Japanese Patent Application Laid-Open No. 2001-102479, the number of connection points due to solder bumps is reduced and the number of reflows received by the board is reduced.
  • the rewiring layer is formed on the core substrate having a small thermal expansion coefficient, the occupation ratio of the heat resistant substrate to the circuit wiring board with the built-in heat resistant substrate becomes larger than when the rewiring layer is not formed. As a result, the thermal expansion coefficient of the circuit wiring board with built-in heat-resistant board can be reduced compared to the case without the rewiring layer (the thermal expansion coefficient of the circuit wiring board with built-in heat-resistant board becomes the thermal expansion coefficient between the resin board and the electronic component). .
  • the thermal expansion coefficient When the thermal expansion coefficient is reduced, the shear stress between the electronic component and the circuit wiring board with built-in heat-resistant board or between the heat-resistant board built-in circuit wiring board and the mother board connected to the circuit wiring board with built-in heat-resistant board is reduced.
  • the connection member for example, solder
  • the connection member that connects between the component and the circuit wiring board with built-in heat-resistant board or between the circuit board with built-in heat-resistant board and the mother board is less likely to break.
  • the rewiring layer is formed on the core substrate, the pitch between the through-hole conductors formed on the core substrate is widened. As a result, cracks are unlikely to occur in the core substrate having a low thermal expansion coefficient.
  • the core board and the through-hole conductors formed on the core board have different coefficients of thermal expansion, the core board is deformed by the through-hole conductor around the through-hole conductor. The smaller the distance between through-hole conductors, the greater the amount of deformation of the core substrate between the through-hole conductors. Further, by providing a rewiring layer, a through-hole conductor can be formed over the entire core substrate. For this reason, since the thermal expansion coefficient and Young's modulus are substantially uniform in the core substrate, the warpage of the core substrate is reduced, and peeling between the core substrate crack and the heat resistant substrate and the built-in wiring substrate can be prevented. In order to arrange the through-hole conductors substantially uniformly over the entire core substrate, it is preferable to form a build-up layer (surface rewiring layer) only on the surface of the core substrate.
  • a build-up layer surface rewiring layer
  • a build-up wiring layer is formed on a core substrate (thickness of about 0.3 mm) made of silicon or the like using a core substrate (thickness of about 0.8 mm) made of glass epoxy of JP-A-2002-34414. Therefore, the thickness of the circuit wiring board can be reduced (the thickness of the multilayer printed wiring board disclosed in JP-A-2002-34414 can be reduced to about 0.2 to 0.5 mm compared to about 1 mm. ), Lowering the inductance and improving the electrical characteristics.
  • the thermal expansion coefficient of the circuit board with a heat-resistant substrate can be made closer to the thermal expansion coefficient of the IC chip.
  • the material constituting the core substrate of the heat resistant substrate is preferably Si, but is not particularly limited.
  • Ceramic substrates such as Pyrex glass (Pyrex is a registered trademark), dinorequoia, ani- nium nitride, silicon nitride, silicon carbide, alumina, mullite, cordierite, steatite, phonoresterite, and the like.
  • the Si substrate is most easily and inexpensively available, so it is desirable in terms of cost.
  • solder material used for the joint between an electronic component such as an IC and a circuit wiring board (package board) is not particularly limited, but S, Ie, Sn / Pb, Examples include Sn / Ag, Sn, Sn / Cu, Sn / Sb, Sn / In / Ag, Sn / Bi, Sn / ln, copper paste, silver paste, and conductive resin.
  • the through hole (through hole) of the core substrate may be filled with a conductive material, or a stub conductor (through hole conductor) is formed on the inner wall of the through hole, and an insulating material or a conductive material is applied to the unfilled portion.
  • a filled structure may be used.
  • the conductive material to be filled in the through hole is not particularly limited.
  • the conductive paste is made of a single metal such as copper, gold, silver, or Eckenole, or a metal composed of two or more kinds. It is preferable that it is filled. This is because the resistance is low compared to the conductive base, so that the power supply to the IC is smooth and the amount of heat generated is low.
  • FIG. 1 shows the configuration of the circuit wiring board with built-in heat-resistant substrate of Example 1 constituting the resin package substrate.
  • the heat resistant substrate built-in circuit wiring board 10 incorporates a heat resistant substrate 30.
  • the heat resistant substrate 30 includes a base material (core substrate) 20.
  • the substrate 20 is provided with through-hole conductors 36, and through-hole pads 38 are formed at both ends of the through-hole conductors 36.
  • Conductor circuits 39 are formed on both surfaces of the core substrate 20.
  • a rewiring layer (build-up wiring layer) composed of via-hole conductor 48, conductor circuit 49 and insulating layer 40 and via-hole conductor 14 8, conductor circuit 149 and insulating layer 140 is disposed on both surfaces of substrate 20. .
  • a solder resist layer 70 is formed on the front and back of the circuit wiring board 10 with a built-in heat-resistant substrate, and the solder resist layer 70 has an opening 70a for exposing a part of the via hole conductor 148 and the conductor circuit 149.
  • the exposed portions of via-hole conductor 148 and conductor circuit 149 correspond to mounting pad 148P.
  • Solder bumps 78U are provided on the mounting node 148P.
  • the IC chip 90 is mounted by connecting the electrodes 92 of the IC chip 90 via the solder bumps 78U.
  • An interlayer resin insulation layer 150 is disposed.
  • a solder resist layer 70 is formed on the interlayer resin insulation layer 150, and solder bumps 78 D are formed on the via hole conductor 160 through the opening 70 a of the solder resist layer 70.
  • the mounting pad 148P is formed immediately above the via-hole conductor 148 or on the conductor circuit 149 extending beyond the via-hole conductor 148 (other than directly above the via-hole conductor 148).
  • the mounting pads 148P are arranged in a grid or staggered pattern, and the pitch between the mounting pads 148P can be 30-150 / im pitch.
  • the insulating and heat resistant substrate between the mounting pads 148P 30 In consideration of the characteristics and taking in the wiring layer of electronic parts into the printed wiring board, a pitch of 50 to 100 / im is preferable.
  • the mounting pad 148P of the mounting part is expanded with the build-up layer at its pitch, and the conductor circuit on the core substrate 20 (including the conductor circuit that closes the through-hole conductor 36, on the central through-hole conductor 36 in FIG. Is connected to the through hole conductor 36 via the conductor circuit 38).
  • the pitch between the through-hole conductors 36 can be 30 to 200 111, which is larger than the pitch of the mounting pad 148P, and the insulation reliability of the core substrate 20, heat cycle resistance and crack resistance are 75.
  • ⁇ : 150 xm is preferred.
  • a build-up layer (back surface redistribution layer) is also formed on the back surface of the core substrate 20, and the back surface is for connection to make electrical contact with the built-in wiring substrate containing the heat resistant substrate 30.
  • a pad 148D is formed. Connection pad 148D pitch is through-hole conductor 36 pitch It can be larger, 50-250 / im. The connection pad 148D is formed immediately above the via-hole conductor 148 or on the conductor circuit 149 extending from the via-hole conductor 148. A via-hole conductor 60 of a built-in wiring board is formed on the connection pad 148D.
  • the surface rewiring layer is not formed, and the through-hole pad 38 and the conductor circuit 39 on the surface of the substrate 20 can be used as the mounting pad 148P.
  • all the mounting pads 14 8P may be used as the through-hole pads 38 directly above the through-hole conductors 36, or a part of the conductor circuit 39 that connects the mounting pads 148P located on the outer periphery to the through-hole conductors 36 ( The mounting pad 148P located at the center may be part of the through-hole pad 38 directly above the through-hole conductor 36, as shown in FIG.
  • connection pad 148D the conductor circuit 39 and the through-hole pad 38 on the back surface of the base material 20 can be used as the connection pad 148D.
  • all the connection pads 148D may be used as the through-hole pads 38 directly above the through-hole conductors 36, or a part of the conductor circuit 39 that connects the connection pads 148D on the outer periphery of the core substrate 20 to the through-hole conductors 36.
  • the center connection pad 148D can be used as part of the through-hole pad 38 directly above the through-hole conductor 36.
  • the heat-resistant substrate 30 is made of a base material because the pitch of the through-hole conductors 36 formed on the core substrate 20 can be expanded, and the heat-resistant substrate 30 has improved insulation, crack resistance, heat cycle resistance, etc. 20 and a surface rewiring layer (surface buildup layer) are preferable.
  • Base material 2 (1) Prepare a base material (core substrate) 20 made of silicon and having a thickness of 0.5 mm (Fig. 2 (A)). Base material 2
  • a UV laser irradiation is performed to form a through-hole conductor forming opening 22 penetrating the base material 20 (FIG. 2 (C)).
  • a UV laser was used, but instead, an opening can be formed by sandblasting or RIE.
  • a thermal oxidation treatment is performed at 1000 ° C to form an insulating film 24 (Fig. 2 (D)).
  • Thermal oxidation treatment Alternatively, CVD can be performed.
  • a Ni / Cu thin film 26 is formed by sputtering (FIG. 2E). Instead of spattering, it is also possible to use a non-electrical angle early approach.
  • Electrolytic copper plating treatment was performed using the thin film 26 as a lead for plating under the following plating solution and conditions to form an electrolytic copper plating 28 in the opening 22 to form a through-hole conductor 36.
  • base material 2
  • Electrolytic copper plating 28 is also formed on the 0 surface (Fig. 3 (A)).
  • a patterning is added to the electrolytic copper plating 28 to form a through-hole pad 38 and a conductor circuit 39 (FIG. 3C).
  • Insulating layers for example, ABF manufactured by Polyimide Ajinomoto Co., Inc.
  • Insulating layers 40 are provided on both surfaces of the base material 20, and an opening 40a is formed by a laser (FIG. 3 (D)).
  • a Ni / Cu thin film 44 is formed on the surface of the insulating layer 40 by sputtering, and a plating resist 42 having a predetermined pattern is provided on the thin film (FIG. 3E). Electroless plating can be used instead of sputtering.
  • FIG. 4C an insulating layer 140 is formed (FIG. 4C), and a via-hole conductor 148 and a conductor circuit 149 are provided to form a heat resistant substrate 30 (FIG. 4D).
  • the resin film for the interlayer resin insulation layer is subjected to main pressure bonding on the substrate under the conditions of a vacuum of 67 Pa, a pressure of 0.4 MPa, a temperature of 85 ° C., and a pressure bonding time of 60 seconds, and then thermosetting at 170 ° C. for 40 minutes.
  • the substrate after the above treatment is immersed in a neutralizing solution (manufactured by Shipley Co., Ltd.) and then washed with water. Further, by applying palladium catalyst to the surface of the roughened substrate (roughening depth 3 ⁇ ), catalyst nuclei are attached to the surface of the interlayer resin insulation layer and the inner wall surface of the filled via opening. Let That is, the substrate is immersed in a catalyst solution containing palladium chloride (PbCl 2) and stannous chloride (SnCl 3), and a catalyst is applied by precipitating noradium metal.
  • PbCl 2 palladium chloride
  • SnCl 3 stannous chloride
  • the substrate 30 is washed with 50 ° C water and degreased, washed with water at 25 ° C, then washed with sulfuric acid, and then electrolyzed and electrolyzed under the following conditions.
  • a plating film 54 is formed (FIG. 6 (C)).
  • the plating resist 53 is stripped and removed with 5% KH, and the non-electrolyzed film under the resist is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide.
  • Independent conductor circuit 58 and via hole conductor 60 are formed (FIG. 6D). Subsequently, roughened surfaces are formed on the surfaces of the conductor circuit 58 and the via hole conductor 60 (not shown).
  • solder resist composition 70 is applied to both sides of the multilayer wiring board at a thickness of 20 ⁇ m, and the conditions are 70 ° C for 20 minutes and 70 ° C for 30 minutes. After drying, a 5mm thick photomask with solder resist opening pattern drawn is applied to the solder resist layer. The film is exposed to ultraviolet light of 1000 mj / cm 2 in close contact with 70 and developed with a DMTG solution to form an opening 70a having a diameter of 200 ⁇ m (FIG. 7 (C)).
  • solder resist layer is cured by heating at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. And a solder resist pattern layer 70 having a thickness of 15 to 25 ⁇ m.
  • the via hole conductor 148 and the conductor circuit 149 exposed from the opening 70a become the mounting pad 148P.
  • solder paste containing tin-lead is printed in the opening 70a of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and the solder resist layer 70 on the other surface is further printed.
  • Solder paste containing tin and antimony is printed in the opening 70a, and solder bumps (solder bodies) are formed by reflowing at 200 to 240 ° C.
  • the circuit wiring with built-in heat-resistant substrate having solder bumps 78U and 78D A plate is obtained (Fig. 7 (D)).
  • the IC chip 90 is mounted in alignment with the circuit wiring board 10 with a built-in heat resistant substrate. Then reflow and mount (see Figure 1). Then, a sealant (underfill: not shown) is filled between the heat-resistant substrate built-in circuit wiring board 10 and the IC chip 90 and cured at 80 degrees for 15 minutes, and then at 150 degrees for 2 hours.
  • FIG. 8 shows the configuration of the heat resistant substrate built-in circuit wiring board of Example 2.
  • the heat-resistant substrate 30 has a built-in heat-resistant substrate 30.
  • the heat-resistant substrate 30 has a base material 20, through-hole conductors 36 are provided on the base material 20, and through-hole pads 38 are formed at both ends of the through-hole conductors 36.
  • a build-up wiring layer composed of the via hole conductor 48 and the insulating layer 40 is disposed on the surface (upper surface) of the heat-resistant substrate 30 on the IC chip side.
  • Solder bumps 78U are provided in the openings 70a of the solder resist layer 70 of the via-hole conductor 48.
  • the thickness of the circuit wiring board 10 with a built-in heat-resistant substrate is 0.1 to: 1. Omm.
  • the thickness of the core substrate 20 is 0.05 to 0.5 mm.
  • the thermal expansion coefficient of the base material (core substrate) 20 is 3.0 to 10 ppm.
  • the thermal expansion coefficient of the circuit wiring board 10 with a built-in heat resistant substrate can be reduced.
  • the stress due to the difference in thermal expansion between the IC chips 90A and 90B and the resin circuit board 10 with a heat-resistant substrate is reduced.
  • the stress applied to the solder bump between the IC chip and the resin package is reduced.
  • Example 1 the rewiring layer was provided on both surfaces of the core substrate.
  • Example 3 no rewiring is provided on the core substrate.
  • the core substrate 20 can make the heat-resistant substrate built-in circuit wiring board thin, and the mounted IC chip (Chip set) 90A, IC chip (GPLI) 90B and heat-resistant substrate built-in circuit wiring board 30 The thermal expansion coefficient can be made close, and disconnection due to thermal contraction can be prevented.
  • Example 4 The configuration of the heat resistant substrate built-in circuit wiring board according to the fourth embodiment will be described with reference to FIG.
  • the rewiring layer is provided on both surfaces of the core substrate 20.
  • the build-up wiring layer is provided on the surface (lower surface) of the core substrate 20 opposite to the IC chip (memory) 90A and the IC chip (logic) 90B.
  • substantially the same effect as that of the first embodiment can be obtained.
  • Example 1 described above with reference to FIG. 1, the rewiring layer is provided on both surfaces of the core substrate 20.
  • the build-up wiring layers are provided on both the surface (upper surface) of the core substrate 20 on the IC chip side and the surface (lower surface) on the opposite side of the IC chip.
  • Example 1 the heat-resistant substrate 30 is accommodated in the interlayer insulating layer 50 of the circuit wiring board 10 with the built-in heat-resistant substrate.
  • Example 6 the heat-resistant substrate 30 is arranged on the surface, and the interlayer resin insulating layer 50 on the surface of the circuit wiring board with the built-in heat-resistant substrate and the surface of the heat-resistant substrate 30 on the IC chip side Is almost flat so that there is no step. Further, the solder resist layer is not provided on the upper surface.
  • Example 1 the heat resistant substrate 30 is accommodated in the interlayer insulating layer 50 of the circuit wiring board 10 with the built-in heat resistant substrate.
  • Example 6 the surface of the heat-resistant substrate 30 protrudes from the interlayer resin insulating layer 50 on the surface of the circuit wiring board with the heat-resistant substrate. Further, the solder resist layer is not provided on the upper surface.
  • Example 8 The configuration of the heat resistant substrate built-in circuit wiring board according to Example 8 will be described with reference to FIG.
  • Example 1 the build-up layers 50 and 150 of the circuit wiring board with the built-in heat resistant substrate are provided on the lower surface side of the heat resistant substrate 30.
  • the build-up wiring layer 150 of the circuit wiring board with built-in heat-resistant substrate is also formed on the surface of the heat-resistant substrate 30 on the IC chip side.
  • Example 1 the through-hole pad 38 and the conductor circuit 39 are formed on the surface of the base material 20 of the heat resistant substrate 30.
  • Example 9 the through-hole pad 38 and the conductor circuit 39 are provided only on the surface of the base 20 of the heat-resistant substrate 30 on the IC chip side.
  • the through-hole pad 38 and the conductor circuit 39 are formed on both surfaces of the core substrate 20.
  • the through-hole pad 38 and the conductor circuit 39 are provided only on the surface of the base 20 of the heat resistant substrate 30 opposite to the IC chip.
  • the through-hole pad 38 and the conductor circuit 39 are formed on both surfaces of the core substrate 20.
  • no conductor circuit is provided on the substrate 20.
  • Example 2 to Example 11 the force in which the pitch of the mounting pad 148P and the pitch of the through-hole conductor 36 and the pitch of the connection pad 148D are the same.
  • Figure 1 As in the first embodiment described above with reference to FIG. 5, it is desirable that the pitch of the mounting pads 148P, the pitch of the through-hole conductors 36, and the pitch of the connection pads 148D be larger in this order.
  • a plurality of electronic components were mounted. For example, one side is an MPU and the other side is a memory, and both surface wiring layers (surface buildup layers) on the core substrate 20 are used. You can also provide wiring for the two to exchange signals.
  • Many electronic components include chip sets, logic, and graphics.
  • FIG. 1 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Embodiment 1 of the present invention.
  • FIG. 2 is a manufacturing process diagram of a heat-resistant substrate according to Example 1.
  • FIG. 3 is a manufacturing process diagram of a heat-resistant substrate according to Example 1.
  • FIG. 4 is a manufacturing process diagram of a heat-resistant substrate according to Example 1.
  • FIG. 5 is a manufacturing process diagram of a heat-resistant circuit board built-in circuit wiring board according to Example 1.
  • FIG. 6 is a manufacturing process diagram of a circuit wiring board with a built-in heat-resistant substrate according to Example 1.
  • FIG. 7 is a manufacturing process diagram of the circuit wiring board with built-in heat-resistant substrate according to Example 1.
  • FIG. 8 is a cross-sectional view of a circuit wiring board with a built-in heat resistant substrate according to Embodiment 2 of the present invention.
  • FIG. 9 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 3 of the present invention.
  • FIG. 10 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 4 of the present invention.
  • FIG. 11 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 5 of the present invention.
  • FIG. 12 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 6 of the present invention.
  • FIG. 13 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 7 of the present invention.
  • FIG. 14 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 8 of the present invention.
  • FIG. 15 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 9 of the present invention.
  • FIG. 16 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 10 of the present invention.
  • FIG. 17 is a cross-sectional view of a heat resistant substrate built-in circuit wiring board according to Example 11 of the present invention. Explanation of symbols

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/JP2007/058587 2006-05-02 2007-04-20 耐熱性基板内蔵回路配線板 Ceased WO2007129545A1 (ja)

Priority Applications (3)

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EP07742023A EP2015623B1 (en) 2006-05-02 2007-04-20 Circuit wiring board incorporating heat resistant substrate
JP2008514421A JPWO2007129545A1 (ja) 2006-05-02 2007-04-20 耐熱性基板内蔵回路配線板
CN2007800071626A CN101395978B (zh) 2006-05-02 2007-04-20 内置耐热性基板电路板

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US11/415,117 US7462784B2 (en) 2006-05-02 2006-05-02 Heat resistant substrate incorporated circuit wiring board
US11/415,117 2006-05-02

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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130104A (ja) * 2007-11-22 2009-06-11 Shinko Electric Ind Co Ltd 配線基板及び半導体装置及び配線基板の製造方法
JP2009141041A (ja) * 2007-12-05 2009-06-25 Shinko Electric Ind Co Ltd 電子部品実装用パッケージ
JP2010239126A (ja) * 2009-03-09 2010-10-21 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2012033777A (ja) * 2010-07-30 2012-02-16 Kyocer Slc Technologies Corp 配線基板
US9035463B2 (en) 2012-05-18 2015-05-19 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2015097280A (ja) * 2011-06-03 2015-05-21 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． インターポーザ試験構造と方法
US9066435B2 (en) 2012-03-30 2015-06-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
JP2015179795A (ja) * 2013-05-30 2015-10-08 京セラサーキットソリューションズ株式会社 配線基板
JP2016004999A (ja) * 2014-06-18 2016-01-12 ダイ−チュン フＤｙｉ−Ｃｈｕｎｇ ＨＵ Ｉｃパッケージ用高密度フィルム
US9425159B2 (en) 2013-06-05 2016-08-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9433085B2 (en) 2013-04-23 2016-08-30 Ibiden Co., Ltd. Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board
US9431347B2 (en) 2013-06-05 2016-08-30 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9565756B2 (en) 2012-03-30 2017-02-07 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9699921B2 (en) 2014-08-01 2017-07-04 Fujikura Ltd. Multi-layer wiring board
US9723728B2 (en) 2014-08-04 2017-08-01 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
JP2018093107A (ja) * 2016-12-06 2018-06-14 ルネサスエレクトロニクス株式会社 半導体装置
JP2019192886A (ja) * 2018-04-27 2019-10-31 新光電気工業株式会社 配線基板及び配線基板の製造方法
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate

Families Citing this family (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100544558C (zh) * 2004-04-28 2009-09-23 揖斐电株式会社 多层印刷配线板
JP4824397B2 (ja) 2005-12-27 2011-11-30 イビデン株式会社 多層プリント配線板
US7462784B2 (en) * 2006-05-02 2008-12-09 Ibiden Co., Ltd. Heat resistant substrate incorporated circuit wiring board
AT9551U1 (de) * 2006-05-16 2007-11-15 Austria Tech & System Tech Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil
JP5068060B2 (ja) * 2006-10-30 2012-11-07 新光電気工業株式会社 半導体パッケージおよびその製造方法
US8455766B2 (en) * 2007-08-08 2013-06-04 Ibiden Co., Ltd. Substrate with low-elasticity layer and low-thermal-expansion layer
JP5085266B2 (ja) * 2007-10-12 2012-11-28 富士通株式会社 配線基板およびその製造方法
JP5105378B2 (ja) * 2007-12-26 2012-12-26 パナソニック株式会社 半導体装置および多層配線基板
JP2009224492A (ja) * 2008-03-14 2009-10-01 Oki Semiconductor Co Ltd 半導体装置及びその製造方法
JP5284155B2 (ja) * 2008-03-24 2013-09-11 日本特殊陶業株式会社 部品内蔵配線基板
US8178976B2 (en) * 2008-05-12 2012-05-15 Texas Instruments Incorporated IC device having low resistance TSV comprising ground connection
US8304915B2 (en) * 2008-07-23 2012-11-06 Nec Corporation Semiconductor device and method for manufacturing the same
JP5350745B2 (ja) * 2008-10-21 2013-11-27 新光電気工業株式会社 配線基板
US8186053B2 (en) * 2008-11-14 2012-05-29 Fujitsu Limited Circuit board and method of manufacturing the same
TWI384603B (zh) * 2009-02-17 2013-02-01 日月光半導體製造股份有限公司 基板結構及應用其之封裝結構
US8395054B2 (en) * 2009-03-12 2013-03-12 Ibiden Co., Ltd. Substrate for mounting semiconductor element and method for manufacturing substrate for mounting semiconductor element
US8829355B2 (en) * 2009-03-27 2014-09-09 Ibiden Co., Ltd. Multilayer printed wiring board
US7936060B2 (en) * 2009-04-29 2011-05-03 International Business Machines Corporation Reworkable electronic device assembly and method
JP5249132B2 (ja) * 2009-06-03 2013-07-31 新光電気工業株式会社 配線基板
JP5532744B2 (ja) * 2009-08-20 2014-06-25 富士通株式会社 マルチチップモジュール及びマルチチップモジュールの製造方法
US8466562B2 (en) * 2009-09-24 2013-06-18 Headway Technologies, Inc. Layered chip package
JP5290215B2 (ja) * 2010-02-15 2013-09-18 ルネサスエレクトロニクス株式会社 半導体装置、半導体パッケージ、インタポーザ、及びインタポーザの製造方法
JP5115578B2 (ja) * 2010-03-26 2013-01-09 Ｔｄｋ株式会社 多層配線板及び多層配線板の製造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
TWI460834B (zh) * 2010-08-26 2014-11-11 欣興電子股份有限公司 嵌埋穿孔晶片之封裝結構及其製法
TWI418269B (zh) * 2010-12-14 2013-12-01 欣興電子股份有限公司 嵌埋穿孔中介層之封裝基板及其製法
KR101767108B1 (ko) * 2010-12-15 2017-08-11 삼성전자주식회사 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법
TWI459520B (zh) * 2011-01-31 2014-11-01 精材科技股份有限公司 轉接板及其形成方法
US20120217049A1 (en) * 2011-02-28 2012-08-30 Ibiden Co., Ltd. Wiring board with built-in imaging device
TWI455268B (zh) * 2011-03-22 2014-10-01 南亞電路板股份有限公司 封裝載板及其製造方法
JP2012204831A (ja) * 2011-03-23 2012-10-22 Ibiden Co Ltd 電子部品内蔵配線板及びその製造方法
TWI421995B (zh) * 2011-04-27 2014-01-01 欣興電子股份有限公司 半導體封裝結構及其製法
GB201108425D0 (en) * 2011-05-19 2011-07-06 Zarlink Semiconductor Inc Integrated circuit package
US8829684B2 (en) 2011-05-19 2014-09-09 Microsemi Semiconductor Limited Integrated circuit package
TWI492680B (zh) * 2011-08-05 2015-07-11 欣興電子股份有限公司 嵌埋有中介層之封裝基板及其製法
US20130068516A1 (en) * 2011-09-19 2013-03-21 Tessera Research Llc High io substrates and interposers without vias
TWI476888B (zh) 2011-10-31 2015-03-11 欣興電子股份有限公司 嵌埋穿孔中介層之封裝基板及其製法
US11127664B2 (en) 2011-10-31 2021-09-21 Unimicron Technology Corp. Circuit board and manufacturing method thereof
US20130215586A1 (en) * 2012-02-16 2013-08-22 Ibiden Co., Ltd. Wiring substrate
US9236322B2 (en) * 2012-04-11 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for heat spreader on silicon
FR2991108A1 (fr) * 2012-05-24 2013-11-29 St Microelectronics Sa Ligne coplanaire blindee
US8901435B2 (en) 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
TWM455979U (zh) * 2012-09-21 2013-06-21 Chunghwa Prec Test Tech Co Ltd 微小間距測試載板結構
TWI483365B (zh) * 2012-09-26 2015-05-01 財團法人工業技術研究院 封裝基板及其製法
TWI543307B (zh) 2012-09-27 2016-07-21 欣興電子股份有限公司 封裝載板與晶片封裝結構
TWI499023B (zh) * 2012-10-11 2015-09-01 財團法人工業技術研究院 封裝基板及其製法
CN103779284A (zh) * 2012-10-22 2014-05-07 欣兴电子股份有限公司 封装载板与芯片封装结构
TWI544599B (zh) * 2012-10-30 2016-08-01 矽品精密工業股份有限公司 封裝結構之製法
US10032696B2 (en) 2012-12-21 2018-07-24 Nvidia Corporation Chip package using interposer substrate with through-silicon vias
US9312219B2 (en) * 2012-12-28 2016-04-12 Dyi-chung Hu Interposer and packaging substrate having the interposer
TWI503934B (zh) * 2013-05-09 2015-10-11 日月光半導體製造股份有限公司 半導體元件及其製造方法及半導體封裝結構
US8836098B1 (en) * 2013-05-15 2014-09-16 Freescale Semiconductor, Inc. Surface mount semiconductor device with solder ball reinforcement frame
TWI512923B (zh) * 2013-06-18 2015-12-11 矽品精密工業股份有限公司 中介板及其製法
JP6161437B2 (ja) * 2013-07-03 2017-07-12 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ
KR102192356B1 (ko) * 2013-07-29 2020-12-18 삼성전자주식회사 반도체 패키지
AT515069B1 (de) * 2013-11-07 2019-10-15 At & S Austria Tech & Systemtechnik Ag Leiterplattenstruktur
KR102155740B1 (ko) * 2014-02-21 2020-09-14 엘지이노텍 주식회사 인쇄회로기판 및 이의 제조 방법
JP2016021496A (ja) * 2014-07-15 2016-02-04 イビデン株式会社 配線基板及びその製造方法
CN105590914B (zh) * 2014-10-24 2018-04-06 碁鼎科技秦皇岛有限公司 电子元件封装结构及制作方法
US10306777B2 (en) * 2014-12-15 2019-05-28 Bridge Semiconductor Corporation Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same
US9818684B2 (en) * 2016-03-10 2017-11-14 Amkor Technology, Inc. Electronic device with a plurality of redistribution structures having different respective sizes
US9659853B2 (en) 2015-04-24 2017-05-23 Advanced Semiconductor Engineering, Inc. Double side via last method for double embedded patterned substrate
JP6550260B2 (ja) * 2015-04-28 2019-07-24 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP6657609B2 (ja) * 2015-06-12 2020-03-04 凸版印刷株式会社 配線回路基板、半導体装置、配線回路基板の製造方法および半導体装置の製造方法
TW201701429A (zh) * 2015-06-24 2017-01-01 華亞科技股份有限公司 晶圓級封裝及其製作方法
KR102150555B1 (ko) 2015-08-12 2020-09-01 삼성전기주식회사 방열부재 및 이를 구비한 인쇄회로기판
KR102498627B1 (ko) * 2015-10-05 2023-02-10 엘지이노텍 주식회사 인쇄회로기판 및 이를 포함하는 전자 부품 패키지
US9735079B2 (en) * 2015-10-08 2017-08-15 Dyi-chung Hu Molding compound wrapped package substrate
CN105436645A (zh) * 2015-12-07 2016-03-30 天津平高智能电气有限公司 一种用于真空开关装配的钎焊方法
US10515899B2 (en) * 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10002852B1 (en) * 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
CN106783777A (zh) * 2016-12-26 2017-05-31 华进半导体封装先导技术研发中心有限公司 芯片封装结构及方法
US10178755B2 (en) * 2017-05-09 2019-01-08 Unimicron Technology Corp. Circuit board stacked structure and method for forming the same
US10685922B2 (en) 2017-05-09 2020-06-16 Unimicron Technology Corp. Package structure with structure reinforcing element and manufacturing method thereof
US10950535B2 (en) 2017-05-09 2021-03-16 Unimicron Technology Corp. Package structure and method of manufacturing the same
TWI683407B (zh) * 2017-05-23 2020-01-21 矽品精密工業股份有限公司 基板結構及其製法
US11101186B2 (en) * 2018-03-16 2021-08-24 Advanced Semiconductor Engineering, Inc. Substrate structure having pad portions
JP2019220504A (ja) 2018-06-15 2019-12-26 イビデン株式会社 インダクタ内蔵基板およびその製造方法
CN110875294B (zh) * 2018-08-29 2024-01-23 恒劲科技股份有限公司 半导体装置的封装结构及其制造方法
CN111599687B (zh) * 2019-02-21 2022-11-15 奥特斯科技(重庆)有限公司 具有高刚度的超薄部件承载件及其制造方法
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
DE102019107760A1 (de) 2019-03-26 2020-10-01 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur herstellung einer verbindungsstruktur und halbleiterbauelement
CN112216688A (zh) * 2019-07-11 2021-01-12 苏州旭创科技有限公司 一种载板及光模块
US11410934B2 (en) * 2020-04-16 2022-08-09 Advanced Semiconductor Engineering, Inc. Substrate and semiconductor device package and method for manufacturing the same
CN114007344B (zh) * 2020-07-28 2024-04-12 庆鼎精密电子（淮安）有限公司 内埋元件电路板的制作方法以及内埋元件电路板
US11355454B2 (en) * 2020-07-30 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and manufacturing method thereof
US12310032B2 (en) * 2021-06-08 2025-05-20 Intel Corporation Stacked backend memory with resistive switching devices
KR20240052980A (ko) * 2021-09-09 2024-04-23 어플라이드 머티어리얼스, 인코포레이티드 반도체 디바이스 패키지들을 위한 보강재 프레임
KR20230094341A (ko) 2021-12-21 2023-06-28 대덕전자 주식회사 패키지기판
WO2025102289A1 (zh) * 2023-11-16 2025-05-22 京东方科技集团股份有限公司 集成基板及其制备方法、电子设备

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284632A (ja) * 1997-04-08 1998-10-23 Fujitsu Ltd 回路基板及びその製造方法
JP2001044639A (ja) * 1999-05-27 2001-02-16 Hoya Corp 多層プリント配線板及びその製造方法
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
JP2002344142A (ja) 2001-05-15 2002-11-29 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2003197811A (ja) * 2001-12-27 2003-07-11 Hitachi Ltd ガラス基板及びその製造方法、並びに配線基板、半導体モジュール
US20030155638A1 (en) 2002-02-01 2003-08-21 Nec Toppan Circuit Solutions, Inc. Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device
US20040160751A1 (en) 1999-09-02 2004-08-19 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
US20050136634A1 (en) 2003-12-17 2005-06-23 Sergey Savastiouk Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US20060076659A1 (en) 2004-10-13 2006-04-13 Chih-Ming Chung Chip package structure, package substrate and manufacturing method thereof
EP1761119A1 (en) 2005-09-01 2007-03-07 Ngk Spark Plug Co., Ltd Ceramic capacitor

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4665468A (en) * 1984-07-10 1987-05-12 Nec Corporation Module having a ceramic multi-layer substrate and a multi-layer circuit thereupon, and process for manufacturing the same
JP2996510B2 (ja) * 1990-11-30 2000-01-11 株式会社日立製作所 電子回路基板
JPH11317582A (ja) * 1998-02-16 1999-11-16 Matsushita Electric Ind Co Ltd 多層配線基板およびその製造方法
JPH11289025A (ja) * 1998-04-01 1999-10-19 Ngk Spark Plug Co Ltd ビルドアップ多層配線基板
JP2000183532A (ja) 1998-12-16 2000-06-30 Ibiden Co Ltd プリント配線板
JP3761862B2 (ja) 1999-05-27 2006-03-29 Ｈｏｙａ株式会社 両面配線板の製造方法
JP3585793B2 (ja) * 1999-11-09 2004-11-04 富士通株式会社 両面薄膜配線基板の製造方法
JP3796099B2 (ja) 2000-05-12 2006-07-12 新光電気工業株式会社 半導体装置用インターポーザー、その製造方法および半導体装置
JP2002290030A (ja) * 2001-03-23 2002-10-04 Ngk Spark Plug Co Ltd 配線基板
JP3612031B2 (ja) 2001-03-29 2005-01-19 Ｔｄｋ株式会社 高周波モジュール
JP2003174250A (ja) 2001-09-28 2003-06-20 Ibiden Co Ltd プリント配線板及びプリント配線板の製造方法
US7091589B2 (en) * 2002-12-11 2006-08-15 Dai Nippon Printing Co., Ltd. Multilayer wiring board and manufacture method thereof
JP2004228521A (ja) * 2003-01-27 2004-08-12 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
JP2005033195A (ja) 2003-06-20 2005-02-03 Ngk Spark Plug Co Ltd コンデンサ及びコンデンサの製造方法
JP2005039243A (ja) * 2003-06-24 2005-02-10 Ngk Spark Plug Co Ltd 中間基板
JP2005032905A (ja) 2003-07-10 2005-02-03 Ibiden Co Ltd 多層プリント配線板
KR100942400B1 (ko) 2004-01-30 2010-02-17 이비덴 가부시키가이샤 다층 프린트 배선판 및 그 제조 방법
CN100544558C (zh) 2004-04-28 2009-09-23 揖斐电株式会社 多层印刷配线板
CN100367491C (zh) * 2004-05-28 2008-02-06 日本特殊陶业株式会社 中间基板
JP4824397B2 (ja) 2005-12-27 2011-11-30 イビデン株式会社 多層プリント配線板
US7462784B2 (en) 2006-05-02 2008-12-09 Ibiden Co., Ltd. Heat resistant substrate incorporated circuit wiring board
US7843302B2 (en) 2006-05-08 2010-11-30 Ibiden Co., Ltd. Inductor and electric power supply using it
US8395054B2 (en) 2009-03-12 2013-03-12 Ibiden Co., Ltd. Substrate for mounting semiconductor element and method for manufacturing substrate for mounting semiconductor element
US8829355B2 (en) 2009-03-27 2014-09-09 Ibiden Co., Ltd. Multilayer printed wiring board

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10284632A (ja) * 1997-04-08 1998-10-23 Fujitsu Ltd 回路基板及びその製造方法
JP2001044639A (ja) * 1999-05-27 2001-02-16 Hoya Corp 多層プリント配線板及びその製造方法
US20040160751A1 (en) 1999-09-02 2004-08-19 Ibiden Co., Ltd. Printed circuit board and method of manufacturing printed circuit board
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
JP2002344142A (ja) 2001-05-15 2002-11-29 Ibiden Co Ltd 多層プリント配線板の製造方法
JP2003197811A (ja) * 2001-12-27 2003-07-11 Hitachi Ltd ガラス基板及びその製造方法、並びに配線基板、半導体モジュール
US20030155638A1 (en) 2002-02-01 2003-08-21 Nec Toppan Circuit Solutions, Inc. Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device
US20050136634A1 (en) 2003-12-17 2005-06-23 Sergey Savastiouk Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US20060076659A1 (en) 2004-10-13 2006-04-13 Chih-Ming Chung Chip package structure, package substrate and manufacturing method thereof
EP1761119A1 (en) 2005-09-01 2007-03-07 Ngk Spark Plug Co., Ltd Ceramic capacitor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2015623A4

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130104A (ja) * 2007-11-22 2009-06-11 Shinko Electric Ind Co Ltd 配線基板及び半導体装置及び配線基板の製造方法
JP2009141041A (ja) * 2007-12-05 2009-06-25 Shinko Electric Ind Co Ltd 電子部品実装用パッケージ
JP2010239126A (ja) * 2009-03-09 2010-10-21 Shinko Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
JP2012033777A (ja) * 2010-07-30 2012-02-16 Kyocer Slc Technologies Corp 配線基板
US9589857B2 (en) 2011-06-03 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US11682593B2 (en) 2011-06-03 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
JP2015097280A (ja) * 2011-06-03 2015-05-21 台湾積體電路製造股▲ふん▼有限公司Ｔａｉｗａｎ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｍｐａｎｙ，Ｌｔｄ． インターポーザ試験構造と方法
US10734295B2 (en) 2011-06-03 2020-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US10090213B2 (en) 2011-06-03 2018-10-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer test structures and methods
US9066435B2 (en) 2012-03-30 2015-06-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9565756B2 (en) 2012-03-30 2017-02-07 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9480157B2 (en) 2012-05-18 2016-10-25 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9035463B2 (en) 2012-05-18 2015-05-19 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9433085B2 (en) 2013-04-23 2016-08-30 Ibiden Co., Ltd. Electronic component, method for manufacturing the same and method for manufacturing multilayer printed wiring board
JP2015179795A (ja) * 2013-05-30 2015-10-08 京セラサーキットソリューションズ株式会社 配線基板
US9431347B2 (en) 2013-06-05 2016-08-30 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US9425159B2 (en) 2013-06-05 2016-08-23 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
US10304794B2 (en) 2014-06-18 2019-05-28 Dyi-chung Hu Manufacturing method of integrated circuit package
JP2016004999A (ja) * 2014-06-18 2016-01-12 ダイ−チュン フＤｙｉ−Ｃｈｕｎｇ ＨＵ Ｉｃパッケージ用高密度フィルム
US9699921B2 (en) 2014-08-01 2017-07-04 Fujikura Ltd. Multi-layer wiring board
US9723728B2 (en) 2014-08-04 2017-08-01 Ibiden Co., Ltd. Wiring board with built-in electronic component and method for manufacturing the same
JP2018093107A (ja) * 2016-12-06 2018-06-14 ルネサスエレクトロニクス株式会社 半導体装置
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
JP2019192886A (ja) * 2018-04-27 2019-10-31 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP7202785B2 (ja) 2018-04-27 2023-01-12 新光電気工業株式会社 配線基板及び配線基板の製造方法

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US7994432B2 (en) 2011-08-09
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US20090255716A1 (en) 2009-10-15
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