JP4353873B2 - プリント配線板 - Google Patents
プリント配線板 Download PDFInfo
- Publication number
- JP4353873B2 JP4353873B2 JP2004246651A JP2004246651A JP4353873B2 JP 4353873 B2 JP4353873 B2 JP 4353873B2 JP 2004246651 A JP2004246651 A JP 2004246651A JP 2004246651 A JP2004246651 A JP 2004246651A JP 4353873 B2 JP4353873 B2 JP 4353873B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- printed wiring
- wiring board
- solder
- stress relaxation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Description
前記複数の導体回路層のうち外層に最も近い外層導体回路層を覆うように形成され前記絶縁性樹脂よりも弾性率の低い材料からなる応力緩和層と、
前記応力緩和層を貫通する貫通孔と、
前記貫通孔の内壁に形成されたバリア層と該バリア層の内側に形成されたはんだ製の芯体とからなり前記外層導体回路層と前記電子部品とを電気的に接続する導体ポストと、
を備えたものである。
E={σVS 2(3VL 2−4VS 2)}/(VL 2−VS 2)
Claims (7)
- コア基板の少なくとも片面に導体回路層と絶縁層とが交互に形成され各導体回路層間が前記絶縁層を貫通するスルーホール導体又はバイアホールを介して電気的に接続されると共に実装面に実装される電子部品が前記導体回路層と電気的に接続されるプリント配線板であって、
前記複数の導体回路層のうち外層に最も近い外層導体回路層を覆うように形成され前記絶縁性樹脂よりも弾性率の低い材料からなる応力緩和層と、
前記応力緩和層を貫通する貫通孔と、
前記貫通孔の内壁に形成されたバリア層と該バリア層の内側に形成されたはんだ製の芯体とからなり前記外層導体回路層と前記電子部品とを電気的に接続する導体ポストと、
を備えたプリント配線板。 - 前記導体ポストは、アスペクト比が1.5以上である、請求項1に記載のプリント配線板。
- 前記芯体は、超音波探傷法によるヤング率が40GPa以上70GPa未満のはんだからなる、請求項1又は2に記載のプリント配線板。
- 前記芯体は、Sn,Ag,Cu,In,Bi及びZnからなる群より選ばれる少なくとも2種の金属からなる鉛フリーはんだからなる、請求項1〜3のいずれかに記載のプリント配線板。
- 前記バリア層は、厚みが0.03〜5μmである、請求項1〜4のいずれかに記載のプリント配線板。
- 前記バリア層は、Cu,Au,Pd,Ni−Au,Ni−Pd−Au及びNi−Pdからなる群より選ばれた金属からなる、請求項1〜5のいずれかに記載のプリント配線板。
- 前記応力緩和層は、JIS K7113に準拠して測定したヤング率が10MPa〜1GPaである、請求項1〜6のいずれかに記載のプリント配線板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004246651A JP4353873B2 (ja) | 2004-08-26 | 2004-08-26 | プリント配線板 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004246651A JP4353873B2 (ja) | 2004-08-26 | 2004-08-26 | プリント配線板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006066597A JP2006066597A (ja) | 2006-03-09 |
JP4353873B2 true JP4353873B2 (ja) | 2009-10-28 |
Family
ID=36112802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004246651A Active JP4353873B2 (ja) | 2004-08-26 | 2004-08-26 | プリント配線板 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4353873B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT9551U1 (de) | 2006-05-16 | 2007-11-15 | Austria Tech & System Tech | Verfahren zum festlegen eines elektronischen bauteils auf einer leiterplatte sowie system bestehend aus einer leiterplatte und wenigstens einem elektronischen bauteil |
JP5541157B2 (ja) * | 2008-06-12 | 2014-07-09 | 日本電気株式会社 | 実装基板、及び基板、並びにそれらの製造方法 |
JP2010157690A (ja) * | 2008-12-29 | 2010-07-15 | Ibiden Co Ltd | 電子部品実装用基板及び電子部品実装用基板の製造方法 |
JP5490525B2 (ja) * | 2009-12-28 | 2014-05-14 | 日本シイエムケイ株式会社 | 部品内蔵型多層プリント配線板及びその製造方法 |
KR101278426B1 (ko) * | 2010-09-02 | 2013-06-24 | 삼성전기주식회사 | 반도체 패키지 기판의 제조방법 |
JP2012151509A (ja) * | 2012-05-01 | 2012-08-09 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法、半導体パッケージ |
JP7354550B2 (ja) | 2019-02-08 | 2023-10-03 | 富士電機株式会社 | 半導体モジュールの外部接続部、半導体モジュール、外部接続端子、および半導体モジュールの外部接続端子の製造方法 |
-
2004
- 2004-08-26 JP JP2004246651A patent/JP4353873B2/ja active Active
Also Published As
Publication number | Publication date |
---|---|
JP2006066597A (ja) | 2006-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4504975B2 (ja) | 多層プリント配線板 | |
JP4504925B2 (ja) | 多層プリント配線板及びその製造方法 | |
US8610001B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
JP4673207B2 (ja) | 多層プリント配線板およびその製造方法 | |
JP2010153863A (ja) | プリント配線板及びプリント配線板の製造方法 | |
JP2010232636A (ja) | 多層プリント配線板 | |
WO2006046510A1 (ja) | 多層プリント配線板及び多層プリント配線板の製造方法 | |
WO2005081312A1 (ja) | 半導体搭載用基板 | |
US20100108371A1 (en) | Wiring board with built-in electronic component and method for manufacturing the same | |
JPWO2008053833A1 (ja) | 多層プリント配線板 | |
WO2007129545A1 (ja) | 耐熱性基板内蔵回路配線板 | |
JP2006032887A (ja) | 受動素子チップ内蔵型の印刷回路基板の製造方法 | |
JP2001217550A (ja) | 多層回路基板および半導体装置 | |
JP2001036253A (ja) | 多層配線回路基板及びその製造方法 | |
JP4022405B2 (ja) | 半導体チップ実装用回路基板 | |
JP4353873B2 (ja) | プリント配線板 | |
JP4376891B2 (ja) | 半導体モジュール | |
JP2008091377A (ja) | プリント配線基板及びその製造方法 | |
JP2012074487A (ja) | 半導体パッケージの製造方法 | |
JP6107021B2 (ja) | 配線基板の製造方法 | |
JP2002271040A (ja) | 多層プリント配線板の製造方法 | |
JP2001217356A (ja) | 多層回路基板および半導体装置 | |
KR101109287B1 (ko) | 전자부품 내장형 인쇄회로기판 및 그 제조방법 | |
JP2005136042A (ja) | 配線基板及び電気装置並びにその製造方法 | |
KR101523840B1 (ko) | 프린트 배선판 및 프린트 배선판의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070717 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090630 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090707 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090728 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4353873 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120807 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120807 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130807 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |