USRE41242E1 - Package substrate - Google Patents

Package substrate Download PDF

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Publication number
USRE41242E1
USRE41242E1 US10/850,584 US85058498A USRE41242E US RE41242 E1 USRE41242 E1 US RE41242E1 US 85058498 A US85058498 A US 85058498A US RE41242 E USRE41242 E US RE41242E
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US
United States
Prior art keywords
board
package board
layer
soldering
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/850,584
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English (en)
Inventor
Motoo Asai
Yoji Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP9303694A external-priority patent/JPH11121932A/ja
Priority claimed from JP31268697A external-priority patent/JP3126330B2/ja
Priority claimed from JP09312687A external-priority patent/JP3126331B2/ja
Priority claimed from JP34381597A external-priority patent/JP3378185B2/ja
Priority claimed from JP36194797A external-priority patent/JP3188863B2/ja
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to US10/850,584 priority Critical patent/USRE41242E1/en
Application granted granted Critical
Publication of USRE41242E1 publication Critical patent/USRE41242E1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

  • the present invention relates to a package board on which an IC chip is to be mounted, more particularly, a package board provided with soldering pads on its top and bottom surfaces.
  • the soldering pads are connected to the IC chip, as well as to boards such as a mother board, a sub-board, etc.
  • FIG. 23 is a. cross sectional view of the package board 600 provided with an IC chip 80 and mounted on a mother board 90 .
  • the package board 600 includes conductor circuits 658 A and 658 B formed on both surfaces of its core board 630 . Furthermore, conductor circuits 658 C and 658 D are formed in the upper layer of the conductor circuits 658 A and 658 B with an interlaminar resin insulating layer 650 therebetween respectively. On the upper layer of the conductor circuits 658 C and 658 D is formed an interlaminar resin insulator 750 .
  • interlaminar resin insulating layer 650 In the interlaminar resin insulating layer 650 are formed via-holes 660 A and 660 B and in the interlaminar resin insulator 750 are formed via-holes 660 D and 660 C respectively.
  • soldering bumps 676 U On the top surface of the package board on which the IC chip 80 is mounted are formed soldering bumps 676 U connected to the pads 82 formed on the IC chip 80 side surface of the package board.
  • soldering bumps 676 D On the bottom surface of the package board 600 on which a sub-board 90 is mounted are formed soldering bumps 676 D connected to the pads 92 formed on the mother board 90 side surface of the package board 600 .
  • Each of the soldering bumps 676 U is formed on a soldering pad 675 U.
  • soldering bumps 676 D are formed on a soldering pad 675 D.
  • resin 84 is sealed in a clearance between the IC chip 80 and the package board 600 .
  • resin 94 is sealed in a clearance between the package board 600 and the mother board 90 .
  • the package board 600 is used to connect the highly integrated IC chip 80 to the mother board 90 .
  • the pads 82 formed on the IC chip 80 side surface are as small as 133 to 170 ⁇ m in diameter and the pads 92 formed on the mother board 90 side surface are as large as 600 ⁇ m in diameter. Consequently, the IC chip 80 cannot be attached directly to the mother board 90 . This is why the package board 600 is disposed between the IC chip 80 and the mother board 90 .
  • the package board 600 is formed so as to match both IC chip side soldering pads 675 U and mother board side soldering pads 675 D with both IC chip side pads 82 and mother board side pads 92 in size respectively. Consequently, the rate of the area occupied by the soldering pads 675 U on the IC chip side surface of the package board 600 differs from the rate of the area occupied by the soldering pads 675 D on the mother board side surface of the package board 600 .
  • both interlaminar resin insulator 650 and core board 630 are made of resin and the soldering pads 675 U and 675 D are made of a metallic material such as nickel.
  • the package board is warped toward the IC chip side sometimes. This is because of a difference in the rate of the area occupied by the soldering pads between 675 U on the IC chip side surface and 675 D on the mother board side surface of the package board 600 as described above.
  • the heat generated from the IC chip makes the package board expand and shrink repetitively, causing a difference of shrinkage factor between the resin portion and the metallic portion of those soldering pads. And, this results in warping of the package board 600 sometimes.
  • one of a plurality of conductor circuit layers is generally used as a ground layer or a power supply layer to reduce noise or for other purposes.
  • the ground layer (or the power supply layer) is connected to an external terminal via a wire.
  • wires 658 A and 658 B (conductor circuits) used as ground layers are formed on the upper layer of the board 630 .
  • the wiring (ground layer) 658 B is connected to the wiring 658 D-S through a via-hole 660 B and the wiring 658 D-S is connected to the soldering bump 676 U through a via-hole 660 D.
  • the wiring 658 D-S is apt to generate noise and the noise causes malfunctions in electric elements such as an IC chip connected to the multi-layer wiring board.
  • the multi-layer wiring board needs a space for wiring in itself and this makes it difficult to realize higher integrated printed wiring boards.
  • a package board generally includes capacitors therein used to reduce noise from signals transmitted between the IC chip and the mother board.
  • inner layer conductor circuits 658 A and 658 B provided on both surfaces of the core board 630 are used as a power supply layer and a ground layer, so that capacitors are formed between the core board 630 and the power supply layer and the ground layer respectively.
  • FIG. 24A is a top view of the inner conductor circuit layer 658 B formed on the top surface of the core board 630 .
  • a ground layer 638 G On the inner conductor circuit layer 658 B are formed a ground layer 638 G, as well as land-pads 640 for connecting the top layer to the bottom layer. And, around each of the land-pads 640 are formed an insulating buffer 642 .
  • Each of the land-pads 640 consists of a land 640 a of a through-hole 636 of the core board 630 shown in FIG. 23 , a pad 640 b connected to a via-hole 660 A going through the upper interlaminar resin insulating layer 650 , and a wire 640 c connecting the land 640 a to the pad 640 b.
  • the land 640 a is connected to the pad 640 b via the wiring 640 c. Consequently, the transmission path provided between the upper conductor layer and the lower conductor layer is longer so that the package board has confronted with problems that the signal transmission slows down and the connecting resistance increases.
  • a corner K is formed at a joint between the wiring 640 c and the land 640 a, as well as at a joint between the wiring 640 c and the pad 640 b respectively.
  • stress is concentrated on each of those corners K due to a difference of thermal expansivity between the core board 630 /interlaminar resin insulating layer 650 made of resin and the land pad 640 made of a metallic material (copper, etc.).
  • This causes a crack L 1 to be generated sometimes in the interlaminar resin insulating layer 650 as shown in FIG. 23 , resulting in breaking of a wire in the conductor circuit 658 D or the via-hole 660 D formed in the interlaminar resin insulating layer 650 .
  • FIG. 24B shows an expanded view (C direction) of both via-hole 660 D and soldering bump 675 D shown in FIG. 23.
  • a soldering bump 675 on which a soldering bump 676 D is mounted is formed circularly and connected to a circularly-formed via-hole 660 D through the wiring 678 .
  • the IC chip 80 repeats the heat cycle between high temperature during an operation and cooling down up to the room temperature at the end of an operation. Since the thermal expansivity differs significantly between the IC chip 80 made of silicon and the package board 600 made of resin, stress is generated in the package board in the heat cycle, causing a crack L 2 to be generated in the sealing resin 94 provided between the package board 600 and the mother board 90 . And, such a crack L 2 is extended thereby to disconnect the via-hole 660 D from the soldering bump 675 D of the package board 600 sometimes. In other words, as shown in FIG. 24C for an expanded view (D direction) of the via-hole 660 D and the soldering bump 675 shown in FIG. 23 , sometimes a crack L 2 causes breaking of the wiring 678 connecting the via-hole 660 D to the soldering bump 675 D on which the soldering bump 676 D is mounted.
  • the soldering pads on the IC chip side surface of the package board are small, so the rate of the metallic portion occupied by those soldering pads is also small.
  • the soldering pads on the mother board side surface of the package board are large, so the rate of the metallic portion occupied by those soldering pads is also large.
  • a dummy pattern is formed between conductor circuit patterns on the IC chip side surface of the package board thereby to increase the metallic portion and adjust the rate of the metallic portion between the IC chip side surface and the mother board side surface of the package board so as to protect the package board from warping.
  • the dummy pattern mentioned above does not have any functional meaning such as an electrical connection and a capacitor. It just means a pattern formed mechanically.
  • the soldering pads on the IC chip side surface of the package board are small.
  • the metallic portion occupied by the soldering pads is less than that of the mother board side surface of the package board, where the soldering pads are large and the metallic portion occupied by the soldering pads is large.
  • a dummy pattern is formed at the outer periphery of each conductor circuit on the IC chip side surface of the package board thereby to increase the metallic portion thereon and adjust the rate of the metallic portion on the package board surface between the IC chip side and the mother board side.
  • This metallic dummy pattern is also effective to improve the mechanical strength of the outer periphery of the package board, as well as protect the package board from warping.
  • a power supply layer and/or a ground layer is formed as an inner layer conductor circuit formed under an insulating layer that supports the outermost layer conductor circuits.
  • a via-hole is connected directly to the second conductor circuit and solder bump is formed in the via-hole. It is therefore not necessary to provide a wire for connecting the power supply layer or the ground layer to the soldering bumps. Consequently, the package board is free of any noise to be mixed in wires.
  • a power supply and/or a ground layer is formed as the second conductor circuit disposed under the second interlaminar resin insulating layer that supports the conductor circuits formed in the outermost layer.
  • a via-hole is connected directly to the second conductor circuit and a soldering bump is formed in the via-hole. It is therefore not necessary to provide a wire for connecting the power supply layer or the ground layer to the soldering bumps. Consequently, the package board is free of any noise to be mixed in wires.
  • each land and each pad are formed integrally and connected directly to each other without using a wire. It is thus possible to shorten the transmission path provided between upper and lower conductor layers, as well as to reduce the connecting resistance significantly.
  • the land and the pad are connected directly to each other without using a wire, no stress is concentrated at a joint between wiring and land, as well as at a joint between wiring and pad. It is thus possible to protect the package board from breaking of a wire to be caused by a crack generated by such concentrated stress.
  • a soldering bump is formed in a via-hole, so that each soldering bump is connected directly to a via-hole. Therefore, even when the package board is cracked, it is prevented that breaking of a wire occurs between the soldering bump and the via-hole.
  • the conventional package board where a soldering pad is connected to a via-hole through a wire and a soldering bump is formed on a soldering pad, cannot avoid crack-cased breaking of a wire connecting via-holes to soldering pads. A soldering bump is thus disconnected from a via-hole due to such a crack generated inside the package board.
  • the package board defined in this aspect of the invention is completely protected from breaking of a wire caused by such a crack.
  • a soldering bump is formed in a via-hole, so that each soldering bump is connected directly to each via-hole. It is thus possible to prevent breaking of a wire between a soldering bump and a via-hole even when the package board is cracked.
  • Such a soldering bump is also formed in a plurality of via-holes respectively in this case. It is possible to utilize a fail-safe, since the soldering bump can be connected to another via-hole when one of the via-holes is disconnected from the soldering bump. In addition, since a soldering bump is formed on a plurality of via-holes, a soldering bump can be formed larger to each via-hole.
  • FIG 1 is a cross sectional view of the package board in a first embodiment of the present invention.
  • FIG. 2 is an X 1 —X 1 line cross sectional view of the package board shown in FIG. 1 .
  • FIG. 3 to FIG. 9 illustrate manufacturing processes of the package board in the first embodiment of the present invention
  • FIG. 10 is a cross sectional view of the package board in a second embodiment of the present invention.
  • FIG. 11A is a top view of the package board in the second embodiment.
  • FIG. 11B is a bottom view of an IC chip.
  • FIG. 12 is a cross sectional view of the package board shown in FIG. 10 when the package board with an IC chip mounted thereon is attached to a mother board.
  • FIG. 13 is a cross sectional view of a multi-layer printed wiring board in a third embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of a configuration of a variation of the multi-layer printed wiring board in the third embodiment of the present invention.
  • FIG. 15 is a cross sectional view of the package board in the fourth embodiment of the present invention.
  • FIG. 16A is a top view of a core board of the package board in the fourth embodiment of the present invention. On the core board is formed an inner layer copper pattern.
  • FIG. 16B is an expanded partial top view of FIG. 16 A.
  • FIG. 17 is a cross sectional view of a package board composed as a variation of the package board in the fourth embodiment of the present invention.
  • FIG. 18A is a top view of a conductor circuit formed on a package board composed as a variation of the package board in the fourth embodiment of the present invention.
  • FIG. 18B is an expanded partial top view of FIG. 18 A.
  • FIG. 19 is a cross sectional view of the package board in a fifth embodiment of the present invention.
  • FIG. 20 is a cross sectional view of the package board shown in FIG. 19 when the package board with an IC chip mounted thereon is attached to a mother board.
  • FIG. 21 is a cross sectional view of a package board composed as a variation of the package board in the fifth embodiment, of the present invention.
  • FIG. 22 is an X 5 —X 5 line cross sectional view of the package board shown in FIG. 21 .
  • FIG. 23 is a cross sectional view of a prior art package board.
  • FIG. 24A is a top view of an inner layer conductor circuit shown in FIG. 23 .
  • FIG. 24B is a C-line view of FIG. 23 .
  • FIG. 24C is a D-line view of FIG. 23 .
  • FIG. 1 shows a cross sectional view of the package board in the first embodiment.
  • the package board in this first embodiment is a so-called IC package provided with an IC (not illustrated) mounted thereon and attached to a mother board (not illustrated).
  • the package board is provided with soldering bumps 76 U on its top surface and soldering bumps 76 D on its bottom surface.
  • Each of the soldering bumps 76 U is connected to a soldering bump of the IC and each of the soldering bumps 76 D is connected to a soldering bump of the mother board.
  • Both soldering bumps 76 U and 76 D are used to pass signals between the IC and the mother board, as well as relay a supply power from the mother board to other parts.
  • inner layer copper patterns 34 U and 34 D are used as ground layers.
  • a conductor circuit 58 U In the upper layer of the inner layer copper pattern 34 U is formed a conductor circuit 58 U, as well as a dummy pattern 58 M for forming a signal line with an interlaminar resin insulating layer 50 therebetween.
  • a via-hole 60 U is formed through the interlaminar resin insulating layer 50 .
  • a via-hole 160 U respectively with an interlaminar resin insulating layer 150 therebetween.
  • the via-hole 160 U goes through both outermost conductor circuit 158 U and interlaminar resin insulating layer 150 .
  • a soldering pad 75 U is formed both in the conductor circuit 158 U and in the via-hole 160 U.
  • the soldering pad 75 U is used to support a soldering bump 76 U.
  • Each IC chip side soldering pad 75 U is formed so as to be 133 to 170 ⁇ m in diameter.
  • a conductor circuit 58 D for forming a signal line with an interlaminar resin insulating layer 50 therebetween.
  • a via-hole 160 D through both an outermost layer conductor circuit 158 D and an interlaminar resin insulating layer 150 with an interlaminar resin insulating layer 150 therebetween.
  • a soldering pad 75 D is formed both in the conductor circuit 158 D and in the via-hole 160 D. The soldering pad 75 D is used to support a soldering bump 76 d.
  • Each mother board side soldering pad 75 D is formed so as to be 600 ⁇ m in diameter.
  • FIG. 2 shows an X 1 —X 1 line cross sectional view of FIG. 1 .
  • FIG. 2 shows a cross sectional view of the package board.
  • the X 1 —X 1 line cross sectional view in FIG. 2 is equal to FIG. 1 .
  • a dummy pattern 58 M is formed between conductor circuits 58 U forming signal lines.
  • a dummy pattern mentioned here means a pattern just formed mechanically; it has no functional meaning such as an electrical connection, a capacitor, etc.
  • each soldering pad disposed on the IC chip side surface is small (133 to 170 ⁇ m in diameter), so the metallic portion occupied by such soldering pads is also small.
  • each soldering pad is large (600 ⁇ m in diameter) on the mother board side surface (bottom) of the package board, a larger metallic portion is occupied by the soldering pads.
  • a dummy pattern 58 M is formed between conductor circuits 58 U forming a signal line respectively on the IC chip side surface of the package board thereby to increase the metallic portion and adjust the rate of the metallic portion on the surface of the package board between the IC chip side and the mother board side. It is thus possible to protect the package board from warping in the manufacturing processes to be described later, as well as during a usage of the package board.
  • This resin composition was obtained by mixing and stirring 35 weight parts of a resin solution obtained by dissolving 25% acrylic-modified cresol novolac epoxy resin (Nippon, Kayaku, molar weight 2500) in DMDG at a concentration of 80 wt %; 3.15 weight parts of photosensitive monomer (Toagosei, ARONIX M315); 0.5 weight part of an anti-forming agent (SANNOPCO, S-65); and 3.6 weight parts of NMP.
  • a resin solution obtained by dissolving 25% acrylic-modified cresol novolac epoxy resin (Nippon, Kayaku, molar weight 2500) in DMDG at a concentration of 80 wt %; 3.15 weight parts of photosensitive monomer (Toagosei, ARONIX M315); 0.5 weight part of an anti-forming agent (SANNOPCO, S-65); and 3.6 weight parts of NMP.
  • This resin composition was obtained by mixing 12 weight parts of polyether-sulfone (PES) ; 7.2 weight parts of epoxy resin particles (Sanyo Chemical Industries, Polymer Pole) 1.0 ⁇ m in average diameter; and 3.09 weight parts of the same epoxy resin particles 0.5 ⁇ m in average particle diameter; then adding 30 weight parts of NMP to the mixture and stirring the mixture using a beads mill.
  • PES polyether-sulfone
  • epoxy resin particles Sanyo Chemical Industries, Polymer Pole
  • This hardener composition was obtained by mixing and stirring 2 weight parts of an imidazole hardener (Shikoku Chemicals, 2E4MZ0CN); 2 weight parts of a photo-initiator (Ciba Geigy, Iracure I-907); 0.2 weight part of a photo-sensitizer (Nippon Kayaku, DETX-S); and 1.5 weight parts of NMP.
  • the resin composition (1) was obtained by mixing and stirring 35 weight parts of a resin solution obtained by dissolving 25% acrylated cresol novolac epoxy resin (Nippon Kayaku, molar weight 2500) into DMDG at a concentration of 80 wt %; 4 weight parts of photosensitive monomer (Toagosei, ARONIX M315); 0.5 weight part of an anti-forming agent (SANNOPCO, S-65); and 3.6 weight parts of NMP.
  • a resin solution obtained by dissolving 25% acrylated cresol novolac epoxy resin (Nippon Kayaku, molar weight 2500) into DMDG at a concentration of 80 wt %; 4 weight parts of photosensitive monomer (Toagosei, ARONIX M315); 0.5 weight part of an anti-forming agent (SANNOPCO, S-65); and 3.6 weight parts of NMP.
  • This resin composition (2) was obtained by mixing 12 weights part of polyether-sulfone (PES); 14.49 weight parts of epoxy resin particles (Sanyo Chemical Industries, Polymer Pole) 0.5 ⁇ m in average diameter; then adding 30 weight parts of NMP to the mixture and stirring the mixture using a beads mill.
  • PES polyether-sulfone
  • epoxy resin particles Sanyo Chemical Industries, Polymer Pole
  • This hardener composition (3) was obtained by mixing and stirring 2 weight parts of an imidazole hardener (Shikoku Chemicals, 2E4MZ0CN); 2 weight parts of a photo-initiator (Ciba Geigy, Irgacure I-907); 0.2 weight part of a photosensitizer (Nippon Kayaku, DETX-S); and 1.5 weight parts of NMP.
  • This composition (1) was obtained by mixing and stirring 100 weight parts of bisphenol F type epoxy monomer (Yuka Shell, molecular weight 310, YL983U); 170 weight parts of SiO 2 ball-like particles (Admatec, CRS 1101-CE, the maximum size of particles should be the thickness (15 ⁇ m) of the inner layer copper pattern to be described later) 1.6 ⁇ m in average diameter, when their surfaces are coated with a silane coupling agent; and 1.5 weight parts of a leveling agent (SANNOPCO, PERENOL S4); then adjusting the viscosity of the mixture to 45,000 to 49,000 cps at 23 ⁇ 1° C.
  • bisphenol F type epoxy monomer Yuka Shell, molecular weight 310, YL983U
  • Admatec SiO 2 ball-like particles
  • SANNOPCO leveling agent
  • This solder resist composition was obtained by mixing 46.67 g of photosensitive oligomer (molecular weight 4000) obtained by acrylic-modifying 50% of epoxy groups of 60 percentage by weight of cresol novolac dissolved into DMDG of 50% epoxy resin (Nippin Kayaku); 15.0 g of 80 percentage by weight of bisphenol A type epoxy resin (Yuka Shell, Epikote 1001) dissolved into methyl ethyl ketone; 1.6 g of imidazole hardener (Shikoku Chemicals, 2E4MZ-CN); 3 g of multivalent acrylic monomer (Nippon Kayaku, R604) which is photoreceptive monomer; 1.5 g of the same multivalent acrylic monomer (KYOEISHA CHEMICAL, DPE6A); 0.71 g of a scattering anti-foaming agent (SANNOPCO, S-65); then adding 2 g of benzophenone (KANTO CHEMICAL) used as a photoinitiator; and 0.2 g of Michler'
  • a rotor No.4 viscosity meter (Tokyo Keiki, DVL-B type) was used to measure the viscosity at 60 rpm and a rotor No.3 B type viscosity meter (Tokyo Keiki, DVL-B type) was used to measure the viscosity at 6 rpm.
  • a copper-clad laminate 30 A was obtained at first by laminating 18 ⁇ m copper foil 32 on both surfaces of a board 30 made of glass epoxy resin or BT (bismaleimide triazine) resin of 1 mm in thickness (process A in FIG. 3 ). After this, the copper-clad laminate 30 A was drilled to make holes, then electroless-plated and etched for patterning thereby to form inner layer copper patterns 34 U and 34 D on both surfaces of the board 30 and make through-holes 36 in the board 30 (process (B) in FIG. 3 )).
  • the board 30 was washed in water and dried. Then, the board was treated with oxidation-reduction using NaOH (10 g/l), NaClO2 (40 g/l), and Na3PO4 (6 g/l) as oxidation bathing (blackening bathing) agents and using NaOH (10 g/l) and NaBH4 (6 g/l) as reduction agents thereby to form a rough layer 38 on the surface of each of the inner layer copper patterns 34 U and 34 D, as well as the through-holes 36 (process (C) in FIG. 3 )).
  • the resin filler 40 obtained in (3) was coated on both surfaces of the board 30 within 24 hours after the manufacturing using a roll coating device thereby to fill a clearance between the conductor circuits (inner layer copper patterns) 34 U, as well as in the through-holes 36 .
  • the filler was then dried at 70° C. for 20 minutes.
  • the resin filler 40 was filled in a clearance between the conductor circuits 34 D or in the through-holes 36 and dried at 70° C. for 20 minutes (process (D) in FIG. 3 )).
  • one surface of the board 30 was sanded using a belt sanding machine and a #600 belt sand paper (Sankyo Rikagaku) to remove the resin filler 40 completely from the surfaces of both inner layer copper patterns 34 U and 34 D, as well as from the surface of the land 36 a of each through-hole 36 .
  • the surface of the board 30 was buffed to remove scratches made by the belt sanding.
  • Such a series of sanding was also carried out for the other surface of the board in the same way (process (E) in FIG. 4 )).
  • the resin filler 40 was hardened by baking at 100° C. for one hour, at 120° C. for three hours, at 150° C. for one hour, and at 180° C. for seven hours respectively.
  • the board 30 was alkaline-degreased for soft-etching, then the board 30 was treated with a catalyst solvent consisting of palladium chloride and organic acid thereby to add a Pd catalyst.
  • an electroless plating solvent consisting of 3.2 ⁇ 10 ⁇ 2 mol/l of copper sulfate, 3.9 ⁇ 10 ⁇ 3 mol/l of nickel sulfate, 5.4 ⁇ 10 ⁇ 2 mol/l of a complexing agent, 3.3 ⁇ 10 ⁇ 1 mol/l of sodium hydrophosphite, 5.0 10 ⁇ 1 mol/l of boracic acid,
  • the board 30 was vibrated in both vertical and horizontal directions once every 4 seconds thereby to form a needle-like alloy coating layer consisting of Cu—Ni—P and a rough layer 42 on the surfaces of each of the conductor circuits 34 , as well as on the surface of the land 36 a of each of the through-holes 36 (process (F)) in FIG. 4 ).
  • Both surfaces of the board obtained in (6) were coated with an interlaminar resin insulation material (for lower layers) 44 of 1.5 Pa•s in viscosity using a roll coating device within 24 hours after the solution was manufactured. Then, the board was left horizontally for 20 minutes, then dried (prebaking) at 60° C. for 30 minutes. After this, the board was coated with a sensitive binding solution 46 (for upper layers) of 7 Pa•s in viscosity obtained in (7) within 24 hours after the solution was manufactured, then the board was left horizontally for 20 minutes. Then, the board was dried (prebaking) at 60° C. for 30 minutes thereby to form a binding material layer 50 a of 35 ⁇ m in thickness (process (G) in FIG. 4 )).
  • a photo-masking film (not illustrated) provided with 85 ⁇ m ⁇ printed black circles was stuck fast to each surface of the board 30 on which a binding layer was formed respectively in (8), then exposed at 500 mJ/cm 2 using a super high voltage mercury lamp. A DMTG solution was then sprayed on the black circle for developing. Furthermore, the board 30 was exposed at 3000 mJ/cm 2 using a super high voltage mercury lamp, then heated (post-baking) at 100° C. for one hour, at 120° C. for one hour, and at 150° C. for 3 hours thereby to form an interlaminar resin insulating layer (two-layer structure) of 35 ⁇ m in thickness.
  • the layer was thus provided with 85 ⁇ m ⁇ openings (used to form via-holes), which were excellent in size accuracy, functioning equally to a photo-masking film (process (H) in FIG. 5 )).
  • the tinned layer (not illustrated) was partially exposed in each of the openings 48 to be used as via-holes.
  • a palladium catalyst (Atotech) was thus applied to the roughened surface (roughened depth 6 ⁇ m) of the board 30 to stick catalytic nuclei on the surface of the interlaminar resin insulating layer 50 , as well as the inner wall surface of each of the via-hole openings 48 .
  • the plating resist 54 was separated and removed with 5%KOH, then the electroless plated film 52 under the plating resist was melted and removed with etching treatment using a mixed solution of sulfuric acid and hydrogen peroxide thereby to form conductor circuits 58 U and 58 D for 18 ⁇ m in thickness respectively, as well as via-holes 60 U and 60 D consisting of an electroless copper plated film 52 and an electrolytic copper plated film 56 respectively (process (M) in FIG. 6 )).
  • the surface of the interlaminar resin insulating layer 150 was then roughened (process (P) in FIG. 7 )). After this, an electroless copper plated film 152 was formed on th roughened surface of the board 30 (process (Q) in FIG. 8 )). It was followed by forming of a plating resist 154 on the electroless copper plated film 152 , then by forming of an electrolytic copper plated film 156 on the no-resist-coated portion of the film 152 (process (R) in FIG. 8 )).
  • the plating resist 154 was then separated and removed with KOH, and the electroless plated film 152 under the plating resist 54 was melted and removed thereby to form conductor circuits 158 U and 158 D, as well as via-holes 160 U and 160 D (process (S) in FIG. 8 )). Then, a roughened layer 162 was formed on the roughened surface 162 form on the surfaces of the conductor circuits 158 and the via-holes 160 (process (T) in FIG. 9 )). No Sn displacement was carried out for the roughened surface 162 at this time.
  • Both surfaces of the board 30 obtained in (16) were coated with a solder resist composition 70 a described in D at a thickness of 45 ⁇ m.
  • the board 30 was then dried at 70° C. for 20 minutes, then at 70° C. for 30 minutes. After this, a photo-masking film (not illustrated) of 4 mm in thickness on which circles (masking pattern) were drawn was stuck fast to both surfaces of the board 30 respectively, then exposed with an ultraviolet beam of 1000 mJ/cm 2 and developed with DMTG.
  • the board 30 was baked at 80° C. for 1 hour, at 120° C. for 1 hour, and at 150° C. for 3 hours thereby to form a solder resist layer (20 ⁇ m thick) provided with an opening (200 ⁇ m diameter) 71 at each soldering pad (including the via-hole and its land) (process (U) in FIG. 9 )).
  • the electroless nickel plating solution consisted of 2.31 ⁇ 10 ⁇ 1 mol/l of nickel chloride, 2.8 ⁇ 10 ⁇ 1 mol/l of sodium hydrophosphite, and 1.85 ⁇ 10 ⁇ 1 mol/l of sodium citrate.
  • the board 30 was then dipped in an electroless gold plating solution for 7 minutes 20 seconds at 80° C.
  • the electroless gold plating solution consisted of 4.1 ⁇ 10 ⁇ 2 mol/l of gold potassium cyanide, 1.87 ⁇ 10 ⁇ 1 mol/l of ammonium chloride, 1.16 ⁇ 10 ⁇ 1 mol/l of sodium citrate, and 1.7 ⁇ 10 ⁇ 1 mol/l of sodium hydrophosphite.
  • soldering paste was printed in the opening 71 of the solder resist layer 70 and reflowed at 200° C. thereby to form soldering bumps (soldering bodies) 76 U and 76 D. This completed manufacturing of the package board 10 (see FIG. 1 ).
  • the configuration of the present invention may also apply to a package board to be formed with the full-additive process, of course.
  • a dummy pattern 58 M is formed between conductor circuits 58 U formed between the interlaminar resin insulating layer 50 and the interlaminar resin insulating layer 150 in the first embodiment, such a dummy pattern 58 M may also be formed between the inner layer copper patterns 34 D formed on the core board 30 or between outermost layer conductor circuits 158 U.
  • a dummy pattern is formed between conductor circuits that form signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the IC chip side surface of the package board and adjust the rate of the metallic portion between the IC chip side and the mother board side on the package board. It is thus possible to protect the package board from warping in the manufacturing processes, as well as during operation.
  • FIG. 10 is a cross sectional view of the package board in the second embodiment.
  • FIG. 11A is a top view of the package board and
  • FIG. 11B is a bottom view of an IC chip mounted on the package board.
  • FIG. 12 illustrates how the IC chip 80 is mounted on the top of the package board shown in FIG. 10 as a cross sectional view of the package board mounted on a mother board 90 .
  • the package board is provided with soldering bumps 76 U on its top surface and soldering bumps 76 D on the bottom surface as shown in FIG. 12 .
  • Those bumps are connected to the bumps 82 of the IC chip 80 and the bumps 92 of the mother board 90 respectively. Those bumps are used to pass signals between the IC chip 80 and the mother board 90 , as well as relay a supply power from the mother board to other parts.
  • inner layer core patterns 34 U and 34 D are used as ground layers.
  • inner layer core patterns 34 U and 34 D are used as ground layers.
  • a conductor circuit 58 U for forming a signal line with an interlaminar resin insulating layer 50 therebetween and a via-hole 60 U through the interlaminar resin insulating layer 50 .
  • the outermost layer conductor circuits 158 U with an interlaminar resin insulating layer 150 therebetween, as well as via-holes 160 U through both a dummy pattern 159 and an interlaminar resin insulating layer 150 are formed in the upper layer of the conductor circuit 58 U.
  • the dummy pattern 159 is formed at the outer periphery of each of the conductor circuits 158 U as shown in FIG. 11 , that is, along the circumference of the package board.
  • a soldering pad 75 U for supporting a soldering bump 76 U.
  • the soldering pads 75 U on the IC chip side surface are formed so as to be 120 to 170 ⁇ m in diameter.
  • conductor circuits 58 D for forming signal lines with the interlaminar resin insulating layer 50 therebetween.
  • a soldering pad 75 D for supporting a soldering bump 76 D.
  • the soldering pads 75 D on the mother board side surface are formed so as to be 600 to 700 ⁇ m in diameter.
  • FIG. 11A is a top view of the package board 200 , that is, an A-line view of FIG. 10 .
  • FIG. 10 is equal to the X 2 —X 2 line vertical cross sectional view of FIG. 11 A.
  • a 10 mm-wide dummy pattern 159 As shown in FIG. 11 A and FIG. 10 , at the outer periphery of each of the conductor circuits 158 U for forming signal lines on the lower layer of the solder resist 70 is formed a 10 mm-wide dummy pattern 159 .
  • the dummy pattern mentioned here means a pattern formed just mechanically; it has no functional meaning such as an electric connection, capacitor, etc.
  • the IC chip 80 side (top) surface of the package board is provided with smaller soldering pads 76 U (120 to 170 ⁇ m in diameter), so the metallic portion occupied by those soldering pads on the surface of the package board is also small.
  • the mother board 90 side (bottom) surface of the package board is provided with larger soldering pads 75 D (600 to 700 ⁇ m in diameter), so the metallic portion occupied by those soldering pads on the surface of the package board is also large.
  • the package board in this embodiment forms a dummy pattern 159 at the outer periphery of each of the outermost layer conductor circuits 158 U on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side on the surface of the package board.
  • the dummy patterns 159 are also effective to improve the mechanical strength of the circumference of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.
  • FIG. 11A shows a top view (A-line view of FIG. 10 ) of a completed package board and FIG. 11B shows a bottom view of an IC chip.
  • the package board 100 while the IC chip 80 is put thereon, is passed through a reflowing oven to fix the IC chip on the package board through the soldering bumps 76 U as shown in FIG. 12 .
  • the package board 100 with the IC chip mounted thereon is mounted on a mother board 90 , then passed in a reflowing oven thereby to fix the package board on the mother board 90 .
  • a dummy pattern 159 is formed around each of the outermost layer conductor circuits 158 U formed on the interlaminar resin insulating layer 150 .
  • the dummy pattern 159 may also be formed around each conductor circuit 58 U formed between inner layer copper patterns 34 D or around each of the conductor circuits 58 U formed between the interlaminar resin insulating layers 50 and 150 .
  • a dummy pattern is formed around each conductor circuit on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC side and the mother board side on the surface of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.
  • the core board 30 of the package board 300 is provided with inner layer copper patterns 34 U used as signal lines and formed on its top surface, as well as inner layer copper patterns 34 D used as signal lines and formed on its bottom surface respectively.
  • inner layer copper patterns 34 U used as signal lines and formed on its top surface
  • inner layer copper patterns 34 D used as signal lines and formed on its bottom surface respectively.
  • a conductor circuit 58 U that forms a power supply layer with the interlaminar resin insulating layer 50 therebetween.
  • a soldering bump 76 U is formed in the via-hole 160 U.
  • the package board is composed in the third embodiment so that a soldering bump 76 U is formed on a via-hole 160 U connected to a conductor circuit 58 U that forms a power supply layer.
  • the power supply layer can thus be connected directly to an external bump (not illustrated).
  • a conductor circuit 58 D used as a ground layer is formed in the upper layer of a signal line (inner layer copper pattern) 34 D with the interlaminar resin insulating layer 50 therebetween on the bottom side of the core board 30 .
  • a soldering bump 76 D is formed on the via-hole 160 D.
  • the package board is composed in this embodiment so that a soldering bump 76 D is formed on a via-hole 160 D connected to a conductor circuit 58 D composing a ground layer.
  • the ground layer can thus be connected directly to an external bump (not illustrated).
  • the conductor circuits 58 U and 58 D disposed under the interlaminar resin insulating layer 150 supporting the conductor circuits 158 U and 158 D in the outermost layer are used as a power supply layer and a ground layer.
  • via-holes 160 U and 160 D are connected directly to the conductor circuits 58 U and 58 D, and soldering bumps 76 U and 76 D are formed in the via-hole respectively. Consequently, it is not necessary to connect any power supply layer or ground layer directly to soldering bumps. The package board is thus protected from noise mixed in wires.
  • the multi-layer printed wiring board (package board) can be packed more densely.
  • a conductor circuit 58 U is used as a power supply layer and a conductor circuit 58 D is used as a ground layer.
  • the conductor circuit 58 U or 58 D may be formed in the same layer together with other conductor circuits functioning as a power supply layer and a ground layer respectively.
  • FIG. 14 is a cross sectional view of a configuration of the multi-layer printed wiring board in the second embodiment of the present invention.
  • inner layer copper patterns 234 U and 234 D used as ground layers.
  • capacitors are formed with the ground layers (inner layer copper patterns) 234 U and 234 D that face each other with the core board therebetween.
  • a conductor circuits 258 U that form signal lines with the interlaminar resin insulating layer 250 therebetween.
  • via-holes 360 U through the interlaminar resin insulating layer 350 .
  • soldering bump 376 U is formed on each of those via-holes 360 U.
  • a conductor circuit 258 D that forms a signal line with the interlaminar resin insulating layer 250 therebetween.
  • a conductor circuit 388 D used as a power supply layer with the interlaminar resin insulating layer 350 therebetwen.
  • a via-hole 380 D is formed in the upper layer of the conductor circuit 388 D through the interlaminar resin insulating layer 390 .
  • a soldering bump 376 D is formed in the via-hole 380 D.
  • a soldering bump 376 D is formed in a via-hole 380 D connected to a conductor circuit 388 D used as a power supply layer.
  • the power supply layer can thus be connected directly to an external bump (not illustrated).
  • a via-hole 380 D is connected directly to the conductor circuit 388 D used as a power supply layer and a soldering bump 376 D is formed in a via-hole. Consequently, it is not necessary to provide a wire for connecting the power supply layer to soldering bumps. It is thus possible to make the package board free of noise mixed in wires.
  • an inner layer conductor circuit formed in the lower layer of the insulating layer supporting the conductor circuits formed in the outermost layer is used as a power supply layer and/or a ground layer, and a via-hole is connected directly to a second conductor circuit and a soldering bump is formed in each of those via-holes.
  • the package board can therefore eliminate a wire for connecting the power supply layer or the ground layer to soldering bumps. Consequently, it is possible to make the package board free of noise mixed in wires.
  • the wiring-eliminated space can be used to pack the multi-layer printed wiring board in a higher density.
  • a second conductor circuit formed under the second interlaminar resin insulating layer supporting the outermost layer conductor circuits is used as a power supply layer or a ground layer, and a via-hole is connected directly to the second conductor circuit and a soldering bump is formed on the via-hole.
  • the package board can thus eliminate a wire for connecting the power supply layer or the ground layer to soldering bumps. Consequently, it is possible to make the package board free of noise mixed in wires.
  • the wiring-eliminated space can be used to pack the multi-layer printed wiring board more densely.
  • inner layer copper patterns 34 U and 34 D used as a ground layer respectively.
  • a conductive circuit 58 U that forms a signal line with an interlaminar resin insulating layer 50 therebetween, as well as a via-hole 60 U through the interlaminar resin insulating layer 50 .
  • soldering pad 75 U for supporting a soldering bump 76 U is formed on the conductor circuit 158 U and the via-hole 160 U respectively.
  • soldering pads 75 U on the IC chip side surface of the package board is formed so as to be 133 to 170 ⁇ m in diameter.
  • a conductor circuit 58 D that forms a signal line with the interlaminar resin insulating layer 50 therebetween.
  • a soldering pad 75 D for supporting a soldering bump 76 D is formed on the conductor circuit 158 D and the via-hole 160 D respectively.
  • Each of those soldering pads 75 D on this mother board side surface of the package board is formed so as to be 600 ⁇ m in diameter.
  • a ground (electrode) layer is formed on each of the inner layer copper patterns 34 U and 34 D that face each other with the core board 30 therebetween, so that a capacitor is formed with those inner layer copper patterns 34 U and 34 D.
  • FIG. 16A is a top view of an inner layer copper pattern 34 U formed on the top surface of the core board 30 .
  • On this inner layer copper pattern 34 U are formed a ground layer 34 G and land-pads 41 used to connect the upper layer to the lower layer respectively.
  • FIG. 16B shows an expanded land-pad 41 formed in the B area in FIG. 16 A.
  • the X 3 —X 3 line cross sectional view in FIG. 16B is equal to the X 3 —X 3 line cross sectional view in FIG. 15 .
  • each land-pad 41 is a combination of the land 41 a of a through-hole 36 shown in FIG. 15 and a pad 41 b connected to a via-hole 60 U that goes through the upper interlaminar resin insulating layer 50 .
  • an insulating buffer 43 of about 200 ⁇ m in width.
  • a land 41 a is united with a pad 41 b as shown in FIG. 16B , so that the land 41 a is connected directly to the pad 41 b without using a wire. It is thus possible to shorten the transmission path between the lower layer (the conductor circuit 58 D) and the upper conductor wiring 58 U in the upper layer (the interlaminar resin insulating layer 50 ) thereby to speed up the signal transmission, as well as reduce the connection resistance.
  • the land 41 a is connected directly to the pad 41 b without using a wire, no stress is concentrated between a wire and a land or between a wire and a pad.
  • the package board is thus protected completely from breaking of a wire caused by a crack generated by concentrated stress at such a place, although the package board manufactured with the prior art technology described above with reference to FIG. 24A has confronted with such a problem. And, although a description was made for only the inner layer copper pattern 34 U formed on the top surface of the core board 30 , the inner layer copper pattern 34 D on the bottom surface of the core board 30 is also composed in the same way.
  • the ground layer (electrode layer) 34 G and the land-pad 41 are formed on the inner layer copper patterns 34 U and 34 D formed on both top and bottom surfaces of the core board 30 .
  • the power supply layer (electrode layer) 58 G and the land-pad 61 are formed on the conductor circuits 58 U and 58 D formed in the upper layer of the interlaminar resin insulating layer 50 as shown in FIG. 16 A.
  • FIG. 17 is a cross sectional view of the package board composed as a variation of the fourth embodiment.
  • FIG. 18A is a top view of the conductor circuit 58 U formed on the top surface of the interlaminar resin insulating layer 50 . On this conductor circuit 58 U are formed a power supply layer 58 G, as well as land-pads 61 used to connect the upper layer to the lower layer respectively.
  • FIG. 18B shows an expanded land-pad 61 in the B area shown in FIG. 18 A.
  • the X 4 —X 4 line cross sectional view shown in FIG. 18B is equal to the X 4 -X 4 line cross sectional view shown in FIG. 17 .
  • each of those land-pads 61 is a combination of the land 61 a of a via-hole 60 U connected to an inner layer copper pattern 34 U and a pad 61 b connected to a via-hole 16 U going through the upper interlaminar resin insulating layer 150 .
  • an insulating buffer 63 of about 200 ⁇ m in width as shown in FIG. 18 B.
  • a land 61 a is united with a pad 61 b, so that the land 61 a is connected directly to the pad 61 b without using a wire.
  • the land 61 a is connected directly to the pad 61 b without using a wire, no stress is concentrated between a wire and a land or between a wire and a pad. The package board is thus protected completely from breaking of a wire caused by a crack generated by concentrated stress at such a place, although the package board manufactured with the prior art technology described above with reference to FIG. 24A has confronted with such a problem.
  • each circularly-formed land is united with a pad in the above embodiment, the land may be formed as an ellipse, a polygon, etc. and united with a pad in this invention.
  • each land is connected directly to a pad without using a wire. It is thus possible to shorten the transmission between the lower layer and each conductor wiring (conductor layer) formed in the upper layer, as well as to speed up the signal transmission and reduce the connection resistance.
  • each land is connected directly to a pad without using a wire, no stress is concentrated at a junction between wiring and land, as well as a junction between wiring and pad. The package board can thus be protected completely from breaking of a wire caused by a crack generated by concentrated stress at such a place.
  • FIG. 19 is a cross sectional view of the package board 500 in the fifth embodiment.
  • FIG. 20 shows how the package board 500 provided with an IC chip 80 mounted on its top surface thereof is mounted on a mother board 90 thereby to compose a so-called integrated circuit package.
  • inner layer copper patterns 34 U and 34 D used as ground layers.
  • a conductor circuit 58 U forming a signal line with an interlaminar resin insulating layer 50 therebetween, as well as a via-hole 60 U through the interlaminar resin insulating layer 50 .
  • soldering pad 75 U for supporting a soldering bump 76 U is formed on the conductor circuit 158 U and the via-hole 160 U respectively.
  • Each of the soldering pads 75 U on the IC chip side surface of the package board is formed so as to be 133 to 170 ⁇ m in diameter.
  • a conductor circuit 58 D forming a signal line with an interlaminar resin insulating layer 50 therebetween.
  • a soldering pad 75 D for supporting a soldering bump 76 D is formed in the via-hole 160 D.
  • Each of the soldering pads 75 D on the mother board side surface is formed so as to be 600 ⁇ m in diameter.
  • a soldering bump 76 D is formed on each via-hole 160 D on the mother board side surface 60 , so that the soldering bump is connected directly to the via-hole. Consequently, the package board is completely protected from breaking of a wire, otherwise to occur between the soldering bump 76 D and the via-hole 160 D if the package board is cracked.
  • each soldering pad 375 D is connected to a via-hole 360 through a wire 378 and a soldering bump 376 D is disposed on a soldering pad 375 D.
  • the crack L 2 breaks the wire 378 connecting the via-hole 376 D to the soldering pad 376 D.
  • the soldering bump 376 D can therefore be disconnected from the via-hole 360 D.
  • no breaking of a wire occurs between the soldering bump 376 D and the via-hole 160 D even when a crack is generated in the package board.
  • the IC chip 80 is mounted on the package board 500 in the fifth embodiment of the present invention shown in FIG. 19 .
  • the IC chip 80 is mounted on the package board 500 so that the soldering pads 82 of the IC chip 80 are aligned to the soldering bumps 76 U of the package board 500 .
  • the package board 500 with the IC chip 80 mounted thereon is passed through a heating oven thereby to weld the soldering pads 76 U to the soldering pads 82 .
  • the IC chip 80 is thus connected to the package board 500 .
  • the package board 500 is thus washed to remove the soldering flux seeped out when the soldering bumps 76 U are welded to and set up at the soldering pads 82 in the heating process.
  • an organic solution such as chlorothen is flown between the IC chip 80 and the package board 500 to remove the soldering flux. Resin is then filled between the IC chip 80 and the package board 500 to seal the portion.
  • the whole IC chip 80 is molded with resin at this time thereby to finish the mounting of the IC chip 80 on the package board 500 .
  • soldering pads 92 of the mother board 90 are aligned to the soldering bumps 76 D to mount the package board 500 on a mother board 90 .
  • the package board is passed through a heating oven to fuse the soldering pads 76 D to the soldering pads 92 .
  • the package board 500 is then connected to the mother board 90 .
  • resin 94 is filled in a clearance between the package board 500 and the mother board 90 as shown in FIG. 20 to seal the clearance. This completes the mounting of the package board 500 on the mother board 90 .
  • a soldering bump 76 D is formed on a via-hole 160 D.
  • a soldering bump 276 is formed on a plurality of (three) via-holes 260 as shown in FIG. 21 .
  • three via-holes 260 are formed closely to each other as shown in FIG. 22 , which is equal to the X 5 —X 5 line cross sectional view shown in FIG. 21 (the X 6 —X 6 line in FIG. 22 is equal to the X 5 —X 5 line in FIG. 21 ).
  • a nickel plated layer 72 and a gold plated layer 74 are formed respectively on a common land 260 a of the three via-holes 260 thereby to form one large land 275 .
  • a large soldering bump 276 is formed on the large land 275 .
  • a soldering bump 276 is formed on a plurality of via-holes 260 , so that the soldering bump 276 is connected directly to the via-holes 260 . Consequently, it is prevented that the soldering bump 276 is disconnected from the via-holes 260 , for example, even when the package board 501 is cracked.
  • the package board 501 can have a phase safe function. Because, when one of those via-holes 260 is disconnected from the inner layer conductor circuit 58 D, another via-hole 260 can keep the connection with the soldering bump 27 and the inner layer conductor circuit 58 D.
  • each soldering pad 75 U on the IC chip 80 side surface is formed so as to be 133 to 170 ⁇ m in diameter and each soldering pad 75 D on the mother board side surface is formed so as to be 600 ⁇ m in diameter.
  • soldering pad size 4 to 5 times between the IC chip side and the mother board side. It is thus difficult to form a large soldering pad 75 D on a via-hole like those formed on the mother board side surface.
  • a soldering bump 276 is formed on a plurality of (three) via-holes 260 , 260 , and 260 thereby to form such a large soldering bump.
  • one soldering bump is formed on three via-holes in this variation described above, it is also possible to form one soldering bump on two via-holes or on four or more via-holes.
  • a soldering bump is formed on a via-hole, so that the soldering bump is connected directly to the via-hole. This can prevent breaking of a wire even when the package board is cracked between the soldering bump and the via-hole.
  • the package board can have a phase safe function. Because, when one of the via-holes is disconnected from the soldering bump inside the package board, another via-hole can keep the connection with the soldering bump. And, since a soldering bump is formed on a plurality of via-holes, the soldering bump can be formed larger with respect to the via-hole.
  • the present invention also allows the package board to be connected to the mother board via a sub-board, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
US10/850,584 1997-10-17 1998-09-28 Package substrate Expired - Lifetime USRE41242E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/850,584 USRE41242E1 (en) 1997-10-17 1998-09-28 Package substrate

Applications Claiming Priority (13)

Application Number Priority Date Filing Date Title
JP9-303694 1997-10-17
JP9303694A JPH11121932A (ja) 1997-10-17 1997-10-17 多層配線板及び多層プリント配線板
JP9-312687 1997-10-29
JP31268697A JP3126330B2 (ja) 1997-10-29 1997-10-29 パッケージ基板
JP9-312686 1997-10-29
JP09312687A JP3126331B2 (ja) 1997-10-29 1997-10-29 パッケージ基板
JP9-343815 1997-11-28
JP34381597A JP3378185B2 (ja) 1997-11-28 1997-11-28 パッケージ基板
JP9-361947 1997-12-10
JP36194797A JP3188863B2 (ja) 1997-12-10 1997-12-10 パッケージ基板
US52959798A 1998-09-28 1998-09-28
US10/850,584 USRE41242E1 (en) 1997-10-17 1998-09-28 Package substrate
PCT/JP1998/004350 WO1999021224A1 (fr) 1997-10-17 1998-09-28 Substrat d'un boitier

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US52959798A Reissue 1997-10-17 1998-09-28

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USRE41242E1 true USRE41242E1 (en) 2010-04-20

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US09/529,597 Ceased US6392898B1 (en) 1997-10-17 1998-09-28 Package substrate
US10/850,584 Expired - Lifetime USRE41242E1 (en) 1997-10-17 1998-09-28 Package substrate
US09/905,973 Expired - Lifetime US6490170B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/905,974 Expired - Lifetime US6411519B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,076 Abandoned US20010054513A1 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,078 Expired - Lifetime US6487088B2 (en) 1997-10-17 2001-07-17 Package substrate
US10/876,287 Expired - Lifetime USRE41051E1 (en) 1997-10-17 2004-06-25 Package substrate

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US09/529,597 Ceased US6392898B1 (en) 1997-10-17 1998-09-28 Package substrate

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US09/905,973 Expired - Lifetime US6490170B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/905,974 Expired - Lifetime US6411519B2 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,076 Abandoned US20010054513A1 (en) 1997-10-17 2001-07-17 Package substrate
US09/906,078 Expired - Lifetime US6487088B2 (en) 1997-10-17 2001-07-17 Package substrate
US10/876,287 Expired - Lifetime USRE41051E1 (en) 1997-10-17 2004-06-25 Package substrate

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US (7) US6392898B1 (de)
EP (4) EP1895586A3 (de)
KR (1) KR100691296B1 (de)
CN (3) CN1161838C (de)
MY (1) MY128327A (de)
TW (1) TW398162B (de)
WO (1) WO1999021224A1 (de)

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