KR100333627B1 - 다층 인쇄회로기판 및 그 제조방법 - Google Patents
다층 인쇄회로기판 및 그 제조방법 Download PDFInfo
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- KR100333627B1 KR100333627B1 KR20000019037A KR20000019037A KR100333627B1 KR 100333627 B1 KR100333627 B1 KR 100333627B1 KR 20000019037 A KR20000019037 A KR 20000019037A KR 20000019037 A KR20000019037 A KR 20000019037A KR 100333627 B1 KR100333627 B1 KR 100333627B1
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- resin layer
- printed circuit
- circuit board
- forming
- layer
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1536—Temporarily stacked PCBs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
Abstract
Description
Claims (10)
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다층개의 층으로 구성된 인쇄회로기판에서,부품이 장착되어 연결되는 상면의 회로패턴의 두께를 메인 PCB측에 연결되는 하면의 회로패턴의 두께보다 얇게 형성한 것을 특징으로 하는 다층 인쇄회로기판.
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다수개의 층으로 구성된 인쇄회로기판에서,상기 다수개의 층 내부에 블라인드비어홀이 형성되고, 상기 블라인드비어홀의 외측에 상기 다수개의 층을 전기적으로 연결하는 도금층이 형성되며, 상기 블라인드비어홀 중심과 대략 일치되는 위치의 상면에 부품을 실장하기 위한 범프를 형성한 것을 특징으로 하는 다층 인쇄회로기판.
- 제 2 항에 있어서, 상기 범프의 직경은 상기 블라인드비어홀의 직경보다 크게 형성하는 것을 특징으로 하는 다층 인쇄회로기판.
- 절연성물질로 형성되는 수지층과,상기 수지층상에 형성되는 회로패턴을 포함하여 다수개의 층으로 구성된 인쇄회로기판에서,상기 다수개의 층 내부에 블라인드비어홀이 형성되고, 상기 블라인드비어홀은 부품이 실장되는 인쇄회로기판의 상면을 향하여 형성되어 상측이 막힌 상태로 되고, 블라인드비어홀의 상면에 부품실장용 범프가 형성된 것을 특징으로 하는 다층 인쇄회로기판.
- 코어형성용 수지층의 일측면에 이형제를 위치시키고, 상기 이형제를 포함하는 수지층의 일측면에 금속박판층과 적층수지층을 형성하는 제1단계와,상기 적층수지층을 관통하여 상하의 금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제2단계와,상기 블라인드비어홀이 개구된 표면에 회로패턴을 형성하는 제3단계와,상기 회로패턴상에 적층수지층과 금속박판층을 형성하는 제4단계와,상기 적층수지층을 관통하여 상하의 금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제5단계와,위에서 형성된 패널을 이형제를 이용하여 분리하는 제6단계와,상기 분리된 각각의 패널의 상면과 하면에 회로패턴을 형성하는 제7단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 제4단계와 제5단계를 반복하여 적층되는 층수를 결정함을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 제2단계와 제5단계는 레이저를 이용하여 블라인드비어홀을 천공하는 단계와,상기 블라인드비어홀을 포함하는 외층에 도금층을 형성하는 단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 5 항에 있어서, 상기 이형제 측면에 위치한 금속박판의 회로패턴에 부품 실장용 범프와 그 반대면의 회로패턴에 메인 PCB연결용 범프를 형성하는 8단계를 더 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 일측면에 제1금속박판과 반대면에 제2금속박판을 가지는 제1수지층을 제2금속박판 측에서 제1금속박판측으로 관통하여 상기 제1,2금속박판층을 전기적으로 연결하는 블라인드비어홀을 형성하는 제1단계와,상기 제2금속박판측 표면에 회로패턴을 형성하며 제1수지층을 노출시키는 제2단계와,제3금속박판을 한면에만 가지는 제2수지층을 상기 노출된 제1수지층과 마주하도록 상기 제1수지층에 제2금속박판측면에 적층하여 상기 제1수지층과 제2수지층을 일체화하는 제3단계와,상기 제3금속박판측에서 제2수지층을 관통하여 상기 제2금속박판과 제3금속박판을 전기적으로 연결하는 블라인드비어홀을 형성하는 제4단계와,상기 제1금속박판과 제3금속박판에 회로패턴을 형성하는 제5단계와,상기 제1금속박판의 회로패턴과 연결된 블라인드비어홀의 중심과 대략 일치하는 위치에 부품실장용 범프를 형성하는 제6단계를 포함하여 구성됨을 특징으로 하는 다층 인쇄회로기판의 제조방법.
- 제 9 항에 있어서, 상기 제1단계 및 제4단계에서 형성되는 블라인드비어홀에는 도금층을 형성하여 상하 금속박판을 연결하는 것을 특징으로 하는 다층 인쇄회로기판의 제조방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
JP2001096366A JP5000809B2 (ja) | 2000-04-11 | 2001-03-29 | 多層印刷回路基板及びその製造方法並びに多層印刷回路基板を利用したbga半導体パッケージ |
US09/832,193 US6580036B2 (en) | 2000-04-11 | 2001-04-11 | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
US10/384,658 US6884945B2 (en) | 2000-04-11 | 2003-03-11 | Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
KR1020000019040A KR100366411B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20000058316A KR20000058316A (ko) | 2000-10-05 |
KR100333627B1 true KR100333627B1 (ko) | 2002-04-22 |
Family
ID=26637807
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR20000019037A KR100333627B1 (ko) | 2000-04-11 | 2000-04-11 | 다층 인쇄회로기판 및 그 제조방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6580036B2 (ko) |
JP (1) | JP5000809B2 (ko) |
KR (1) | KR100333627B1 (ko) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2009108030A3 (en) * | 2008-02-29 | 2009-11-26 | Lg Micron Ltd. | Printed circuit board and method of manufacturing the same |
KR101449022B1 (ko) * | 2008-02-29 | 2014-10-08 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조방법 |
KR102629710B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 캐비티 형성방법 |
KR102629708B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 마운트홀 형성방법 |
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JP2003059971A (ja) * | 2001-08-20 | 2003-02-28 | Nec Kansai Ltd | 配線基板及びその製造方法並びに半導体装置 |
JP3910387B2 (ja) * | 2001-08-24 | 2007-04-25 | 新光電気工業株式会社 | 半導体パッケージ及びその製造方法並びに半導体装置 |
JP4082995B2 (ja) * | 2001-11-30 | 2008-04-30 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
JP2003188541A (ja) * | 2001-12-19 | 2003-07-04 | Kyocera Corp | 配線基板の製造方法 |
US7548430B1 (en) | 2002-05-01 | 2009-06-16 | Amkor Technology, Inc. | Buildup dielectric and metallization process and semiconductor package |
US9691635B1 (en) | 2002-05-01 | 2017-06-27 | Amkor Technology, Inc. | Buildup dielectric layer having metallization pattern semiconductor package fabrication method |
JP2004186265A (ja) * | 2002-11-29 | 2004-07-02 | Ngk Spark Plug Co Ltd | 多層配線基板の製造方法 |
US6787443B1 (en) * | 2003-05-20 | 2004-09-07 | Intel Corporation | PCB design and method for providing vented blind vias |
ATE358411T1 (de) * | 2003-07-08 | 2007-04-15 | Viasystems Group Inc | Verfahren zur herstellung einer midplane |
US6972382B2 (en) * | 2003-07-24 | 2005-12-06 | Motorola, Inc. | Inverted microvia structure and method of manufacture |
JP4549695B2 (ja) * | 2003-08-08 | 2010-09-22 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
TWI227502B (en) * | 2003-09-02 | 2005-02-01 | Ind Tech Res Inst | Precise multi-pole magnetic components and manufacturing method thereof |
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KR101449022B1 (ko) * | 2008-02-29 | 2014-10-08 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조방법 |
KR102629710B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 캐비티 형성방법 |
KR102629708B1 (ko) | 2023-07-31 | 2024-01-29 | 아주전자(주) | 인쇄회로기판의 마운트홀 형성방법 |
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KR20000058316A (ko) | 2000-10-05 |
JP2001308548A (ja) | 2001-11-02 |
JP5000809B2 (ja) | 2012-08-15 |
US6884945B2 (en) | 2005-04-26 |
US20030168255A1 (en) | 2003-09-11 |
US20010027875A1 (en) | 2001-10-11 |
US6580036B2 (en) | 2003-06-17 |
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