CN1136220A - 载片及其制造方法和安装方法 - Google Patents

载片及其制造方法和安装方法 Download PDF

Info

Publication number
CN1136220A
CN1136220A CN96101291A CN96101291A CN1136220A CN 1136220 A CN1136220 A CN 1136220A CN 96101291 A CN96101291 A CN 96101291A CN 96101291 A CN96101291 A CN 96101291A CN 1136220 A CN1136220 A CN 1136220A
Authority
CN
China
Prior art keywords
mentioned
slide glass
resin
resin bed
salient point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN96101291A
Other languages
English (en)
Other versions
CN1076872C (zh
Inventor
中村嘉文
别所芳宏
板垣峰广
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1136220A publication Critical patent/CN1136220A/zh
Application granted granted Critical
Publication of CN1076872C publication Critical patent/CN1076872C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/17104Disposition relative to the bonding areas, e.g. bond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0104Properties and characteristics in general
    • H05K2201/0129Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/043Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

在BGA及LGA等中,通过在载片的外部电极和电路布线基板之间形成树脂层,防止由于外部连接电极和电路布线基板的热膨胀系数不同而使外部连接电极部分出现裂纹,从而提高热冲击试验的可靠性,导通半导体元件的电极的连接布线设置在绝缘性基板的表面,在其背面设置连接电路布线基板的连接电极的外部连接电极,外部连接电极具有由导体构成的软焊料球,在外部连接电极侧面部分形成树脂层。

Description

载片及其制造方法和安装方法
本发明涉及用于在电路布线基板上安装半导体元件的载片及其制造方法。更详细地说是涉及用于半导体元件的安装及用于MCM(多片组件)的载片及其制造方法和它的安装方法。
迄今为止,半导体器件中有称为BGA(球状栅格阵列)外壳及LGA(焊接区栅格阵列)外壳的二种类型。这是一些安装了半导体元件的载片的外部连接电极呈栅格状地被配置在载片的背面上的半导体器件。这样安装起来的半导体器件与以往的QFP(四方扁平外壳)相比较,由于外部连接电极位于外壳的背面,所以具有能使半导体器件的尺寸大幅度地小型化的优点。另外,外部连接电极的间距也比间距为0.3mm或0.5mm的QFP要宽一些,达1.5mm或1.27mm,易于安装。因此BGA外壳或LGA外壳的器件作为新的半导体器件已显露头角。
原有的BGA外壳的半导体器件示于图8。图8中1是载片、2是焊料球、3是半导体元件、4是外部连接电极。载片1是这样构成的,即把导通半导体元件3的电极焊接区31的连接布线61设置在绝缘性基板60的表面60a上,把外部连接电极4设置在背面。通过设置在将电绝缘性基板60的表面和背面导通的通孔62内的布线64等,使表面60a上的连接布线61和背面60b上的外部引出电极62电导通。
焊料球2作为BGA至外部的连接电极呈栅格状排列在载片1的背面上,该焊料球2与图中未示出的电路布线基板相连接。另一方面,LGA是通过非球形软钎焊料或插口与电路布线基板连接。
BGA与LGA相比较,因BGA是用焊料球进行安装的,所以载片和电路布线基板的安装间隔宽,用焊料安装时,安装的可靠性比LGA高。因此在具有呈栅格状的外部连接电极的半导体器件中以BGA为主。可是,在像计算机的CPU之类需要提高质量的半导体器件中,多半使用LGA和称为插口组合形态的半导体器件。
可是,在用焊料将这种原有的BGA或LGA这样的载片安装到电路布线基板上时,安装部分是用软焊料将载片和电路布线基板直接连接起来的,所在在按照JIS(日本工业标准)C0025中的规定进行从-40℃变化到+100℃的热冲击试验即环境可靠性试验时,由于载片和电路布线基板的热膨胀系数不同,在外部连接电极部分出现裂纹,造成外部连接电极剥离、断开、存在连接性变坏的现象。所以BGA或LGA有热冲击试验的可靠性低的问题。
本发明的目的就是为了解决上述问题,提供一种能防止外部连接电极部分出现裂纹、外部连接电极剥离、能提高可靠性的载片及其制造方法和它的安装方法。
为了达到上述目的,本发明的载片是这样一种载片,即把连接半导体元件电极的连接布线设置在绝缘性基板的表面上,把用于连接电路布线基板的连接电极的外部连接电极设置在背面,该载片的特征在于上述外部连接电极用由导体构成的凸点形成,并形成至少覆盖该凸点的一部分的树脂层。而且可在安装后形成树脂层将焊接部分覆盖住。
在上述载片中最好在凸点周围平坦地或呈凸状地形成上述树脂层,并使该凸点的前端部分露出。
在上述载片中最好在绝缘性基板的背面形成层状的上述树脂层并使该凸点的前端部分露出。
在上述载片中最好由软焊料球构成上述凸点。
在上述载片中最好以从Sn、Cu、Ag、Au及Ni中选择的至少一种为主要成分的导体构成上述凸点。
在上述载片中最好用树脂层从载片一侧算起将上述凸点至少覆盖其高度的20%以上。
在如上构成的载片中,上述树脂最好是环氧树脂。
在上述载片中,上述树脂层的厚度最好在50~1000μm范围内。
本发明的载片制造方法的特征在于,在绝缘性基板的表面上设置连接半导体元件的电极的连接布线,在上述绝缘性基板的背面形成具有用于连接电路布线基板上的连接电极的凸点的外部连接电极,用膏状树脂覆盖上述外部连接电极的侧面部分,然后在使上述树脂膏硬化的温度下进行热处理,形成树脂层。
在上述制造方法的结构中,最好使膏状树脂流入上述外部连接电极之间,然后在使上述树脂膏梗化的温度下进行热处理,形成树脂层。
在上述制造方法中,最好将热量供给形成上述外部连接电极的背面,使树脂流入,形成树脂层。
在上述制造方法中,最好将形成由上述凸点构成的外部连接电极的背面浸渍在膏状树脂中,然后从树脂中取出上述载片,在使上述树脂硬化的温度下进行热处理,形成树脂层,此后对该树脂层形成面进行加工,直到出现上述凸点为止。
在上述制造方法中,最好将树脂喷射到上述外部连接电极面上,在上述外部连接电极面上形成树脂层,然后加工该树脂层形成面,直到出现上述凸点为止。
在上述制造方法中,最好进行研磨加工,直到出现上述凸点为止。
在上述制造方法中,最好在通过在导体箔上形成软焊料凸点而形成外部连接电极时,通过丝网印刷,使上述导体箔的表面露出,涂敷树脂膏,形成树脂层,在使该树脂层硬化温度下进行热处理后,将软焊料膏涂敷在上述导体箔上,在使软焊料膏熔融的温度下进行热处理,形成软焊料凸点,从而形成上述外部连接电极。
在上述制造方法中,最好将由薄片构成的树脂层粘接在上述载片的背面,从而在载片上形成树脂层。
在上述制造方法中,上述膏状树脂的粘度最好在500~200000cps范围内。
本发明的载片如上所述,是一种在绝缘性基板的表面设置用于连接半导体元件的电极的连接布线,而在背面设置用于连接电路布线基板的连接电极的外部连接电极的载片,上述外部连接电极有由导体构成的凸点,形成树脂层将该凸点覆盖。因此,通过用树脂覆盖最容易施加应力的外部连接电极凸点和主体的界面周围使之能增加强度,还能将热冲击试验中在凸点和主体界面上集中的形变应力扩散到树脂层上,能使各电极的焊接部分的形变应力得到缓和。其结果,能防止由于载片和电路布线基板的热膨胀系数不同而在外部连接电极部分出现裂纹,能使外部连接电极不剥离,能提高热冲击试验的可靠性。
在上述载片中如果采用在凸点周围形成凸状的上述树脂层,并使上述凸点的前端部分露出这种好的例子,则能获得上述的作用和效果,同时容易形成树脂层,能更增加外部连接电极部分的强度。
在上述载片中如果采用在绝缘性基板的背面形成层状的上述树脂层,并使上述凸点的前端部分露出的这种好的例子,则在外部连接电极部分难以出现裂纹。另外,更容易形成树脂层,能提高生产率,能使外部连接电极部分更加牢固。
在上述载片中如果采用由软焊料球构成上述凸点的好的例子,则能获得上述作用和效果,同时在向电路布线基板的连接电极粘接时不用涂敷软焊料,能减少工序。
在上述载片中如果采用由从Sn、Cu、Ag、Au及Ni中选择的至少一种作为主要成分的导体构成上述凸点的好的例子,则能获得上述作用和效果,同时能使与电路布线基板的连接电极的连接稳定性好,能得到良好的电连接。
在上述载片中如果采用利用树脂层从载片一侧算起将上述凸点至少覆盖其高度的20%以上的好的例子,则能获得上述的作用和效果。特别是能可靠地增强由树脂层构成的外部连接电极部分。
本发明的载片的制造方法的特征在于,将连接半导体元件的电极的连接布线设置在绝缘性基板的表面,而在上述绝缘性基板的背面形成有用于连接电路布线基板的连接电极的凸点的外部连接电极,用膏状树脂覆盖上述外部连接电极的侧面部分,然后在使上述树脂膏硬化的温度下进行热处理,形成树脂层。通过这种制造方法,能容易地形成树脂层,能可靠地增强由树脂层构成的外部连接电极部分。其结果是能容易地制造上述那种可靠性高的载片。
在上述制造方法中,如果采用使膏状树脂流入上述外部连接电极之间,然后在使上述树脂膏硬化的温度下进行热处理而形成树脂层的好的例子,则容易形成树脂层,同时能容易地使树脂硬化,能可靠地增强由树脂层构成的外部连接电极部分。
在上述制造方法中,如果采用将热量供给到形成上述外部连接电极的背面,使树脂流入而形成树脂层的这种好的例子,则由于用流入的方法形成树脂层,所以能更迅速、更容易地形成树脂层,能可靠地增强由树脂层构成的外部连接外部部分。
在上述制造方法中,如果采用将形成由上述凸点构成的外部连接电极的背面浸渍在膏状树脂中,然后将上述载片从树脂中取出,在使上述树脂硬化的温度下进行热处理而形成树脂层,然后对该树脂层形成面进行加工,直到出现上述凸点为止的好的例子,则能更迅速、更容易地形成树脂层,能制造用树脂层增强外部连接电极部分的载片。另外,能可靠地使外部连接电极露出,能确保导通。
在上述制造方法中,如果采用将树脂喷射到上述外部连接电极面上、在上述外部连接电极面上形成树脂层,然后对该树脂层形成面进行加工的这种好的例子,则能制造用树脂层增强外部连接电极部分的载片,能更迅速、更容易地形成树脂层。
在上述制造方法中,如果采用研磨加工直到出现上述凸点的好的例子,则能制造用树脂层增强外部连接电极部分的载片,能更迅速、更容易地形成树脂层。
在上述制造方法中,如果采用通过在上述导体箔上形成软焊料凸点而形成外部连接电极时,通过丝网印刷使上述导体箔表面露出,涂敷树脂膏而形成树脂层,在使该树脂层硬化的温度下进行热处理后,将软焊料膏涂敷在上述导体箔上,在使软焊料膏熔融的温度下进行热处理,进行形成软焊料凸点而形成上述外部连接电极的这种好的例子,则能制造用树脂层进一步增强外部连接电极部分的载片,能更迅速、更容易地形成外部连接电极和树脂层。
如上所述,如果采用本发明,则能使热冲击试验中集中于焊料连接部分的形变应力扩展到树脂层中,能缓和各部分的形变应力。另外,能用树脂增加最容易施加应力的载片和软焊料的界面的强度。
其次,本发明的载片安装方法是一种将在背面形成树脂层而外部连接电极部分通过上述树脂层露出到外部的载片安装到电路布线基板上的安装方法,其特征在于,在电路布线基板的连接电极上形成软焊料膏层,将上述载片安装到上述电路布线基板上,以便将载片背面的外部连接电极和上述电路布线基板的连接电极上的软焊料膏连接起来,然后用规定的温度使软焊料膏熔融,同时将在上述载片背面形成的树脂层粘接在上述电路布线基板上。
在上述方法中,最好利用上述树脂层的表面粘接层将上述树脂层和上述电路布线基板粘接起来。
在上述方法中,最好在上述软焊料膏熔融时使上述树脂层也熔融,从而将上述载片和上述电路布线基板粘接起来。
在上述方法中,上述树脂层的厚度和在上述电路布线基板上形成的软焊料膏层的厚度实际上相同,或者最好使上述软焊料膏层的厚度稍厚一些。
另外,在上述方法中,上述树脂层的软化点最好在150℃以上且在上述软焊料膏的熔解温度以下。
图1是示出本发明的载片的一实施例的局部剖面图。
图2是示出将具有形成了本发明一实施例中的树脂层的软焊料球的载片装配在电路基板上的状态下的局部剖面图。
图3是示出具有形成了本发明一实施例中的树脂层的软焊料球的载片的局部剖面图。
图4是示出具有由形成了本发明的另一实施例的树脂层的由导体构成的凸点的载片的局部剖面图。
图5A~D是说明本发明的一实施例的载片制造方法的一部分工序的剖面图。
图6A~D是示出形成了本发明的另一实施例的树脂层的载片的局部剖面图。
图7是示出形成了本发明的另一实施例的树脂层的载片的局部断面图。
图8是示出先有有技术的BGA(球状栅格阵列)外壳的局部断面图。
图中1:载片
图中2:软焊料球
图中3:半导体元件
图中4:外部连接电极(由导体构成的凸点)
图中5:树脂层
图中7:软焊料球侧面的树脂层。
图中8:印刷布线基板(电路布线基板)
图中9:载片
图中10:玻璃、陶瓷布线基板图中11:连接布线图中12:外部电极图中13:树脂层图中14:由导体构成的凸点图中20:玻璃、陶瓷布线基板图中21:连接布线图中22:外部电极图中23:通孔图中24:布线图中31:连接电极图中32:软焊料球图中40:玻璃、陶瓷布线基板图中41:布线电极图中42:外部连接电极图中43:树脂层图中44:蚀刻后的孔图中45:软焊料凸点图中50:由树脂构成的薄片图中51:冲孔图中52:印刷布线基板图中53:连接电极图中54:软焊料图中55:粘接层图中60:绝缘性基板图中61:连接布线图中62:外部引出电极图中63:通孔
图中85:连接布线
下面参照附图说明本发明的载片的一个实施例。
图1是示出本发明的一实施例中的载片的局部剖面图。图2是示出将图1中的载片安装在印刷布线基板上的状态下的局部剖面图。图3是示出在软焊料球的侧面有树脂层的另一实施例的载片的局部剖面图。
在图1及图2中,1是用于安装半导体元件3的载片、2是连接外部电极22以形成由导体构成的凸点的软焊料球、4是由外部电极22和软焊料球构成的外部连接电极(由导体构成的凸点)、5是覆盖凸点的树脂层、8是将安装了半导体元件3的载片1安装起来的印刷布线基板。
载片1与上述原有的载片结构相同,在玻璃、陶瓷等绝缘性基板20的表面20a上设有导通半导体元件3的电极焊接区31及与其连接的软焊料球32的以从Sn、Cu、Ag、Au及Ni中选择的至少一种为主要成分的连接电极21,在背面20b上设有由同样成分构成的外部电极22。而且由该外部电极22和软焊料球2形成外部连接电极4。另外,通过设在通孔23内部的布线24,将表面20a上的连接电极21和背面20b上的外部连接电极4电导通。该载片1的表面和背面上的电极的导通方法不限于设置图1及图2所示的通孔,也可以根据基板的不同情况,通过基板面上的布线进行导通。
软焊料球2是作为将BGA连接到外部的连接电极用的,它由软焊料形成,且粘接到设置在位于绝缘性基板20的背面20b上呈栅状排列配置的外部电极22上。软焊料球2的直径为0.5~1.0mm左右。如果太小则容易产生连接不良,连接的可靠性变低,如果太大则可能产生短路。
树脂层5是为了当用软焊料焊接载片1上的外部连接电极4和印刷布线基板上的布线时防止电极因热应力作用而断裂、用来吸收热应力而设的。该树脂层5是在绝缘性基板20的背面20b上的外部连接电极4之间的全部表面上形成的,它从外部电极22和软焊料球2的界面一直覆盖到前端部2a附近,以0.1~1.0mm左右的厚度形成,以便使软焊料球2的前端部2a露出。即为了能确实覆盖载片1和凸点的界面,使厚度至少达到外部连接电极4的高度的20%以上,最好使厚度相当于软焊料球2的半径以上、直径以下的尺寸。
作为树脂层5使用的树脂,可以采用热塑性树脂或热硬化性树脂中的任何一种。该树脂的粘度最好在室温下约大于200000厘泊,最好制成树脂膏使用,以便具有能进行形成树脂层5的作业的粘度。使用环氧树脂最好。用以上方法制作带有树脂层的附有软焊料球的载片。
如上构成的载片1如图2所示,它通过软焊料球2焊接在印刷布线基板8的连接布线85上,从而安装在布线基板8上。进行该安装时,为了用软焊料焊接载片1上的外部连接电极4和印刷布线基板8上的布线85而需要加热,即使由于加热而在外部连接电极4上产生热应力,也能利用树脂层5将热应力缓和,能防止在外部连接电极4的软焊料球2的界面等处产生裂纹,且能防止产生连接不良等。
图3是示出本发明的载片的另一实施例的局部剖面图。本实施例的载片与图1所示的实施例的载片的不同之处在于在软焊料球2的侧面周围设有凸状的树脂层7。与图1所示实施例相当的部分标以相同的符号,详细说明从略。
树脂层7设在软焊料球2的侧面周围,呈凸状,厚度为0.1~0.5mm,几乎沿绝缘性基20的背面20b全部表面以同一厚度设置,这是与图1所示例不同之处。这样形成树脂层7,能容易使软焊料球2的前端2a露出,且能容易与电路布线基板进行良好的连接。
其次,利用更具体的实施例说明本发明。
(实施例1)
本实施例的载片的结构如图1所示。如上所述,作为载片1的基板20,使用通用的玻璃、陶瓷制的基板,作为基板布线导体使用Cu。
本实施例的载片的制造方法是首先在上述玻璃、陶瓷基板20的表面20a上,用Cu设置用于安装半导体元件的布线图形21,在背面20b上设置呈格子状的外部电极22。将共晶软焊料膏(63Pb/37Sn合金膏,千住金属(株)制)通过金属印刷法涂敷在上述基板20的背面20b的外部电极22上。上述涂敷结束后将软焊料球2排列在各外部电极22的软焊料膏上,形成作为外部连接电极的外部连接端子4。作为软焊料球2是使用合金成分为63Pb/37Sn的软焊料,球的直径为0.7mm。在240℃的峰值温度下,在10秒内通过红外线回流将上述软焊料膏和软焊料球2熔融。用上述方法在载片1的背面20b上的外部电极22上形成软焊料球2。
然后,将注入注射器中的树脂膏射到已形成上述软焊料球的载片背面的上述软焊料球2之间。树脂膏的量控制在能均匀地将软焊料球2埋到其直径的大约一半处(层厚约0.4mm),使软焊料球2的前端2a露出。在负压气氛中在150℃下进行持续2小时的处理使上述树脂膏硬化。作为该树脂膏使用的是环氧树脂(ABLESTIK公司的埃伊普尔邦德(エイプルボンド),975-2L,20000CPS)。用上述方法制成了带具有树脂层的附有软焊料球的载片。
将共晶软焊膏(合金成分为60Pb/37/Sn的膏,千住金属(株)制)用金属印刷法印刷在具有用于安装可靠性试验的布线图形的通用印刷布线基板上,将已形成上述树脂层的载片安装在上述印刷好的软焊料上。在240℃的峰值温度下,持续10秒钟用红外线回流使上述安装体上的软焊料熔融,制成载片安装体(图2)。
通过环境可靠性试验之一的上述热冲击试验(-40℃~100℃)对用上述方法制作的载片安装体进行了可靠性试验。其结果表明,经过1000次循环,能几乎无变化地保持其电阻值。因此断定外部连接电极无裂纹等。因此,能将热冲击试验中安装可靠性低的那种BGA型载片制作成安装可靠性高的载片。
(实施例2)
本实施例的载片结构如图3所示。本实施例的载片与实施例1不同之处仅在于树脂层7是沿软焊料球的侧面形成的。
本实施例的载片的制造方法是首先用与实施例1相同的方法在玻璃、陶瓷基板20的外部电极22上形成软焊料球2,从而形成了由外部电极22和软焊料球2构成的外部连接电极4。
然后,将注入注射器中的树脂膏射到已形成软焊料球2的载片1的背面20b上的各软焊料球2上。树脂膏的量控制在能将玻璃、陶瓷基板20和软焊料球2的连接面完全埋住、但使软焊料球2的前端2a露出的厚度(约0.2mm)。树脂膏射出后,用酒精将软焊料球2的前端洗净。在负压气氛中,按照温度:150℃,处理时间:2小时,使上述树脂膏硬化。作为树脂膏使用了与实施例1相同的环氧树脂。
用金属印刷法将共晶软焊料膏(合金成分为63Pb/37Sn的膏,千住金属(株)制)印刷在具有用于安装可靠性试验的布线图形的通用印刷布线基板上,将已形成树脂层7的载片1安装在上述印刷好的软焊料上。在240℃的峰值温度下,持续10秒钟用红外线回流使上述安装体上的软焊料熔融。
用以上方法制作载片安装体,并通过环境可靠性试验之一的上述热冲击试验(-40℃~100℃)对该安装体进行了可靠性试验。其结果表明经过1000次循环能几乎无变化地保持电阻值。由此断定外部连接电极无裂纹等。因此,能将在热冲击试验中安装可靠性显得低的BGA型载片制作成安装可靠性高的载片。
(实施例3)
本实施例的载片结构如图4所示。在图4中,9是安装了半导体元件3的载片,11是导通半导体元件3的连接电极31的布线图形,13是覆盖由导体构成的凸点14的树脂层,15是所设置的用于导通基板表、背两面的导体的通孔。本实施例的载片9与实施例1的载片1不同之处在于外部连接端子(电极)4用由导体构成的凸点14形成。
该载片9用与实施例1同样的方法,在玻璃、陶瓷基板10的表面10a上设置布线图形11,再通过该布线图形11用软焊料32与半导体元件3的连接电极31焊接起来而电导通。外部电极12设置在陶瓷基板10的背面10b上,在该外部电极12的表面上形成由导体构成的凸点14,由外部电极12和凸点14形成外部连接端子4。基板10的表面10a上的布线图形及背面10b上的外部电极11通过通孔15彼此导通。用Cu形成布线图形11及外部电极12。在包含由导体构成的凸点14的周围的背面10b的全部表面上形成厚约0.3mm的树脂层13。将凸点14的前端14a上的树脂除去,确保导电性。
本实施例中载片9的制造方法是首先在玻璃、陶瓷基板10的表面10a上用Cu形成用于安装半导体元件的布线导体11的图形,将外部电极12呈格子状地设置在背面10b上。在基板10的背面10b的外部电极12上用镀Cu法形成凸点14。上述凸点14的高度为200μm。
其次,在扁平的不锈钢上通过供给树脂膏使其厚度均匀地形成树脂层,将有凸点14的面(背面10b)朝下而将已形成上述凸点14的载片9放到上述树脂膏上,使树脂一直浸渍到凸点14和玻璃、陶瓷基板10的界面。此后通过提起载片9而将载片9从树脂层中取出。将载片9的安装面的表面10a朝下,将已涂敷了树脂膏的载片9置于加热板上,通过加热使树脂膏软化,便在载片9上均匀地形成树脂膏层。加热板的温度为60℃。然后在负压气氛中,在150℃的温度下持续2小时,使上述树脂膏硬化,形成树脂层13。作为树脂膏使用了与实施例1相同的树脂膏。
在本实施例中也可以像上述实施例那样形成树脂层。
其次,用锉刀研磨上述树脂层13的已硬化了的载片9的树脂层13的一侧,直到露出由导体构成的凸点14的表面14a为止。这时通过破坏在由导体构成的凸点14上形成的树脂层13,可使导体部分的表面露出。
用金属印刷法将共晶软焊接膏(合金成分为63Pb/37Sn的膏,千住金属(株)制)印刷在具有用于安装可靠性试验布线图形的通用印刷布线基板上,将上述研磨完成的载片安装到上述印刷好的软焊料上。在240℃的峰值温度下,持续10秒钟用红外线回流使上述安装体上的软焊料熔融。
用以上方法制作载片安装体,通过环境可靠性试验之一的上述热冲击试验(-40℃~100℃)对上述安装体进行可靠性试验,其结果表明经过1000次循环能几乎无变化地保持电阻值。由此断定外部连接电极上无裂纹等。因此,能将热冲击试验中安装可靠性低的BGA型载片制作成安装可靠性高的载片。
(实施例4)
图5A~D是示出本实施例的载片的制造方法的一部分工序图。在图5A~D中,40是形成载片的绝缘性布线基板,在布线基板40的表面上形成布线电极41,在背面形成外部电极42,同时形成树脂层43。44是蚀刻后的孔,在蚀刻后的孔44上形成软焊料45。
与上述一样,用通用玻璃、陶瓷作为载片的基板,用Cu作为基板布线导体。
如图5A所示,首先用Cu在玻璃、陶瓷基板40的表面形成用于安装半导体元件的布线电极41的图形,在背面呈格子状地形成外部电极42。
然后,如图5B所示,用金属印刷版在上述基板40的背面的全部表面上全面印刷树脂膏,形成厚为200μm的树脂层43。在负压气氛下,在150℃下持续2小时对上述印刷过的基板40加热,使上述树脂膏硬化。作为树脂膏,使用了与实施例1同样的树脂膏。
然后,如图5C所示,对已形成树脂层43的基板40的背面上的外部电极42进行蚀刻,在外部电极42部位的树脂层43上开一个孔44,使电极42露出。
然后,如图5D所示,用金属印刷法将共晶软焊料膏(合金成分为63Pb/37Sn的膏,千住金属(株)制)印刷在外部电极42上的孔44中,在240℃的峰值温度下,持续10秒钟用红外线回流使软焊料熔融而设置导体层45。
然后,用金属印刷法将共晶软焊料膏(合金成分为63Pb/37Sn的膏,千住金属(株)制)印刷在具有用于安装可靠性试验布线图形的通用印刷布线基板上,将上述已形成上述树脂层的载片安装在上述已印刷的软焊料上。在240℃的峰值温度下,持续10秒钟用红外线回流对上述安装体加热,使软焊料熔融。
用以上方法制作载片安装体,并通过环境可靠性试验之一的上述热冲击试验(-40℃~100℃)对该安装体进行了可靠性试验。其结果是经过1000次循环能几乎无变化地保持电阻值。由此断定外部连接电极上无裂纹。因此能将在热冲击试验中安装可靠性低的BGA型载片制作成安装可靠性高的载片。
(实施例5)
本实施例的载片结构如图6A~D所示。图6A是从载片的印刷布线基板安装面看到的平面图。在该图6A中,20是玻璃、陶瓷布线基板的印刷布线基板安装面、22是外部电极。图6B是由树脂构成的薄片的平面图。该图中的50是由树脂构成的薄片,51是冲孔。图6C是将图6A和B所示的零件粘接后的剖面图。本实施例的载片与实施例1不同之处仅在于不安装软焊料球和由薄片形成树脂层。
本实施例的载片制造方法是首先用与实施例1相同的方法形成玻璃、陶瓷基板20上的外部电极22。
然后,用冲孔机在由热塑性聚氧醚树脂构成的薄片(厚度为0.15mm)上开出直径为0.5mm的孔。上述树脂薄片的软化点为160℃。使上述载片上的外部电极和上述开孔后的薄片上的孔的部位相对地重合。将用聚四氟乙烯树脂(特氟隆)加工过的扁平的不锈钢加热到160℃,从薄片一侧用上述不锈钢对上述部位重合后的载片加热进行临时粘接,可将上述薄片临时粘接在载片上。另外在加热板上将上述部位重合后的载片加热到约160℃,利用经过用聚四氟乙烯树脂(特氟隆)加工后的扁平的不锈钢对上述载片进行所希望的时间的加压处理,也可将上述薄片临时粘接在载片上。用以上方法将由树脂构成的薄片粘接在载片上。在本实施例中,作为由树脂构成的薄片,使用了聚氧醚树脂,但即使采用的树脂层的软化点不是160℃但只要是在上述软焊料的熔解温度以下的树脂,也具有同样的效果。另外,之所以需要在160℃以上,是为了放置在150℃下进行环境可靠性试验时不软化。
然后,用金属印刷法将共晶软焊料(合金成分为63Pb/37Sn的膏,千住金属(株)制)印刷在具有用于安装可靠性试验布线图形的通用印刷布线基板上,使其厚度为0.15mm,将上述已形成树脂层的载片安装在上述印刷好的软焊料上,使得载片上的外部电极与上述印刷布线基板上的电极上的软焊料膏位置重合。在240℃的峰值温度下,持续10秒钟用红外线回流加热上述安装体,使软焊料熔融。软焊料熔融时,在上述载片上形成的树脂层软化,从而将上述载片和上述印刷布线基板粘接起来。图6D示出了将载片安装在印刷布线基板上后的剖面图。52是印刷布线基板,53是连接电极,54是软焊料。
用以上方法制作载片安装体,并通过环境可靠性试验之一的上述热冲击试验(-40℃~100℃)对该安装体进行了可靠性试验。其结果是经过1000次循环能几乎无变化地保持电阻值。由此断定外部连接电极无裂纹等。因此能将热冲击试验中安装可靠性低的LGA型载片制作成安装可靠性高的载片。
另外,将由树脂构成的薄片粘接在载片上之后,用丝网印刷法将软焊料膏印刷在在树脂薄片上形成的冲孔中,在240℃的峰值温度下,持续10秒钟用红外线回流对上述安装体加热,使软焊料熔融,具有如上形成的软焊料的载片也有同样的效果。
(实施例6)
本实施例的载片结构如图7所示。图7中,9是安装了半导体元件3的载片,11是导通半导体元件3的连接电极31的布线图形,23是设置导通基板的表、背两面的导体的通路孔,22是外部电极,50是树脂层,55是粘接层。本实施例的载片与实施例5不同之处只在于在由树脂构成的薄片的两面有粘接层。
其次,在有粘接层(厚为0.05mm)的由环氧树脂构成的薄片(厚为0.15mm)上,用冲孔机在薄片的两面开出直径为0.5mm的孔。将上述载片9与上述开了孔的薄片粘结在一起,使得上述载片9的外部电极与该薄片上的孔的位置重合。
然后,用金属印刷法将共晶软焊料膏(合金成分为63Pb/27Sn的膏,千住金属(株)制)印刷在用于具有安装可靠性试验布线图形的通用印刷布线基板上,并使其厚度为0.15mm,将上述已形成了树脂层的载片安装在上述印刷好的软焊料上,使得载片上的外部电极与上述印刷布线基板的电极上的软焊料膏的位置重合,并进行焊接。在240℃的峰值温度下持续10秒钟用红外线回流加热上述安装体,使软焊料熔融。
用以上方法制作载片安装体,通过环境可靠性试验之一的上述热冲击热(-40℃~100℃)对该安装体进行了可靠性试验。其结果是经过1000次循环能几乎无变化地保持电阻值。由此断定外部连接电极没有裂纹等。因此,能将热冲击试验中安装可靠性低的LGA型载片制作成安装可靠性高的载片。
另外,将由树脂构成的薄片粘接在载片上后,用丝网印刷法将软焊料印刷在在树脂薄片上形成的冲孔中,在240℃的峰值温度下,持续10秒钟用红外线回流加热上述安装体,使软焊料熔融,具有如上形成的软焊料的载片也有同样的效果。

Claims (26)

1.一种载片,其中用于连接半导体元件电极的连接布线设置在绝缘性基板的表面上,将用于连接电路布线基板的连接电极的外部连接电极设置在背面,该载片的特征在于,上述外部连接电极用由导体构成的凸点形成,并形成覆盖该凸点侧面的树脂层。
2.根据权利要求1所述的载片,其特征在于上述树脂层在凸点周围大致平坦地形成,并使上述凸点的前端部分露出。
3.根据权利要求1所述的载片,其特征在于上述树脂层在凸点周围呈凸出状地形成,并使上述凸点的前端部分露出。
4.根据权利要求1所述的载片,其特征在于上述树脂层在绝缘性基板的背面呈层状地形成,并使上述凸点的前端部分露出。
5.根据权利要求1所述的载片,其特征在于上述凸点由软焊料球构成。
6.根据权利要求1所述的载片,其特征在于上述凸点由以从Sn、Cu、Ag、Au及Ni中选择的至少一种成分作为主要成分的导体构成。
7.根据权利要求1所述的载片,其特征在于用树脂层从载片一侧算起将上述凸点至少覆盖其高度的20%以上。
8.根据权利要求1所述的载片,其特征在于上述树脂是环氧树脂。
9.根据权利要求1所述的载片,其特征在于上述树脂层的厚度为50~1000μm的范围。
10.一种载片的制造方法,其特征在于在绝缘性基板的表面设置连接半导体元件的电极的连接布线,在上述绝缘性基板的背面形成具有用于连接电路布线基板上的连接电极的凸点的外部连接电极,用膏状的树脂覆盖上述外部连接电极的侧面部分,然后通过用使上述树脂膏硬化的温度进行热处理而形成树脂层。
11.根据权利要求10所述的载片的制造方法,其特征在于使膏状树脂流入上述外部连接电极之间,然后通过用使上述树脂膏硬化的温度进行热处理而形成树脂层。
12.根据权利要求10所述的载片的制造方法,其特征在于将热量供给形成上述外部连接电极的背面,使树脂流入,形成树脂层。
13.根据权利要求10所述的载片的制造方法,其特征在于将形成由上述凸点构成的外部连接电极的背面浸渍在膏状树脂中,然后将上述载片从树脂中取出,用树脂覆盖上述凸点,接着用使上述树脂硬化的温度进行热处理而形成树脂层,然后使上述凸点从该树脂层形成面露出。
14.根据权利要求10所述的载片的制造方法,其特征在于将树脂喷射到上述外部连接电极表面上,用树脂层覆盖上述外部连接电极面,然后使上述凸点从该树脂层形成面露出。
15.根据权利要求13或14所述的载片的制造方法,其特征在于使上述凸点露出的方法是研磨加工。
16.根据权利要求10所述的载片的制造方法,其特征在于当通过在上述导体箔上形成软焊料凸点而形成外部连接电极时,用丝网印刷法使上述导体箔的表面露出,涂敷树脂膏而形成树脂层,在使该树脂层硬化的温度下进行热处理后,将软焊料膏涂敷在上述导体箔上,用使软焊料膏熔融的温度进行热处理,形成软焊料凸点。
17.根据权利要求10所述的载片的制造方法,其特征在于上述膏状树脂的粘度为500~200000cps的范围。
18.一种载片的制造方法,其特征在于将连接半导体元件的电极的连接布线设置在绝缘性基板的表面上,在上述绝缘性基板的背面形成用于连接电路布线基板上的连接电极的外部连接电极,将在与上述外部连接电极相对的位置处设有通孔的由树脂构成的薄片贴在上述绝缘性基板的背面,由此形成树脂层,使得上述外部连接电极与上述通孔位置重合。
19.根据权利要求18所述的载片的制造方法,其特征在于在由上述树脂构成的薄片的表面上有具有粘接性的树脂层。
20.根据权利要求18所述的载片的制造方法,其特征在于将上述由树脂构成的薄片的表面配置在上述绝缘性基板的背面,用适当的温度使上述树脂薄片熔融而粘接在上述绝缘性基板上,从而形成树脂层。
21.根据权利要求18或19所述的载片的制造方法,其特征在于在上述绝缘性基板的背面具有用于连接上述外部连接电极的凸点。
22.一种载片的安装方法,其中将在背面形成树脂层,而将外部连接电极部分通过上述树脂层露出到外部的载片安装到电路布线基板的连接电极上,以形成软焊料膏层,将上述载片安装到上述电路布线基板上,以便将载片背面的外部连接电极和上述电路布线基板的连接电极上的软焊料膏连接起来,然后用规定的温度使软焊料膏熔融,同时将在上述载片背面形成的树脂层粘接在上述电路布线基板上。
23.根据权利要求22所述的载片的安装方法,其特征在于利用上述树脂层表面上的粘接层将上述树脂层和上述电路布线基板粘接起来。
24.根据权利要求22所述的载片的安装方法,其特征在于当上述软焊料膏熔融时上述树脂层熔融,将上述载片和上述电路布线基板粘接起来。
25.根据权利要求22所述的载片的安装方法,上述树脂层的厚度和在上述电路布线基板上形成的软焊料膏层的厚度实际上相同,或者上述软焊料膏层较厚。
26.根据权利要求22所述的载片的安装方法,其特征在于上述树脂层的软化点为150℃以上而且处在上述软焊料膏的熔融温度以下。
CN96101291A 1995-02-23 1996-02-18 载片及其制造方法和安装方法 Expired - Fee Related CN1076872C (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP035359/1995 1995-02-23
JP7035359A JPH08236654A (ja) 1995-02-23 1995-02-23 チップキャリアとその製造方法
JP035359/95 1995-02-23
US08/601,293 US6229209B1 (en) 1995-02-23 1996-02-16 Chip carrier

Publications (2)

Publication Number Publication Date
CN1136220A true CN1136220A (zh) 1996-11-20
CN1076872C CN1076872C (zh) 2001-12-26

Family

ID=26374338

Family Applications (1)

Application Number Title Priority Date Filing Date
CN96101291A Expired - Fee Related CN1076872C (zh) 1995-02-23 1996-02-18 载片及其制造方法和安装方法

Country Status (4)

Country Link
US (3) US6229209B1 (zh)
EP (1) EP0729182A3 (zh)
JP (1) JPH08236654A (zh)
CN (1) CN1076872C (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100378980C (zh) * 2003-09-11 2008-04-02 罗姆股份有限公司 半导体装置
CN100435299C (zh) * 2002-09-17 2008-11-19 新光电气工业株式会社 布线基板的制备方法
USRE41051E1 (en) 1997-10-17 2009-12-22 Ibiden Co., Ltd. Package substrate
CN1909226B (zh) * 1997-10-17 2012-09-26 揖斐电株式会社 封装基板
CN104617069A (zh) * 2014-12-19 2015-05-13 南通富士通微电子股份有限公司 半导体圆片级封装结构
CN104737287A (zh) * 2014-06-06 2015-06-24 华为技术有限公司 栅格阵列封装模块
CN111822899A (zh) * 2019-04-17 2020-10-27 托普莱恩公司 焊料柱及其制造方法

Families Citing this family (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
JP2861965B2 (ja) * 1996-09-20 1999-02-24 日本電気株式会社 突起電極の形成方法
TW571373B (en) * 1996-12-04 2004-01-11 Seiko Epson Corp Semiconductor device, circuit substrate, and electronic machine
JPH10233413A (ja) * 1997-02-21 1998-09-02 Nec Kansai Ltd 半導体装置およびその製造方法並びに配線基板
DE19754372A1 (de) * 1997-03-10 1998-09-24 Fraunhofer Ges Forschung Chipanordnung und Verfahren zur Herstellung einer Chipanordnung
JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
JP3876953B2 (ja) 1998-03-27 2007-02-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP3417292B2 (ja) * 1998-04-08 2003-06-16 松下電器産業株式会社 半導体装置
US6063646A (en) * 1998-10-06 2000-05-16 Japan Rec Co., Ltd. Method for production of semiconductor package
JP2000138313A (ja) 1998-10-30 2000-05-16 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
DE19905055A1 (de) * 1999-02-08 2000-08-17 Siemens Ag Halbleiterbauelement mit einem Chipträger mit Öffnungen zur Kontaktierung
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
FR2796497B1 (fr) * 1999-07-13 2001-09-07 Thomson Csf Detexis Interconnexion perfectionnee entre un composant electronique et une carte
US6352881B1 (en) * 1999-07-22 2002-03-05 National Semiconductor Corporation Method and apparatus for forming an underfill adhesive layer
JP4526651B2 (ja) * 1999-08-12 2010-08-18 富士通セミコンダクター株式会社 半導体装置
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Necエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
US6392301B1 (en) * 1999-10-22 2002-05-21 Intel Corporation Chip package and method
JP3593935B2 (ja) * 1999-11-10 2004-11-24 ソニーケミカル株式会社 バンプ付き配線回路基板の製造方法及びバンプ形成方法
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
EP1113497A3 (en) * 1999-12-29 2006-01-25 Texas Instruments Incorporated Semiconductor package with conductor impedance selected during assembly
US6710454B1 (en) * 2000-02-16 2004-03-23 Micron Technology, Inc. Adhesive layer for an electronic apparatus having multiple semiconductor devices
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6400574B1 (en) * 2000-05-11 2002-06-04 Micron Technology, Inc. Molded ball grid array
US6916683B2 (en) * 2000-05-11 2005-07-12 Micron Technology, Inc. Methods of fabricating a molded ball grid array
US6367763B1 (en) * 2000-06-02 2002-04-09 Wayne K. Pfaff Test mounting for grid array packages
US6815712B1 (en) 2000-10-02 2004-11-09 Eaglestone Partners I, Llc Method for selecting components for a matched set from a wafer-interposer assembly
JP3735526B2 (ja) * 2000-10-04 2006-01-18 日本電気株式会社 半導体装置及びその製造方法
US7439621B1 (en) * 2000-11-08 2008-10-21 Matsushita Electric Industrial Co., Ltd. Radio frequency signal processing device
US6840777B2 (en) * 2000-11-30 2005-01-11 Intel Corporation Solderless electronics packaging
US6529022B2 (en) * 2000-12-15 2003-03-04 Eaglestone Pareners I, Llc Wafer testing interposer for a conventional package
US6673653B2 (en) * 2001-02-23 2004-01-06 Eaglestone Partners I, Llc Wafer-interposer using a ceramic substrate
US6694609B2 (en) * 2001-03-22 2004-02-24 Molex Incorporated Method of making stitched LGA connector
US6722896B2 (en) 2001-03-22 2004-04-20 Molex Incorporated Stitched LGA connector
US6573122B2 (en) * 2001-03-28 2003-06-03 International Rectifier Corporation Wafer level insulation underfill for die attach
US6551863B2 (en) * 2001-08-30 2003-04-22 Micron Technology, Inc. Flip chip dip coating encapsulant
US6613606B1 (en) * 2001-09-17 2003-09-02 Magic Corporation Structure of high performance combo chip and processing method
JP4977937B2 (ja) * 2001-09-25 2012-07-18 日本テキサス・インスツルメンツ株式会社 半導体装置及びその製造方法
US20030066679A1 (en) * 2001-10-09 2003-04-10 Castro Abram M. Electrical circuit and method of formation
KR100446429B1 (ko) * 2001-12-24 2004-08-30 동부전자 주식회사 번인 테스트 장치 및 그 제조 방법과 이를 이용한 반도체칩 번인 테스트 방법
JP3687610B2 (ja) * 2002-01-18 2005-08-24 セイコーエプソン株式会社 半導体装置、回路基板及び電子機器
US6906425B2 (en) 2002-03-05 2005-06-14 Resolution Performance Products Llc Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
WO2003077618A2 (en) * 2002-03-05 2003-09-18 Resolution Performance Products Llc Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive
TWI256719B (en) * 2002-03-06 2006-06-11 Via Tech Inc Semiconductor device package module and manufacturing method thereof
US7423337B1 (en) 2002-08-19 2008-09-09 National Semiconductor Corporation Integrated circuit device package having a support coating for improved reliability during temperature cycling
US20040105243A1 (en) * 2002-10-03 2004-06-03 Kuang-Hua Lee Electronic device having a plurality of metallic balls for transmitting signals between two circuit boards
US7059512B2 (en) * 2002-11-06 2006-06-13 Ricoh Company, Ltd. Solder alloy material layer composition, electroconductive and adhesive composition, flux material layer composition, solder ball transferring sheet, bump and bump forming process, and semiconductor device
US7253510B2 (en) 2003-01-16 2007-08-07 International Business Machines Corporation Ball grid array package construction with raised solder ball pads
US7301222B1 (en) 2003-02-12 2007-11-27 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
EP1471575A1 (en) * 2003-04-24 2004-10-27 Samsung Electronics Co., Ltd. Rf chip carrier having inductors provided therein and method of manufacturing the same
US7414505B2 (en) * 2003-05-13 2008-08-19 Samsung Electronics Co., Ltd. High frequency inductor having low inductance and low inductance variation and method of manufacturing the same
US20050068757A1 (en) * 2003-09-30 2005-03-31 Saikumar Jayaraman Stress compensation layer systems for improved second level solder joint reliability
DE10351833B4 (de) * 2003-11-06 2010-03-11 Eppendorf Ag Zellbehandlungskammer
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
KR101237172B1 (ko) 2003-11-10 2013-02-25 스태츠 칩팩, 엘티디. 범프-온-리드 플립 칩 인터커넥션
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US7258549B2 (en) 2004-02-20 2007-08-21 Matsushita Electric Industrial Co., Ltd. Connection member and mount assembly and production method of the same
WO2005081602A1 (ja) * 2004-02-24 2005-09-01 Matsushita Electric Industrial Co., Ltd. 電子部品実装方法とそれに用いる回路基板及び回路基板ユニット
US20050221635A1 (en) * 2004-03-30 2005-10-06 International Business Machines Corporation Micro-bumps to enhance lga interconnections
US7282375B1 (en) 2004-04-14 2007-10-16 National Semiconductor Corporation Wafer level package design that facilitates trimming and testing
US7205177B2 (en) 2004-07-01 2007-04-17 Interuniversitair Microelektronica Centrum (Imec) Methods of bonding two semiconductor devices
EP1732126A1 (en) * 2005-06-08 2006-12-13 Interuniversitair Microelektronica Centrum ( Imec) Method for bonding and device manufactured according to such method
US7378297B2 (en) 2004-07-01 2008-05-27 Interuniversitair Microelektronica Centrum (Imec) Methods of bonding two semiconductor devices
US7745912B2 (en) * 2005-03-25 2010-06-29 Intel Corporation Stress absorption layer and cylinder solder joint method and apparatus
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
EP1732127B1 (en) 2005-06-08 2016-12-14 Imec Method for bonding and device manufactured according to such method
US7615476B2 (en) * 2005-06-30 2009-11-10 Intel Corporation Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages
JP4137112B2 (ja) * 2005-10-20 2008-08-20 日本テキサス・インスツルメンツ株式会社 電子部品の製造方法
KR100699874B1 (ko) * 2005-11-08 2007-03-28 삼성전자주식회사 삽입형 연결부를 갖는 비. 지. 에이 패키지 그 제조방법 및이를 포함하는 보드 구조
KR100665365B1 (ko) * 2006-01-05 2007-01-09 삼성전기주식회사 발광다이오드 패키지 제조 방법
US20070278002A1 (en) * 2006-05-31 2007-12-06 Romi Mayder Method and apparatus for a low thermal impedance printed circuit board assembly
US20080176428A1 (en) * 2007-01-24 2008-07-24 Brandenburg Scott D Connector applied underfill
US8179693B2 (en) * 2007-03-30 2012-05-15 International Business Machines Corporation Apparatus for electrically connecting two substrates using a land grid array connector provided with a frame structure having power distribution elements
SG166773A1 (en) * 2007-04-24 2010-12-29 United Test & Assembly Ct Lt Bump on via-packaging and methodologies
JP2008294323A (ja) * 2007-05-28 2008-12-04 Nec Electronics Corp 半導体素子および半導体素子の製造方法
US8487428B2 (en) * 2007-11-20 2013-07-16 Fujitsu Limited Method and system for providing a reliable semiconductor assembly
US20090127667A1 (en) * 2007-11-21 2009-05-21 Powertech Technology Inc. Semiconductor chip device having through-silicon-via (TSV) and its fabrication method
JP5147779B2 (ja) 2009-04-16 2013-02-20 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
DE102009045911A1 (de) * 2009-10-22 2011-04-28 Robert Bosch Gmbh Koppelvorrichtung, Anordnung mit einer Koppelvorrichtung, Verfahren zur Herstellung einer Anordnung mit einer Koppelvorrichtung
US9449933B2 (en) 2012-03-29 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging device and method of making the same
US8756546B2 (en) * 2012-07-25 2014-06-17 International Business Machines Corporation Elastic modulus mapping of a chip carrier in a flip chip package
US8650512B1 (en) 2012-11-15 2014-02-11 International Business Machines Corporation Elastic modulus mapping of an integrated circuit chip in a chip/device package
US9105629B2 (en) 2013-03-07 2015-08-11 International Business Machines Corporation Selective area heating for 3D chip stack
US20150004750A1 (en) * 2013-06-27 2015-01-01 Stats Chippac, Ltd. Methods of Forming Conductive Materials on Contact Pads
JP6274135B2 (ja) * 2015-03-12 2018-02-07 株式会社村田製作所 コイルモジュール
US10660216B1 (en) * 2018-11-18 2020-05-19 Lenovo (Singapore) Pte. Ltd. Method of manufacturing electronic board and mounting sheet
EP3944290A1 (en) * 2020-07-21 2022-01-26 Infineon Technologies Austria AG Chip-substrate composite semiconductor device
KR20220089365A (ko) * 2020-12-21 2022-06-28 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3323956A (en) 1964-03-16 1967-06-06 Hughes Aircraft Co Method of manufacturing semiconductor devices
US3959874A (en) 1974-12-20 1976-06-01 Western Electric Company, Inc. Method of forming an integrated circuit assembly
US4172907A (en) 1977-12-29 1979-10-30 Honeywell Information Systems Inc. Method of protecting bumped semiconductor chips
JPS5529181A (en) 1978-08-24 1980-03-01 Toshiba Corp Production of semiconductor device
JPS56142656A (en) 1980-04-09 1981-11-07 Fujitsu Ltd Semiconductor device
US4616406A (en) 1984-09-27 1986-10-14 Advanced Micro Devices, Inc. Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit layers therein
US4627468A (en) * 1985-08-30 1986-12-09 Husco International, Inc. Hydraulic control valve with manual override
JPS62136049A (ja) * 1985-12-10 1987-06-19 Fuji Electric Co Ltd 半導体装置の製造方法
JPS6412553A (en) 1987-07-07 1989-01-17 Nec Corp Manufacture of semiconductor device
JPH02234447A (ja) 1989-03-07 1990-09-17 Nec Corp 半導体集積回路素子の接続方法
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
JPH03107989A (ja) 1989-09-22 1991-05-08 Fujitsu Ltd 電子回路チップの実装方法
US5148266A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies having interposer and flexible lead
US5120678A (en) 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5155904A (en) 1991-04-03 1992-10-20 Compaq Computer Corporation Reflow and wave soldering techniques for bottom side components
WO1992020097A1 (en) 1991-04-26 1992-11-12 Citizen Watch Co., Ltd. Semiconductor device and manufacturing method therefor
JP2570498B2 (ja) 1991-05-23 1997-01-08 モトローラ・インコーポレイテッド 集積回路チップ・キャリア
US5316788A (en) 1991-07-26 1994-05-31 International Business Machines Corporation Applying solder to high density substrates
US5824569A (en) 1992-07-15 1998-10-20 Micron Technology, Inc. Semiconductor device having ball-bonded pads
JPH06252286A (ja) 1993-02-22 1994-09-09 Matsushita Electric Works Ltd チップキャリア
US5397917A (en) * 1993-04-26 1995-03-14 Motorola, Inc. Semiconductor package capable of spreading heat
JP3291368B2 (ja) 1993-07-06 2002-06-10 シチズン時計株式会社 ボールグリッドアレイ型半導体パッケージの構造
US5663106A (en) 1994-05-19 1997-09-02 Tessera, Inc. Method of encapsulating die and chip carrier
US5436203A (en) 1994-07-05 1995-07-25 Motorola, Inc. Shielded liquid encapsulated semiconductor device and method for making the same
JPH0888248A (ja) * 1994-09-16 1996-04-02 Taiyo Yuden Co Ltd フェイスダウンボンディング方法及びそれに用いる接続材料
US5581122A (en) * 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
FR2728392A1 (fr) * 1994-12-16 1996-06-21 Bull Sa Procede et support de connexion d'un circuit integre a un autre support par l'intermediaire de boules
JPH08236654A (ja) * 1995-02-23 1996-09-13 Matsushita Electric Ind Co Ltd チップキャリアとその製造方法
US5664822A (en) * 1995-06-07 1997-09-09 Rosenfield Gerald F Tailgate gap cover
US5663593A (en) * 1995-10-17 1997-09-02 National Semiconductor Corporation Ball grid array package with lead frame
US5798563A (en) * 1997-01-28 1998-08-25 International Business Machines Corporation Polytetrafluoroethylene thin film chip carrier
US6034437A (en) * 1997-06-06 2000-03-07 Rohm Co., Ltd. Semiconductor device having a matrix of bonding pads
US5889655A (en) * 1997-11-26 1999-03-30 Intel Corporation Integrated circuit package substrate with stepped solder mask openings
JP2000208547A (ja) * 1998-11-12 2000-07-28 Nec Corp 半導体装置におけるバンプ補強構造およびその形成方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE41051E1 (en) 1997-10-17 2009-12-22 Ibiden Co., Ltd. Package substrate
USRE41242E1 (en) 1997-10-17 2010-04-20 Ibiden Co., Ltd. Package substrate
CN1909226B (zh) * 1997-10-17 2012-09-26 揖斐电株式会社 封装基板
CN100435299C (zh) * 2002-09-17 2008-11-19 新光电气工业株式会社 布线基板的制备方法
CN100378980C (zh) * 2003-09-11 2008-04-02 罗姆股份有限公司 半导体装置
CN104737287A (zh) * 2014-06-06 2015-06-24 华为技术有限公司 栅格阵列封装模块
WO2015184635A1 (zh) * 2014-06-06 2015-12-10 华为技术有限公司 栅格阵列封装模块
CN104737287B (zh) * 2014-06-06 2017-11-17 华为技术有限公司 栅格阵列封装模块
CN104617069A (zh) * 2014-12-19 2015-05-13 南通富士通微电子股份有限公司 半导体圆片级封装结构
CN111822899A (zh) * 2019-04-17 2020-10-27 托普莱恩公司 焊料柱及其制造方法
CN111822899B (zh) * 2019-04-17 2022-02-01 托普莱恩公司 焊料柱及其制造方法

Also Published As

Publication number Publication date
CN1076872C (zh) 2001-12-26
US6372547B2 (en) 2002-04-16
US6229209B1 (en) 2001-05-08
US6365499B1 (en) 2002-04-02
EP0729182A3 (en) 1997-02-19
EP0729182A2 (en) 1996-08-28
JPH08236654A (ja) 1996-09-13
US20020003299A1 (en) 2002-01-10

Similar Documents

Publication Publication Date Title
CN1076872C (zh) 载片及其制造方法和安装方法
CN1143375C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1154178C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1189068C (zh) 多层印刷电路板及其制造方法
CN1107349C (zh) 一种半导体器件引线框架及引线接合法
CN1291467C (zh) 电子器件的制造方法
CN1160780C (zh) 用于半导体衬底的多层焊料密封带及其工艺
CN1236489C (zh) 半导体装置及其制造方法、电路基板和电子装置
CN1110078C (zh) 半导体元件的安装方法
CN1031907C (zh) 一种用于导线连接装置的毛细管以及一种应用该毛细管形成导电连接隆起的方法
CN1174665C (zh) 多层挠性布线板
CN1790651A (zh) 芯片集成基板的制造方法
CN1823409A (zh) 电气部件的安装方法和安装装置
CN1753177A (zh) 功率半导体模块及其制造方法
CN1309425A (zh) 半导体集成电路器件及其制造方法
CN1214545A (zh) 半导体封装及其制造方法
CN101065842A (zh) 电子元器件及其制造方法
CN1819189A (zh) 电路装置及其制造方法
CN1591861A (zh) 电路元件内置模块及其制造方法
CN1174475C (zh) 用于制造具有声表面波单元的射频模块元件的方法
CN1146991C (zh) 散热板引入树脂模制的半导体封装及其制造方法
CN1165989C (zh) 半导体器件和用于制造该半导体器件的方法
CN1155997C (zh) 各向异性导电膜、半导体芯片的安装方法和半导体装置
CN1536658A (zh) 半导体器件及其制造方法
CN1678175A (zh) 电路部件模块及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee