US6127633A - Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production - Google Patents
Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production Download PDFInfo
- Publication number
- US6127633A US6127633A US08/636,959 US63695996A US6127633A US 6127633 A US6127633 A US 6127633A US 63695996 A US63695996 A US 63695996A US 6127633 A US6127633 A US 6127633A
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- insulation layer
- circuit pattern
- blind hole
- resin
- substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0158—Polyalkene or polyolefin, e.g. polyethylene [PE], polypropylene [PP]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0209—Inorganic, non-metallic particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09827—Tapered, e.g. tapered hole, via or groove
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0756—Uses of liquids, e.g. rinsing, coating, dissolving
- H05K2203/0773—Dissolving the filler without dissolving the matrix material; Dissolving the matrix material without dissolving the filler
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
- H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
- H05K2203/0796—Oxidant in aqueous solution, e.g. permanganate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Definitions
- This invention relates to improvements of print circuit boards and the production method thereof, and, in particular, relates to a multilayer print circuit board having a laminated structure, wherein at least an inner print circuit pattern and an outer print circuit pattern for mounting surface mount devices are laminated on a substrate being insulated by an insulation layer interposed there-between, and are electrically connected to each other through a blind hole provided in the insulation layer.
- the multilayer print circuit boards have a plurality of electrically conductive printed circuit patterns being electrically insulated by insulation layers each interposed between the neighboring printed circuit patterns.
- FIG. 1 is a sectional view showing a multilayer print circuit board in the prior art.
- an inner print circuit pattern (referred to as an inner circuit pattern) 102 is formed on the surface thereof. Then, a surface of the inner circuit pattern is grained by using a copper surface oxidization agent. An insulation layer 103 and a bond layer 104 having a thickness of 2 to 3 ⁇ m provided for an electroless plating are respectively laminated on the inner circuit pattern 102 by coating and heat curing in the order.
- blind hole 106 for electrically connecting inner and outer circuit patterns is formed by using a carbonic acid gas laser, and a through hole 107 adjacent to the blind hole 106 by drilling.
- a chemical roughing treatment is given to the insulation layer 103 exposed to the air, the bond layer 104 for electroless plating and an insulation material portion of the substrate 101 by using a solution of dichromic acid/sulfuric acid/sodium fluoride.
- an outer circuit pattern 108 is formed on the insulation layer 103 by the electroless plating.
- conductive layers are also formed on the surfaces of the blind hole 106 and the through hole 107 thereby, wherein a land 109 is also formed for connecting the inner circuit pattern 102 to the through hole 107.
- both the inner circuit pattern 102 and the outer circuit pattern 108 can be electrically connected through the land 109 formed on the surface of the blind hole 106.
- the solution of dichromic acid/sulfuric acid/sodium fluoride is used for the chemical roughing treatment to enhance adherence of electroless plating as mentioned in the foregoing. This causes serious problems in view of the environmental protection as follows.
- Dichromic acid (chromium (VI)) is designated as an harmful material under the water-pollution preventing law, and there are some regions where the use of dichromic acid is prohibited.
- a multilayer print circuit board and the production method thereof capable of readily forming the blind hole for electrically connecting the inner and outer circuit patterns from the outer surface of the insulation layer without using harmful materials.
- a general object of the present invention is to provide the multilayer print circuit board and the production method thereof in which the disadvantages mentioned in the foregoing Description of the Related Art have been eliminated.
- a more specific object of the present invention is to provide a multilayer print circuit board comprising: an substrate being electrically insulative; a first circuit pattern provided on at least one of the surfaces of the substrate; an insulation layer provided on the substrate to overlay the first circuit pattern, the insulation layer comprising a resin insoluble in an oxidization agent and calcium carbonate powder soluble in an oxidization agent, the calcium carbonate powder being dispersed in the resin, an inner surface of the first insulation layer being roughed by the oxidization agent; a blind hole provided in the insulation layer so as to reach the first circuit pattern for exposing a surface of the first circuit pattern, an inner wall of the first hole being roughed by the oxidization agent; and a second circuit pattern provided on the insulation Layer and on the inner wall of the blind hole so as to electrically connect the first circuit pattern to the second circuit pattern through the blind hole.
- a further and more specific object of the present invention is to provide a production method of a multilayer print circuit board, comprising the steps of: forming a first conductive layer on at least one of surfaces of a substrate being electrically insulative; forming a first circuit pattern by etching the first conductive layer; forming an insulation layer on the substrate so as to overlay the first circuit pattern, the insulation layer comprising a resin insoluble in an oxidization agent and calcium carbonate powder dispersed in the insulation layer, the calcium carbonate powder being soluble in the oxidization agent; forming a blind hole in the insulation layer so as to reach the first circuit pattern for exposing a surface thereof by irradiating a laser beam from an outside of the insulation layer; roughing a surface of the insulation layer and a wall surface of the blind hole by using the oxidization agent; forming a second conductive layer on the roughed surfaces of the insulation layer and the wall surface of the blind hole; and forming a second circuit pattern by etching the second conductive layer.
- a further and more specific object of the present invention is to provide a production method of a multilayer print circuit board, comprising the steps of: forming a first conductive layer on at least one of surfaces of a substrate being electrically insulative; forming a first circuit pattern by etching the first conductive layer; forming an inner insulation layer on the substrate to overlay the first circuit pattern, the first insulation layer comprising a resin insoluble in an oxidization agent and SiO 2 powder dispersed in the resin; forming an outer insulation layer on the inner insulation layer, the outer insulation layer comprising a resin insoluble in an oxidization agent and calcium carbonate powder dispersed in the outer insulation layer, the calcium carbonate powder being soluble in the oxidization agent; forming a blind hole in the inner and outer insulation layers so as to reach the first circuit pattern for exposing a surface thereof by irradiating a laser beam from an outside of the outer insulation layer; roughing a surface of the outer insulation layer and a wall surface of the blind hole by using the oxidization agent; forming
- FIG. 1 is a sectional view showing a multilayer print circuit board in the prior art
- FIG. 2 is a sectional view of a multilayer print circuit board of the present invention
- FIGS. 3(A) through 3(F) are sectional views for explaining a production process of the present invention.
- FIG. 4 is a sectional view showing a multilayer circuit board of a second embodiment of the present invention.
- FIG. 5 is a sectional view showing one side of a multilayer circuit board of a third embodiment of the present invention.
- FIG. 6 is a sectional view showing a multilayer circuit board of a fourth embodiment of the present invention.
- FIG. 2 and FIGS. 3(A) through 3(F) A detailed description is given of a first embodiment of a multilayer print circuit board along with a production method thereof, referring to FIG. 2 and FIGS. 3(A) through 3(F) along with Tables 1 to 2.
- FIG. 2 is a sectional view of a multilayer print circuit board of the present invention
- FIGS. 3(A) through 3(F) are sectional views for explaining the production process of the present invention.
- an insulation substrate 2 having a flat shape is used as a support base.
- the insulation substrate is made of epoxy resin or glass fiber enhanced epoxy resin and inner circuit patterns 3, 3 are provided on both an upper surface 2a and a bottom surface 2b of the insulation substrate 2 by causing inner conductive layers 3a, 3a to be etched.
- the method to form the inner circuit patterns on the upper and bottom surfaces of the insulation substrate 2 is well known.
- dry films are formed on the inner conductive layers 3a, 3a made of copper foils laminated on both the upper surface 2a and the bottom surface 2b of the insulation substrate 2. After the dry films are exposed to an ultraviolet ray through a photomask and are developed by using a water solution of 1% sodium carbonate, they are etched by using a water solution of cupric chloride. The dry films are removed, resulting in the inner circuit patterns 3, 3.
- insulation layers 4, 4 are respectively provided thereon by coating.
- These insulation layers 4, 4 are mainly made of a liquid resin 4a (before cured) in which an inorganic powder (calcium carbonate) is dispersed.
- the liquid resin 4a is insoluble in an oxidizing agent but the inorganic powder is soluble in the oxidizing agent.
- the liquid resin 4a may contain a stress cushioning agent for lessening an impact of machining and a small amount of other additives.
- the above insulation layer 4 is a main structural component of the present invention.
- the material of the insulation layer 4 is selected as mentioned hereinafter so as to allow the use of such a harmless oxidizing agent as a permanganate upon performing the chemical roughing treatment before plating an outer conductive layer 7a on the insulation layer 4.
- the inorganic powder is dispersed in the insulation layer 4 so as to form grains on the surface of the insulation layer 4 by causing the inorganic powder exposed on the surface thereof to melt in the oxidizing agent when the surface roughing treatment is performed by using the oxidizing agent.
- the particle diameters of of the inorganic powder are determined to be below 15 ⁇ m (an average diameter: 1 to 5 ⁇ m, preferably 2-4 ⁇ m) taking account of a predetermined surface roughness of the insulation layer 4 and of a laser machining. Further, a content rate of the inorganic powder is to be 15 to 35 weight parts.
- the insulation layer 4 is made of following materials.
- the mixture is coated to a thickness of 50 to 100 ⁇ m on both the upper and bottom surfaces 2a, 2b of the insulation substrate 2 on which the inner circuit patterns 3, 3 are formed by a curtain coat method or a screen print method. After that, the coated layers thereof are cured at 150° C. in a furnace for 40 minutes by heating, resulting in the insulation layers 4, 4. In this embodiment, the thicknesses of the insulation layers 4, 4 are made approximately within 5 ⁇ m.
- a blind hole 5 for connecting the inner circuit pattern 3 and the outer circuit pattern 7 is formed in the insulation layer 4 so as to reach to the inner circuit pattern 3 by irradiating a laser beam from the upper side of the insulation layer 4, thus the inner circuit pattern 3 is exposed to an atmosphere.
- a laser beam is not optimum for providing holes in the inorganic material.
- the blind hole 5 has a V-letter tapered shape having an angle ⁇ of 20° to 90°, preferably 45° to 85° and most preferably 85°, to allow easy plating on the wall surface of the blind hole 5.
- This V-letter tapered shape is obtained by shifting the focus of the laser beam, and controlling the pulse width and pulse energy of the laser beam.
- Table 1 shows various kinds of the laser beams and the experimental results of the blind hole 5 provided on the insulation layer 4 by using the laser beams.
- the short pulse CO 2 and KrF laser beams are acceptable to be used, however, the short pulse CO 2 is more preferable from a practical point of view because of its availability and short machining time.
- the advantage of the short pulse laser is that it is possible to add heat energy low enough to prevent the heat deformation of the insulation layer 4 without applying excessive heat energy.
- the pulse interval thereof is determined to be from 0.003 to 0.02 seconds.
- the blind hole 5 having a tapered shape at a predetermined position on the surface side of the insulation layer 4 there are a conformal mask method, a mask imaging method, a contact mask method and a direct imaging method.
- the masking imaging method and the direct imaging method are preferable to machin the blind hole 5 having the tapered shape from the upper surface of the insulation layer 4.
- a through hole 6 passing through the insulation Layer 4 (outer), the insulation substrate 2 and the insulation layer 4 (inner) is formed by drilling.
- an oxidization treatment (chemical roughing treatment) is performed by using an oxidization agent mainly composed of potassium permanganate so as to rough the upper and bottom surfaces 2a, 2b of the insulation layer 2 and the wall surfaces of the blind hole 5 and the through hole 6.
- the oxidization treatment is performed as follows:
- the potassium permanganate (permanganate) is a harmless oxidization agent different from such harmful ones as the dichromic acid and sodium fluoride as mentioned in the foregoing.
- oxidization process Rouging process
- running cost is decreased because of no environmental pollution problem and of requiring no much cost for wastewater disposal.
- the outer conductive layers 7a, 7b are laminated on the roughed surfaces of the insulation layers 4, 4, to form the outer circuit patterns 7, 7, together with conductive layers on the roughed inner walls of the blind hole 5 and the through hole 6, by both electroless copper plating and copper plating.
- the outer circuit patterns 7, 7 are formed on the both surfaces of the insulation layers 4, 4 by etching the outer conductive layers 7a, 7b, wherein the etching treatment is conducted in such a manner that the inner circuit pattern 3 formed on the upper surface 2a side of the insulation substrate 2 is electrically connected to the outer circuit pattern 7 formed on one of the insulation layer 4 through the conductive layer of the blind hole 5, and the outer circuit pattern 7 formed on the upper surface 2a side of the insulation substrate 2 is electrically connected to the outer circuit pattern 7 formed on the bottom surface 2b side of the insulation substrate 2 through the conductive layer of the through hole 6.
- Table 2 shows the evaluation results of the multilayer circuit board 1 of the present invention.
- the multilayer circuit board 1 of the present invention has such advantages as excellent soldering characteristics, and shows excellent results in both the electrical and mechanical characteristics under various kinds of elevated environmental tests.
- the multilayer circuit board 1 having a high parts mounting density, a high function, a high reliability and a high cost performance.
- the inner circuit patterns 3, 3 are provided on both the upper surface 2a and the bottom surface 2b of the insulation substrate 2, however, it is possible to provide only one of them either on the upper surface 2a or on the bottom surface 2a thereof, wherein the inner circuit pattern 3 formed on the insulation substrate 2 is electrically connected to the outer circuit pattern 7 through the blind hole 5 defined on the insulation layer 4.
- FIG. 4 is a sectional view showing a multilayer circuit board of a second embodiment of the present invention.
- an insulation layer 40 which is provided on the inner circuit patterns 3, 3 of the first embodiment and is corresponding to the insulation layer 4 thereof has a laminated structure of two kinds of insulation layers, i.e., an outer insulation layer 40A and an inner insulation layer 40B.
- the thickness of the insulation layer 40 is made to be about 75 ⁇ m.
- the inner insulation layer 40B is formed over the inner circuit pattern 3 by being coated and cured by heating, then the outer insulation layer 40A having the same composition as that of the insulation layer 4 is provided on the inner insulation layer 40B.
- the inner insulation layer 40B has a thickness of about 50 ⁇ m and contains SiO 2 powder instead of the calcium carbonate powder which is dispersed in the insulation layer 4 of the first embodiment, to improve a machining characteristic of the insulation layer 40 and to enhance a humidity resistance thereof.
- the inner insulation layer 40B has about 2/3 thickness of that of the insulation layer 40.
- the inner insulation layer 40B is made of following materials.
- SiO 2 (average particle diameter 1-3 ⁇ m): 10 to 30 weight parts
- the mixture is coated by a curtain coat method or a screen print method on both the upper and bottom surfaces 2a, 2b of the insulation substrate 2 on which the inner circuit patterns 3, 3 are formed. After that, the coated layers thereof are cured at 150° C. in a furnace for 40 minutes by heating, resulting in the inner insulation layers 40B, 40B. Then, the outer insulation layer 40A having the same components as those of the insulation layer 4 is formed in the same manner as mentioned in the foregoing.
- a blind hole 50 is formed so as to expose the inner circuit pattern 3 by irradiating the laser beam in the same manner as mentioned in the foregoing referring to FIG. 3(C).
- the particle diameter of SiO 2 (below 8 ⁇ m, average particle diameter; 1-3 ⁇ m) is smaller than that of the calcium carbonate powder, and the content rate of SiO 2 in the inner insulation layer 40B is smaller than that of the calcium carbonate contained in the outer insulation layer 40A.
- the inner insulation layer 40B is also roughed to some degree by the solution of potassium permanganate, thus, the adverse effect does not arise in the subsequent process of forming the outer circuit pattern 7.
- the outer circuit pattern 7 is adhered intimately to the outer insulation layer 40A which is adequately roughed, and is adhered intimately to the inner circuit pattern 3 in the blind hole 50.
- the adherence characteristic of the outer circuit pattern 7 is adequately secured.
- the particle diameter of calcium carbonate powder dispersed in the outer insulation layer 40A is below 15 ⁇ m (average particle diameter: 1-5 ⁇ m, preferably 2-4 ⁇ m) as well as that of the first embodiment.
- the content rate of the calcium carbonate is limited to 15 to 35 weight parts to the resin of 100 weight parts. This effectively prevents a separation of the outer and inner insulation layers 40A, 40B by suppressing the infiltration of the treatment liquid of potassium permanganate.
- FIG. 5 is a sectional view showing one side of a multilayer circuit board of the present invention.
- a blind hole 13a having a V-letter tapered shape is formed in the first insulation layer 12 so as to expose the first inner circuit pattern 11 by irradiating the laser beam.
- a through hole (not shown) is formed at a desired position in the substrate 2.
- the blind hole 13a having a conductive layer is obtained by forming a second inner circuit pattern 13 on the first insulation layer 12.
- the numeral characters 17a, 17b denote a blind hole for connecting the third inner circuit pattern 15 and the outer circuit pattern 17, and the blind hole 17b has an additional function to be electrically connected to a blind hole 15a which connects the second inner circuit pattern 13 to the third inner circuit pattern 15.
- Blind hole 17c is constructed to enable the electrical connection of the outer circuit pattern 17 to the second inner circuit pattern 13, and a blind hole 17d is constructed to enable the electrical connection of the outer circuit pattern 17 to the first, second and third inner circuit pattern 11, 13 and 15. Needless to say, these inner and outer circuit patterns can optionally be connected to each other through the blind holes.
- blind holes (13a, 15a, 17a-17d) for electrically connecting the inner and outer circuit patterns (11, 13, 15 and 17) in a desired position the laser beam is controlled as follows.
- the blind holes (13a, 15a, 17a, 17b) for electrically connecting the adjacent circuit patterns may be formed on the insulation layers (12, 14, 16) so as to have a desired V-letter tapered shape by controlling the focus of the laser beam.
- the blind hole 17d for electrically connecting the outer circuit pattern 17 at the top and the first inner circuit pattern 11 at the bottom may be formed so as to have a desired V-letter tapered shape by controlling the energy density of the laser beam, wherein the outer and the inner circuit pattern are situated in the multilayer circuit board 10, the larger the diameter of the blind hole of the inner circuit pattern provided on such circuit pattern because the blind hole 17d has the V-letter tapered shape.
- FIG. 6 is a sectional view showing a multilayer circuit board of a fourth embodiment of the present invention.
- a multilayer circuit board 100 has the same construction as that of the third embodiment except for substituting the insulation layers 12, 14, 16 for insulation layers ⁇ 120 (120A, 120B), 140 (140A, 140B), 160 (160A, 160B) ⁇ , wherein each of the insulation layers 120, 140, 160 employs a laminated structure of two kinds of insulation layers, i.e., the outer insulation layers (120A, 140A, 160A) and the inner insulation layers (120B, 140B, 160B) as mentioned in the second embodiment.
- the construction and the fabrication method and the merits thereof are the same as those of the second and third embodiments. Thus, detailed explanation is omitted here for simplicity.
- the signal carrying pattern below the power source pattern or the ground pattern readily, for instance, by determing the first inner circuit pattern as the signal carrying pattern and by selecting either the second inner circuit pattern (13) or the third inner circuit pattern (15) as the power source pattern or the ground pattern. This prevents interference generated from the signal carrying pattern from causing adverse effect to the peripheral devices.
- the multilayer circuit board and the production method of the present invention it is possible to provide the multilayer circuit board and the production method capable of roughing surfaces of the insulation layer and the inner walls of the blind hole and the through hole by using harmless oxidization agents without using such harmful materials as dichromic acid and sodium fluoride, thus, there is no problem on the oxidization process (roughing process), and it is possible to employ a versatile processing system for that, resulting in decrease of running cost because of no environmental pollution problem and requiring no much cost for wastewater disposal.
- the inner circuit pattern formed on the substrate to the outer circuit pattern on the insulation layer interposed between the inner and outer circuit patterns by using the blind hole securely, and is possible to provide the multilayer circuit board having a high parts mounting density, a high function, a high reliability and a high cost performance.
- the signal carrying pattern below the power source pattern or the ground pattern readily, for instance, by determining the first inner circuit pattern as the signal carrying pattern and by selecting either the second inner circuit pattern or the third inner circuit pattern as the power source pattern or the ground pattern. This prevents the interference generated by the signal carrying pattern from causing adverse effect to the peripheral devices.
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- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
TABLE 1 ______________________________________ kinds of *1 *2 *3 *4 laser damage of decompo. of machin. machin. beams inner patt. insu. layer accuracy time ______________________________________ CO.sub.2 laser large large no good short pulse none small good short CO.sub.2 laser KrF excimer none small good long laser YAG laser large large no good ______________________________________ *1 damage of inner pattern; *2 decomposition of insulation layer; *3 machining accuracy; *4 machining time
TABLE 2 ______________________________________ evaluation items evaluation conditions results ______________________________________ peel strength not less than outer pattern 14 N/cm soldering heat 260° C. ± 5° C., 20 sec. normal proof test thermal shock test -60° C./30 min. normal 125° C./30 min. 100 cycles heat cyclic test -60° C./30 min. normal 20° C./10 min. 125 ° C./30 min. 20° C./10 min. 100 cycles moisture 60° C., 90%, 240 hours normal withstanding test hot oil test 260° C./10 sec.(*silicone) normal (silicon oil) 20° C./10 sec. **(air) 0° C./10 sec.(in silicone) 20° C./10 sec. **(air) 100 cycles pressure cooker (2 atms. 121° C., 100% mois. normal test + soldering 1 hour) + (260° C. ± 5° C.heat proof test 20 sec.) ______________________________________ *in silicone oil **air transfer period
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP12953595 | 1995-04-28 | ||
JP7-129535 | 1995-04-28 |
Publications (1)
Publication Number | Publication Date |
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US6127633A true US6127633A (en) | 2000-10-03 |
Family
ID=15011928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/636,959 Expired - Lifetime US6127633A (en) | 1995-04-28 | 1996-04-24 | Multilayer print circuit board having a blind hole in an insulation layer with a roughened surface formed by application of an oxidizing agent and method of production |
Country Status (5)
Country | Link |
---|---|
US (1) | US6127633A (en) |
JP (1) | JP2000188479A (en) |
KR (1) | KR100278253B1 (en) |
CN (2) | CN1092918C (en) |
TW (1) | TW323432B (en) |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294744B1 (en) * | 1995-04-28 | 2001-09-25 | Victor Company Of Japan, Ltd. | Multilayer print circuit board and the production method of the multilayer print circuit board |
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055321A (en) * | 1988-04-28 | 1991-10-08 | Ibiden Co., Ltd. | Adhesive for electroless plating, printed circuit boards and method of producing the same |
JPH0537360A (en) * | 1991-07-23 | 1993-02-12 | Fujitsu Ltd | Counting device |
JPH05308194A (en) * | 1992-04-30 | 1993-11-19 | Victor Co Of Japan Ltd | Manufacture of multilayer printed wiring board |
JPH06232554A (en) * | 1993-01-29 | 1994-08-19 | Victor Co Of Japan Ltd | Manufacture of multilayer printed wiring board |
US5434751A (en) * | 1994-04-11 | 1995-07-18 | Martin Marietta Corporation | Reworkable high density interconnect structure incorporating a release layer |
US5590461A (en) * | 1993-04-21 | 1997-01-07 | Nec Corporation | Method of making multi-layer wiring board |
US5652055A (en) * | 1994-07-20 | 1997-07-29 | W. L. Gore & Associates, Inc. | Matched low dielectric constant, dimensionally stable adhesive sheet |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0620703B1 (en) * | 1993-04-12 | 1997-12-29 | Ibiden Co, Ltd. | Resin compositions and printed circuit boards using the same |
-
1996
- 1996-04-13 TW TW085104409A patent/TW323432B/zh not_active IP Right Cessation
- 1996-04-24 US US08/636,959 patent/US6127633A/en not_active Expired - Lifetime
- 1996-04-26 KR KR1019960013035A patent/KR100278253B1/en not_active IP Right Cessation
- 1996-04-27 CN CN96108905A patent/CN1092918C/en not_active Expired - Fee Related
- 1996-04-27 CN CNB011230401A patent/CN1184865C/en not_active Expired - Fee Related
-
2000
- 2000-01-27 JP JP2000018438A patent/JP2000188479A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5055321A (en) * | 1988-04-28 | 1991-10-08 | Ibiden Co., Ltd. | Adhesive for electroless plating, printed circuit boards and method of producing the same |
JPH0537360A (en) * | 1991-07-23 | 1993-02-12 | Fujitsu Ltd | Counting device |
JPH05308194A (en) * | 1992-04-30 | 1993-11-19 | Victor Co Of Japan Ltd | Manufacture of multilayer printed wiring board |
JPH06232554A (en) * | 1993-01-29 | 1994-08-19 | Victor Co Of Japan Ltd | Manufacture of multilayer printed wiring board |
US5590461A (en) * | 1993-04-21 | 1997-01-07 | Nec Corporation | Method of making multi-layer wiring board |
US5434751A (en) * | 1994-04-11 | 1995-07-18 | Martin Marietta Corporation | Reworkable high density interconnect structure incorporating a release layer |
US5652055A (en) * | 1994-07-20 | 1997-07-29 | W. L. Gore & Associates, Inc. | Matched low dielectric constant, dimensionally stable adhesive sheet |
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US6294744B1 (en) * | 1995-04-28 | 2001-09-25 | Victor Company Of Japan, Ltd. | Multilayer print circuit board and the production method of the multilayer print circuit board |
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Also Published As
Publication number | Publication date |
---|---|
CN1141570A (en) | 1997-01-29 |
CN1338889A (en) | 2002-03-06 |
TW323432B (en) | 1997-12-21 |
JP2000188479A (en) | 2000-07-04 |
CN1184865C (en) | 2005-01-12 |
KR100278253B1 (en) | 2001-02-01 |
CN1092918C (en) | 2002-10-16 |
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