TWI460859B - 半導體裝置及製造半導體裝置之方法 - Google Patents
半導體裝置及製造半導體裝置之方法 Download PDFInfo
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- TWI460859B TWI460859B TW097120490A TW97120490A TWI460859B TW I460859 B TWI460859 B TW I460859B TW 097120490 A TW097120490 A TW 097120490A TW 97120490 A TW97120490 A TW 97120490A TW I460859 B TWI460859 B TW I460859B
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Classifications
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
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- H01L29/41725—Source or drain electrodes for field effect devices
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Description
本發明關於半導體裝置及製造半導體裝置之方法。更明確地說,本發明關於一種其中具有不同晶格常數之半導體材料係磊晶成長於閘極電極之側之凹陷部分中的半導體裝置及一種製造其之方法。
本發明包含與2007年06月27日向日本專利局申請的日本專利申請案JP 2007-169023有關之主旨,該申請案之全部內容係以引用的方式併入本文。
在具有MOS電晶體之半導體裝置中,已積極使用藉由對半導體基板之通道區域施加應力來提升載子遷移率的技術。如此類技術中之一者,已提出使用圖11中顯示之結構。在此結構中,半導體基板101之表面係由隔離膜102隔離,且閘極電極104係佈置成橫跨隔離作用區域103而延伸,並於閘極電極104之兩側提供凹陷部分。由具有與半導體基板101不同之晶格常數之半導體材料構成的磊晶層105係佈置於凹陷部分中,並作為源極/汲極區域。
在此一情況中,例如,於p型MOS (PMOS)電晶體中,具有比構成半導體基板101之矽(Si)大之晶格常數之矽鍺(SiGe)係成長成磊晶層105。從而,對通道區域ch施加壓縮應力,並提升載子遷移率。例如,參考日本未審查專利申請公開案第2006-165012號(專利文件1)。
同時,於n型MOS (NMOS)電晶體中,具有比構成半導
體基板101之矽(Si)小之晶格常數之矽碳(SiC)係成長成磊晶層105。從而,對通道區域ch施加拉伸應力,並提升載子遷移率。例如,參考Kah Wee Ang等人,"Enhanced Performance in 50 nm N-MOSFETs with Silicon-Carbon Source/Drain Regions",2004年12月,IEDM Tech.Dig.,1069至1071(非專利文件1)。
在具有上述結構之半導體裝置中,為確保電晶體之特性係彼此相同,抑制對通道區域施加之應力的變動十分重要。對通道區域施加之應力係由磊晶層之深度(即,形成於半導體基板中之凹陷之深度)來控制。
然而,因為在使半導體基板凹陷之蝕刻程序期間發生微負載效應致使凹陷面積減小,故半導體基板中之凹陷之深度隨之減小。因此,磊晶層之深度根據(在作用區域中)半導體基板上之閘極電極之布局而改變。
此外,相對於由矽鍺(SiGe)構成之磊晶層,隨著布局面積增大,結晶缺陷之數目增大,而導致接面洩漏增大。
此外,於MOS電晶體中,布局面積可藉由運用一種結構而減小,該結構中相反電導係數類型之擴散層係佈置成與源極與汲極區域中之一毗鄰,且源極與汲極區域中之一者與相反電導係數類型之擴散層係因佈置作為表面層之矽化物層而短路。在此一結構中,在其中PMOS電晶體之源極/汲極區域使用由矽鍺(SiGe)構成之磊晶層的情況中,提供藉由於半導體基板之表面層中擴散n型雜質(如砷(As)或磷(P))所形成之n型擴散層以作為相反電導係數類型之擴散
層。
然而,n型雜質之擴散率在SiGe中係高於在由矽構成之半導體基板中(即,在砷(As)之情況中高出大約七倍,且在磷(P)之情況中高出大約兩倍)。因此,相反電導係數類型之擴散層(n型擴散層)中之n型雜質係擴散至毗鄰源極/汲極區域(由SiGe構成之磊晶層)中並輕易地到達通道區域,因而增大MOS電晶體之臨限值。
期望提供一種包括磊晶層之半導體裝置,該等磊晶層之深度係在不受布局影響下受控制,且其中避免發生結晶缺陷,因而致能特性之提升,以及提供一種製造該半導體裝置的方法。
根據本發明之一具體實施例,一種半導體裝置包括:一閘極電極,其佈置於一半導體基板上;以及源極/汲極區域,其佈置於該閘極電極之兩側,該等源極/汲極區域係由植入雜質形成。該等源極/汲極區域包括一磊晶層,其藉由於該閘極電極之一側之一凹陷位置中磊晶成長具有與半導體基板不同的晶格常數之半導體材料,以及一擴散層,其佈置於該半導體基板之一表面層中。
根據本發明之另一具體實施例,一種製造一半導體裝置之方法包括:一第一步驟,其於一半導體基板上形成一閘極電極;一第二步驟,其藉由透過一遮罩圖案之蝕刻於該閘極電極之一側使該半導體基板之一表面層凹陷;一第三步驟,其於凹陷部分上形成由具有與該半導體基板不同之晶格常數的半導體材料構成之磊晶層;以及一第四步驟,
其藉由移除該遮罩圖案以曝露該半導體基板之表面層並使雜質擴散至該磊晶層及該半導體基板之表面層中來形成源極/汲極區域,該等源極/汲極區域包括其中雜質經擴散之磊晶層與藉由使雜質擴散至該表面層中而形成之一擴散層。
在根據本發明之具體實施例之半導體裝置與製造半導體裝置之方法中,源極/汲極區域包括磊晶層與擴散層。因此,磊晶層之寬度係藉由改變擴散層之寬度來調整。因此,在不受布局影響下,控制其中將形成磊晶層之半導體基板之凹陷部分的寬度,並控制藉由蝕刻而凹陷之凹陷部分的深度。因此,例如,藉由改變擴散層之寬度將磊晶層之寬度設定成一預定值,在不受布局之影響下,等化其中佈置磊晶層之半導體基板之凹陷部分的深度。此外,由於磊晶層之形成面積(布局面積)係在不受布局之影響下,因對應之擴散層之部分而減小,故而可能獲得具有小數目結晶缺陷之磊晶層。
如上所述,根據本發明之具體實施例,可在不受布局影響下控制其中佈置磊晶層之半導體基板之凹陷部分的深度。因此,可能藉由具有控制深度之磊晶層來抑制對閘極電極下之通道區域所施加之應力的變動。此外,由於可在不受布局影響下獲得具有小數目之結晶缺陷的磊晶層,故而可降低接面洩漏。因此,能夠提升半導體裝置的特性。
將參考圖式詳細地說明本發明之具體實施例。於此,將
說明在基板上佈置有複數個MOS電晶體之半導體裝置的結構。
圖1係顯示根據第一具體實施例之半導體裝置之結構的示意性剖面圖。在圖1中顯示之半導體裝置1a中,由矽(Si)構成之半導體基板3之表面係由隔離膜5隔離,且閘極電極9係佈置成橫跨隔離作用區域7而延伸。於閘極電極9之兩側,使半導體基板3之表面凹陷。由具有與半導體基板3不同之晶格常數之半導體材料構成之磊晶層11係佈置於凹陷部分中,且雜質係擴散至磊晶層11中。此外,相對於閘極電極9,擴散層13係佈置於磊晶層11之外側,擴散層13係藉由使雜質擴散至半導體基板3之表面層而形成。
在第一具體實施例中,於閘極電極9之兩側,其中雜質經擴散之磊晶層11與擴散層13構成源極/汲極區域15。
形成提供於每一閘極電極9之兩側中之每側的磊晶層11,使得具有藉由對應之擴散層13所控制的預定寬度W。例如,採用相同標準之MOS電晶體以在通道長度方向上具有實質相同的預定寬度W。因此,僅於磊晶層11之外側部分提供擴散層13,使得磊晶層11具有相同寬度。此外,在磊晶層11之通道長度方向上之預定寬度W係大約10至100 nm。
在半導體裝置1a上提供之MOS電晶體間之p型MOS(PMOS)電晶體中,磊晶層11使用具有比構成半導體基板3之矽(Si)大之晶格常數的矽鍺(SiGe)。從而,對通道區域
ch施加壓縮應力。
同時,在半導體裝置1a上提供之MOS電晶體間之n型MOS (NMOS)電晶體中,磊晶層11使用具有比構成半導體基板3之矽(Si)小之晶格常數的矽碳(SiC)。從而,對通道區域ch施加拉伸應力。
接著,將參考圖2A至5D說明半導體裝置1a之細部結構。
首先,如圖2A中顯示,製備由單晶矽構成之半導體基板3。半導體基板3具有(例如)約10 mmΩ‧cm之電阻係數。作為半導體基板3,可使用絕緣物上矽(SOI)或包括一矽鍺層之基板,只要基板之表面層係由單晶矽構成。
接著,藉由於半導體基板3之表面層上之熱氧化形成具有約15 nm之厚度的襯墊氧化物膜21。然後,藉由低壓CVD (LP-CVD)沈積具有約160 nm之厚度的氮化矽膜22。除其中於襯墊氧化物膜21上佈置氮化矽膜22之結構外,亦可使用其中於多晶矽膜上佈置氮化矽膜之結構,或其中於襯墊氧化物膜上佈置氮化矽膜之結構。
接著,如圖2B中顯示,於氮化矽膜22與襯墊氧化物膜21中形成對應隔離膜形成部分之開口22a。於此,藉由微影術形成一光阻圖案(未顯示),並使用該光阻圖案作為遮罩,蝕刻氮化矽膜22與襯墊氧化物膜21。為執行蝕刻程序,使用反應性離子蝕刻(RIE)系統、電子迴旋共振(ECR)系統或其類似物。在蝕刻程序之後,使用灰化系統或其類似物移除該光阻圖案。
接著,如圖2C中顯示,使用具有開口22a之氮化矽膜22作為遮罩來蝕刻半導體基板3,且從而,在半導體基板3中形成用於形成隔離膜之溝渠3a。溝渠3a之深度係大約0.3 μm。為執行蝕刻程序,使用反應性離子蝕刻(RIE)系統、電子迴旋共振(ECR)系統或其類似物。
在此狀態中,藉由執行熱氧化程序,一襯層氧化物膜(未顯示)係形成有約4至10 nm之厚度。熱氧化程序係於大約800℃至900℃下實施。襯層氧化物膜可為一含氮氧化物膜。可藉由CVD沈積一氮化物膜來替代該襯層氧化物膜。
接著,如圖2D中顯示,藉由以絕緣膜填充溝渠3a而形成隔離膜5,且半導體基板3之表面係分隔成複數個作用區域7。藉由沈積一絕緣膜(如高密度電漿(HDP)氧化物膜)、一無機膜(如旋塗式玻璃(SOG)膜)、一有機氧化物膜或其類似物來形成隔離膜5以便能填充溝渠3a,且隨後藉由化學機械拋光(CMP)拋光絕緣膜直到曝露氮化矽膜22為止。
接著,如圖2E中顯示,為調整相對於半導體基板3之表面隔離膜5之高度,填充於溝渠3a中之絕緣膜(例如,氧化物膜)係經受濕式蝕刻。蝕刻厚度係(例如)大約40至100 nm。接著,以熱磷酸移除氮化矽膜22以曝露襯墊氧化物膜21。
接著,如圖3A中顯示,在半導體基板3之表面層中形成井擴散層23,並執行通道植入。於此,使用光阻圖案作為遮罩,對其中形成p型MOS電晶體之區域(其後稱為"PMOS區域")及其中形成n型MOS電晶體之區域(其後稱為"NMOS
區域")中之每一者個別執行離子植入。
在PMOS區域中,形成n型井擴散層23。在此一情況中,以200 KeV之植入能量植入約1E13原子/cm2
之劑量的磷(P)離子。此外,在通道植入中,以100 keV之植入能量植入約1E11至2E13原子/cm2
之劑量的砷(As)離子。
同時,在NMOS區域中,形成p型井擴散層23。在此一情況中,以200 keV之植入能量植入約1E13原子/cm2
之劑量的硼(B)離子。此外,在通道植入中,以10至20 KeV之植入能量植入約1E11至2E13原子/cm2
之劑量的硼(B)離子。
完成離子植入程序之後,移除該光阻圖案。此外,藉由濕式蝕刻移除襯墊氧化物膜21。
接著,如圖3B中顯示,在半導體基板3之表面上形成閘極絕緣膜25。在此程序中,於其中形成高電壓MOS電晶體之區域中形成厚閘極絕緣膜25,並於其中形成低電壓MOS電晶體之區域中形成薄閘極絕緣膜25。
首先,形成由氧化矽構成之厚閘極絕緣膜25。例如,在針對3.3 V之電源供應電壓所設計之MOS電晶體中,厚度係大約7.5 nm,而在針對2.5 V之電源供應電壓所設計之MOS電晶體中,厚度係大約5.5 nm。然後,藉由使用一光阻圖案作為遮罩之蝕刻移除其中形成低電壓MOS電晶體之區域中的厚閘極絕緣膜25。
接著,在其中形成低電壓MOS電晶體之區域中形成薄閘極絕緣膜25。例如,在針對1.0 V所設計之MOS電晶體
中,厚度係大約1.2至1.8 nm。
閘極絕緣膜25可係藉由快速熱氧化(RTO)形成之熱氧化物膜或氮氧化物膜。此外,為進一步減小閘極洩漏,亦可能使用由以Hf為主或以Zr為主之氧化物製成之高介電膜。
接著,於閘極絕緣膜25上藉由LPCVD沈積構成閘極電極之多晶矽膜27。多晶矽膜27之厚度取決於技術節點,且在90-nm節點下係大約150至200 nm。此外,一般而言,鑑於程序可控制性,厚度傾向於隨節點而減小以便能不增大閘極縱橫比。
接著,雜質係植入至多晶矽膜27中以作為避免閘極空乏之措施。在此步驟中,使用光阻圖案作為遮罩,將磷(P)或砷(As)離子植入至NMOS區域中,並將硼(B)、氟化硼(BF2
)或銦(In)離子植入至PMOS區域中。植入劑量係大約1E15至1E16原子/cm2
。於此,術語"避免閘極空乏之措施"指對付措施,其用於對付的事實在於隨閘極絕緣膜之厚度減小,閘極絕緣膜之實體厚度與閘極多晶矽膜中之空乏層之厚度之影響變得不可忽略,且閘極膜之有效厚度不減小,而導致Tr.效能減低。
在此一情況中,為避免植入至多晶矽膜27中之雜質侵入閘極絕緣膜25下之區域,可結合植入氮(N2
)。
此外,作為避免閘極空乏之措施,可沈積SiGe多晶膜來替代用於構成閘極電極的多晶矽膜;可完全矽化閘極電極;或可使用金屬閘極。
接著,於多晶矽膜27上形成在閘極製造程序期間作為遮
罩之遮罩層29。作為遮罩層29,使用氧化矽膜、氮化矽膜或其類似物。遮罩層29之厚度係大約10至100 nm。
接著,如圖3C中顯示,藉由使用一光阻圖案作為遮罩之使用RIE系統或其類似物之蝕刻將遮罩層29圖案化成閘極電極形狀。完成蝕刻程序之後,移除該光阻圖案。
然後,使用RIE系統或其類似物透過圖案化遮罩層29蝕刻多晶矽膜27以形成由圖案化多晶矽膜27構成之閘極電極9。此外,在此程序中,亦可藉由蝕刻來圖案化閘極絕緣膜25。
接著,於閘極電極9之側壁上形成偏移間隔物31。在此步驟中,首先,沈積由TEOS膜、HTO膜、氮化矽膜或其類似物構成之偏移間隔物之絕緣膜,並使絕緣膜經受使用RIE系統之回蝕程序以獲得偏移間隔物31。藉由於閘極電極9之側壁上沈積偏移間隔物31,增大有效通道長度,並可減小短通道效應。此外,在形成偏移間隔物31之前,可能實施藉由RTO或其類似物氧化閘極電極之側壁的步驟。此步驟具有減低為寄生電容之閘極重疊電容之效果。
接著,於閘極電極9之側在半導體基板3之表面上執行囊袋植入(圖式中未顯示輪廓),並形成延伸擴散層33。在此步驟中,使用光阻圖案作為遮罩,對PMOS區域與NMOS區域中之每一者分別執行離子植入。
在PMOS區域中之囊袋植入中,植入約1E12至1E14原子/cm2
之劑量的砷(As)或磷(P)。在延伸擴散層33中,離子植入約1E15至2E15原子/cm2
之劑量的硼(B)、氟化硼(BF2
)
或銦(In)。
同時,在NMOS區域中之囊袋植入中,離子植入約1E12至1E14原子/cm2
之劑量的硼(B)、氟化硼(BF2
)或銦(In)。在延伸擴散層33中,離子植入約1E14至2E15原子/cm2
之劑量的砷(As)或磷(P)。此外,在對NMOS區域施加根據本發明之具體實施例之結構時,可省略延伸擴散層33之形成。
此外,在NMOS區域與PMOS區域上執行囊袋植入之前,為抑制植入時的通道作用,可(例如)藉由植入Ge執行預非晶化。此外,為減小可能在形成延伸擴散層33之後產生瞬間增強擴散(TED)或其類似物之植入缺陷,可額外執行在約800℃至900℃下之快速熱退火(RTA)處理。
圖3D中顯示之步驟係根據本發明之具體實施例之特性步驟中的一者。
此即,首先,藉由CVD依序形成具有約10 nm之厚度之氧化矽膜35與具有約50 nm之厚度之氮化矽膜37。儘管在圖式中未顯示,其上可進一步沈積氧化矽膜。
接著,藉由使用一光阻圖案(即,遮罩圖案,未顯示)之蝕刻使包括氧化矽膜35與氮化矽膜37之層壓膜經受圖案化。在此步驟中,使氧化矽膜35與氮化矽膜37經受圖案化使得在通道長度方向上具有預定寬度W之開口係穿透由包括氧化矽膜35與氮化矽膜37之層壓膜構成之側壁而提供於閘極電極9之兩側。從而,部分允許包括氧化矽膜35與氮化矽膜37之層壓膜在每一閘極電極9之每一側上使具有預定寬度W之部分保留於外側。
應注意,例如,採用相同標準之MOS電晶體以具有實質相同的預定寬度W。
接著,藉由使用光阻圖案作為遮罩之RIE執行凹陷蝕刻,其中使半導體基板3凹陷。從而,在半導體基板3之表面(井擴散層23)中形成具有預定寬度W之凹陷部分39。凹陷部分之深度係大約150 nm。源極/汲極區域之接面深度係藉由凹陷部分之深度及稍後執行之退火處理來決定。因此,隨著技術節點提升,縮小進行,且蝕刻深度減小。
完成蝕刻程序之後,移除該光阻圖案。
接著,如圖4A中顯示,在凹陷半導體基板3之表面上(即,在凹陷部分39中),形成由具有與半導體基板3不同之晶格常數之半導體材料構成的磊晶層11。
如上文中參考圖1所說明的,在PMOS區域中,磊晶層11使用具有比構成半導體基板3之矽(Si)大之晶格常數的矽鍺(SiGe)。在此程序中,NMOS區域係保持由氧化矽膜或包括氧化矽膜與氮化矽膜之層壓膜所覆蓋。含硼(B)之矽鍺(SiGe)係使用二氯矽烷(Si2H2
Cl2)、二硼烷(B2
H6
)、氯化氫(HCl)、氫(H2
)等作為氣體物種在600℃至800℃下磊晶成長。
同時,在NMOS區域中,磊晶層11使用具有比構成半導體基板3之矽(Si)小之晶格常數的矽碳(SiC)。在此程序中,PMOS區域係保持由氧化矽膜或包括氧化矽膜與氮化矽膜之層壓膜所覆蓋。含磷(P)之矽碳(SiC)係使用矽烷(SiH4
)、丙烷(C3
H6
)、膦(PH3
)、氯化氫(HCl)等作為氣體物
種在600℃至800℃下磊晶成長。
接著,如圖4B中顯示,使包括氧化矽膜35與氮化矽膜37之層壓膜經受回蝕程序以於閘極電極9之側形成側壁37a。從而,在作用區域7之部分中曝露半導體基板3之表面A。
接著,如圖4C中顯示,形成源極/汲極區域15。在此步驟中,使用光阻圖案作為遮罩,對PMOS區域與NMOS區域中之每一者分別執行離子植入。
在PMOS區域中,作為p型雜質,離子植入1E15至1E16原子/cm2
之劑量的硼(B)或氟化硼(BF2
)。
同時,在NMOS區域中,作為n型雜質,離子植入1E15至1E16原子/cm2
之劑量的砷(As)或磷(P)。
完成離子植入程序後,移除該等光阻圖案,並在約800℃至1,100℃下執行活化退火。使用RTA系統、尖波RTA系統或其類似物。
從而,獲得p型或n型MOS電晶體Tr,MOS電晶體中之每一者包括閘極電極9與佈置在閘極電極9之兩側之源極/汲極區域15,該等源極/汲極區域15各自包括其中擴散雜質之磊晶層11與擴散層13。
接著,如圖4D中顯示,藉由矽化曝露之矽表面形成矽化物層。在此步驟中,首先,在天然氧化物膜上執行濕式蝕刻處理,並使用濺鍍系統沈積約10 nm之厚度之(例如)由鎳(Ni)構成之金屬膜。然而,曝露之矽部分係藉由在約300℃至400℃下執行退火處理而矽化。在矽化後保留之金屬膜係藉由濕式蝕刻來移除。然後,在約500℃至600℃下執
行退火處理以形成由矽化鎳構成之矽化物層41。矽化物層41僅以自對準方式形成於由多晶矽構成之閘極電極9、由矽鍺(SiGe)構成之磊晶層11與由單晶矽構成之擴散層13上。
此外,作為金屬膜,除了鎳(Ni)之外可使用鈷(Co)、鈦(Ti)、鉑(Pt)、鎢(W)或其類似物。在此一情況中,獲得矽化鈷(CoSi2
)、矽化鈦(TiSi2
)、矽化鉑(PtSi)、矽化鎢(WSi2
)或其類似物。
接著,如圖5A中顯示,於閘極電極9、磊晶層11與擴散層13上形成由氮化矽構成之應力膜43。在此步驟中,形成不同應力膜43,使得拉伸應力係施加至其中佈置n型MOS電晶體Tr之區域且壓縮應力係施加至其中佈置p型MOS電晶體Tr之區域。
首先,作為應力膜43,藉由LPCVD、p-CVD或其類似物沈積約5至100 nm之厚度之賦予拉伸應力的氮化矽膜(拉伸Si3N4)。接著,作為處理應力膜43所使用之停止膜(未顯示),藉由CVD或其類似物沈積約100 nm之厚度的氧化矽膜(TEOS膜、PSG膜、BPSG膜、SOG膜或其類似物)。然後,藉由使用光阻圖案作為遮罩之蝕刻移除其中佈置p型MOS電晶體Tr之區域中的停止膜,並使用停止膜作為遮罩,移除應力膜43。在此階段中,pFET之側壁膜亦因蝕刻選擇性/過度蝕刻而移除。
從而,其中佈置n型MOS電晶體Tr之區域係由對通道區域ch施加拉伸應力之應力膜43所覆蓋。
接著,作為應力膜43,藉由CVD或其類似物沈積約5至100 nm之厚度之賦予壓縮應力的氮化矽膜(壓縮Si3N4)。然後,在其中佈置n型MOS電晶體Tr之區域中,移除此一賦予壓縮應力之應力膜43。
從而,其中佈置p型MOS電晶體Tr之區域係由對通道區域ch施加壓縮應力之應力膜43所覆蓋。
藉由上述步驟獲得具有與如圖1中顯示之結構相同之結構的半導體裝置1a。下文中將說明接續的步驟。
首先,如圖5B中顯示,藉由CVD沈積約100至1,000 nm之厚度之氧化矽膜45(如TEOS膜、PSG膜、BPSG膜或SOG膜),以便能覆蓋應力膜43,並藉由CMP執行平坦化。
接著,如圖5C中顯示,於氧化矽膜45與應力膜43中形成通道孔47以便能到達源極/汲極區域15之表面上的矽化物層41。在此步驟中,使用光阻圖案(未顯示)作為遮罩來執行RIE。藉由RIE形成通道孔47後,移除光阻圖案。
然後,如圖5D中顯示,藉由以導電材料填充通道孔47來形成接點49。在此步驟中,首先,藉由濺鍍或CVD沈積氮化鈦(TiN)/鈦(Ti)之層壓膜以作為阻障膜,且隨後藉由CVD沈積鎢(W)膜。鎢膜之厚度係大約100至500 nm。接著,使鎢膜經受CMP或回蝕程序,且從而藉由僅填充通道孔47之內側形成接點49。
接著,於氧化矽膜45上形成連接至接點49之互連線51。在此步驟中,首先,藉由濺鍍沈積鋁(Al)膜,且隨後藉由使用光阻圖案作為遮罩之RIE使鋁膜經受圖案蝕刻。從
而,形成由鋁製成的互連線51。作為互連線51之材料,可使用具有低電阻之銅(Cu)。
儘管在圖式中未顯示接續步驟,然而藉由在一或若干上層中形成互連線,可形成包括二層、三層、四層或四層以上之多層互連結構。從而,可能獲得具有多層互連結構的半導體裝置。
根據上述第一具體實施例,可能獲得其中源極/汲極區域15包括磊晶層11與擴散層13之半導體裝置1a。因此,可藉由改變擴散層13之寬度來調整磊晶層11之寬度。
因此,在參考圖3D所說明之步驟中,其中形成具有對應磊晶層之寬度之預定寬度W的凹陷部分39,藉由在不受作用區域7之閘極電極9之布局的影響下將凹陷部分39之寬度控制成預定寬度W,可能以考慮蝕刻期間之微負載效應之蝕刻深度形成凹陷部分39。明確地說,藉由將凹陷部分39之寬度設定成預定寬度W,可能獲得其中因抑制微負載效應導致蝕刻深度變動的凹陷部分39。
因此,可控制於凹陷部分39中形成之磊晶層11之深度而使其一致。
此外,由於磊晶層11之形成面積(布局面積)係在不受布局之影響下,因對應之擴散層13之部分而減小,故而可能獲得具有小數目結晶缺陷之磊晶層11。
因此,可能藉由具有控制預定深度之磊晶層11來抑制對閘極電極9下之通道區域ch所施加之應力的變動。此外,由於可在不受布局影響下獲得具有小數目之結晶缺陷的磊
晶層11,故而可減小接面洩漏。因此,能夠提升電晶體Tr的特性。
此外,儘管藉由運用此一結構減小磊晶層11之體積,然而可能藉由將磊晶層11之深度設定在特定值來維持對通道區域ch所施加之應力(參考K. Ota等人,"Scalable eSiGe S/D technology with less layout dependence for 45-nm generation",2006年VLSI技術研討會技術論文輯要,2006年)。
此外,如上所述,由於藉由對應之擴散層13之部分減小磊晶層11之形成面積(布局面積),故而使覆蓋磊晶層11外側之側壁的應力膜43接近通道區域ch。從而,可增強應力膜43對通道區域ch施加應力的效果。
圖6係顯示根據本發明之第二具體實施例之半導體裝置之結構的示意性剖面圖。圖6中顯示之半導體裝置1b具有與根據第一具體實施例於圖1中顯示之半導體裝置1a相同的結構,除了構成源極/汲極區域15之擴散層13的深度係大於磊晶層11之深度外。
在具有此一結構之半導體裝置1b中,除了第一具體實施例之效果外,藉由增大相對於閘極電極9之位於磊晶層11外側之擴散層13之深度,在減小短通道效應之同時,可減小於p-n接面之空乏層的電場,因而可進一步提升接面洩漏。此外,藉由增大擴散層13之深度,減小於接面之基板雜質濃度。因此,可減小接面電容,並可提升MOS電晶體
Tr之操作速度。
圖7係顯示根據本發明之第三具體實施例之半導體裝置之結構的示意性剖面圖。圖7中顯示之半導體裝置1c具有與根據第一具體實施例於圖1中顯示之半導體裝置1a相同的結構,除了構成源極/汲極區域15之擴散層13之表面之高度係低於閘極電極9下之半導體基板3之表面之高度外。
在具有此一結構之半導體裝置1c中,覆蓋電晶體Tr之應力膜43係延伸至低於通道區域ch之位置。從而,除了第一具體實施例之效果外,可增強由應力膜43對通道區域ch施加應力的效果。
圖8係顯示根據本發明之第四具體實施例之半導體裝置之結構的示意性剖面圖。圖8中顯示之半導體裝置61a具有具備p型MOS電晶體Tr之結構。半導體裝置61a與根據第一具體實施例於圖1中顯示之半導體裝置1a之不同在於僅源極/汲極區域15中之一者包括磊晶層11,且源極/汲極區域15中之另一者僅包括擴散層13。此外,相反電導係數類型(n型)之擴散層(相反電導係數類型擴散層63)係毗鄰擴散層13來佈置。將省略對與第一具體實施例之結構相同之結構的重複說明。
在半導體裝置61a中,提供相反電導係數類型擴散層63以作為相對於井擴散層23之接點區域。相反電導係數類型擴散層63與毗鄰其而佈置之源極/汲極區域15係因佈置於
其表面上之矽化物層41而短路。在半導體裝置61a中,藉由運用此一結構,減小井接點。
在此一結構中,由於擴散層13構成毗鄰相對於井擴散層23(相反電導係數類型擴散層63)之接點區域來佈置並對該接點區域短路之源極/汲極區域15,故而可能避免相反電導係數類型擴散層63中之n型雜質擴散至源極/汲極區域15中並到達通道區域ch。
此即,如圖9之比較性範例中顯示,在其中由矽鍺(SiGe)構成之磊晶層11構成毗鄰相反電導係數類型擴散層63而佈置之源極/汲極區域15的情況中,於相反電導係數類型擴散層63中之n型雜質輕易地擴散至磊晶層11中並到達通道區域ch。如此之理由在於n型雜質之擴散率在SiGe中係高於在由矽構成之半導體基板中(即,在砷(As)之情況中高出大約七倍,且在磷(P)之情況中高出大約兩倍)。
因此,如圖8中顯示,藉由運用其中僅源極/汲極區域15中之一者包括磊晶層11且毗鄰相反電導係數類型擴散層63而佈置之源極/汲極區域15中之另一者包括擴散層13的結構,可能避免相反電導係數類型擴散層63中之n型雜質擴散至通道區域ch中,並可抑制p型MOS電晶體Tr之臨限值的變動。
圖10係顯示根據本發明之第五具體實施例之半導體裝置之結構的示意性剖面圖。圖10中顯示之半導體裝置61b具有與根據第四具體實施例之半導體裝置61a相同之結構,
除了源極/汲極區域15中之一者包括與磊晶層11在一起之擴散層13外。
在此一情況中,擴散層13係穿透磊晶層11而佈置在閘極電極9之側。
藉由運用此一結構,磊晶層11在通道長度方向上之寬度可設定成受擴散層13控制之預定寬度W。因此,可獲得與第一具體實施例相同的效果。
習知此項技術者應瞭解,可根據設計要求及其他因素進行各種修改、組合、次組合及變更,只要其係在隨附申請專利範圍或其等效內容的範疇內即可。
1a‧‧‧半導體裝置
1b‧‧‧半導體裝置
1c‧‧‧半導體裝置
3‧‧‧半導體基板
3a‧‧‧溝渠
5‧‧‧隔離膜
7‧‧‧隔離作用區域
9‧‧‧閘極電極
11‧‧‧磊晶層
13‧‧‧擴散層
15‧‧‧源極/汲極區域
21‧‧‧襯墊氧化物膜
22‧‧‧氮化矽膜
22a‧‧‧開口
23‧‧‧井擴散層
25‧‧‧閘極絕緣膜
27‧‧‧多晶矽膜
29‧‧‧遮罩層
31‧‧‧偏移間隔物
33‧‧‧延伸擴散層
35‧‧‧氧化矽膜
37‧‧‧氮化矽膜
37a‧‧‧側壁
39‧‧‧凹陷部分
41‧‧‧矽化物層
43‧‧‧應力膜
45‧‧‧氧化矽膜
47‧‧‧通道孔
49‧‧‧接點
51‧‧‧互連線
61a‧‧‧半導體裝置
61b‧‧‧半導體裝置
63‧‧‧相反電導係數類型擴散層
101‧‧‧半導體基板
102‧‧‧隔離膜
103‧‧‧隔離作用區域
104‧‧‧閘極電極
105‧‧‧磊晶層
A‧‧‧表面
ch‧‧‧通道區域
Tr‧‧‧電晶體
圖1係顯示根據本發明之第一具體實施例之半導體裝置之結構的示意性剖面圖;圖2A至2E係顯示根據第一具體實施例之製造半導體裝置之方法中之步驟的示意性剖面圖;圖3A至3D係顯示根據第一具體實施例之製造半導體裝置之方法中接續圖2E中顯示之步驟之步驟的示意性剖面圖;圖4A至4D係顯示根據第一具體實施例之製造半導體裝置之方法中接續圖3D中顯示之步驟之步驟的示意性剖面圖;圖5A至5D係顯示接續圖4D中顯示之步驟之步驟的示意性剖面圖;圖6係顯示根據本發明之第二具體實施例之半導體裝置
之結構的示意性剖面圖;圖7係顯示根據本發明之第三具體實施例之半導體裝置之結構的示意性剖面圖;圖8係顯示根據本發明之第四具體實施例之半導體裝置之結構的示意性剖面圖;圖9係顯示第四具體實施例之比較性範例的示意性剖面圖;圖10係顯示根據本發明之第五具體實施例之半導體裝置之結構的示意性剖面圖;以及圖11係顯示根據先前技術之半導體裝置之結構的示意性剖面圖。
1a‧‧‧半導體裝置
3‧‧‧半導體基板
5‧‧‧隔離膜
7‧‧‧隔離作用區域
9‧‧‧閘極電極
11‧‧‧磊晶層
13‧‧‧擴散層
15‧‧‧源極/汲極區域
23‧‧‧井擴散層
43‧‧‧應力膜
ch‧‧‧通道區域
Tr‧‧‧電晶體
Claims (5)
- 一種半導體裝置,其包含:一閘極電極,其佈置於一半導體基板上;以及源極/汲極區域,其佈置於該閘極電極之兩側,該等源極/汲極區域係由植入雜質形成,其中該等源極/汲極區域包括一磊晶層,其藉由於該閘極電極之一側及/或另一側之一凹陷位置中磊晶成長具有與該半導體基板不同之晶格常數的一半導體材料而形成,以及一擴散層,其佈置於該半導體基板之一表面層中;該擴散層相對該閘極電極係佈置於該磊晶層外側,且該擴散層之深度係較該磊晶層之深度為深。
- 如請求項1之半導體裝置,其中該磊晶層係於該閘極電極之兩側中之每一者均佈置。
- 如請求項2之半導體裝置,其中該磊晶層係在該半導體裝置之通道長度方向上以一預定寬度佈置。
- 如請求項2之半導體裝置,其中該擴散層之表面之高度係低於位在閘極電極下之半導體基板的表面之高度。
- 一種製造一半導體裝置之方法,其包含:一第一步驟,其於一半導體基板上形成一閘極電極;一第二步驟,其藉由透過一遮罩圖案之蝕刻於該閘極電極之一側及/或另一側使該半導體基板之一表面層凹陷;一第三步驟,其於凹陷部分上形成由具有與該半導體 基板不同之晶格常數的半導體材料構成之磊晶層;以及一第四步驟,其藉由移除該遮罩圖案以曝露該半導體基板之表面層並使雜質擴散至該磊晶層及該半導體基板之表面層中來形成源極/汲極區域,該等源極/汲極區域包括其中雜質經擴散之磊晶層與藉由使雜質擴散至該表面層中而形成之一擴散層;該第四步驟中係使該擴散層相對該閘極電極佈置於該磊晶層外側,且使該擴散層之深度較該磊晶層之深度為深。
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2008
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- 2008-06-11 US US12/137,112 patent/US8039901B2/en active Active
- 2008-06-26 KR KR1020080060865A patent/KR101475364B1/ko active IP Right Grant
- 2008-06-27 CN CN2008101317526A patent/CN101335299B/zh active Active
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2011
- 2011-09-21 US US13/238,580 patent/US8486793B2/en active Active
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2013
- 2013-06-07 US US13/913,012 patent/US9070704B2/en active Active
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2015
- 2015-03-19 US US14/662,351 patent/US9356146B2/en active Active
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2016
- 2016-04-22 US US15/136,091 patent/US20160240674A1/en not_active Abandoned
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2021
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TW200908325A (en) | 2009-02-16 |
US20160240674A1 (en) | 2016-08-18 |
US9356146B2 (en) | 2016-05-31 |
US9070704B2 (en) | 2015-06-30 |
US8039901B2 (en) | 2011-10-18 |
US8486793B2 (en) | 2013-07-16 |
CN101335299A (zh) | 2008-12-31 |
CN101335299B (zh) | 2010-06-23 |
US20150194526A1 (en) | 2015-07-09 |
KR101475364B1 (ko) | 2014-12-22 |
US20120009753A1 (en) | 2012-01-12 |
KR20080114608A (ko) | 2008-12-31 |
US20090001420A1 (en) | 2009-01-01 |
US20220029018A1 (en) | 2022-01-27 |
JP2009010111A (ja) | 2009-01-15 |
JP5286701B2 (ja) | 2013-09-11 |
US20130295741A1 (en) | 2013-11-07 |
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