CN101335299B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101335299B
CN101335299B CN2008101317526A CN200810131752A CN101335299B CN 101335299 B CN101335299 B CN 101335299B CN 2008101317526 A CN2008101317526 A CN 2008101317526A CN 200810131752 A CN200810131752 A CN 200810131752A CN 101335299 B CN101335299 B CN 101335299B
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epitaxial loayer
diffusion layer
semiconductor device
semiconductor substrate
gate electrode
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CN101335299A (zh
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松本拓治
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Sony Corp
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Abstract

本发明提供半导体装置，其包括设置在半导体基板上的栅电极和设置在栅电极两侧上的源/漏区域，该源/漏区域通过注入杂质形成。该源/漏区域包括外延层和扩散层，该外延层通过在栅电极侧部上的凹入位置中外延生长晶格常数不同于半导体基板材料的晶格常数的半导体材料形成，而该扩散层设置在半导体基板的表面层中。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置以及制造半导体装置的方法。特别是，本发明涉及这样的半导体及其制造方法：其中具有不同晶格常数的半导体材料在栅电极侧外延生长在凹入部分中。
背景技术
在设置有MOS晶体管的半导体装置中，已经积极地采用通过给半导体基板的沟道区域施加应力而改善载流子迁移率的技术。作为该技术之一，已经提出采用图11所示的结构。在该结构中，半导体基板101的表面通过隔离膜102隔离，并且栅电极104设置为延伸以横截隔离的有源区域103，而凹入部分设置在栅电极104的两侧。由具有与半导体基板101的晶格常数不同的晶格常数的半导体材料组成的外延层105设置在凹入部分中，并且用作源/漏区域。
在这样的情况下，例如，在p型MOS(PMOS)晶体管中，比构成半导体基板101的硅(Si)具有更大的晶格常数的硅锗(SiGe)生长成外延层105。由此，给沟道区域ch施加压应力，并且改善载流子迁移率。例如，参照日本未审查专利申请公开No.2006-165012(专利文件1)。
同样，在n型MOS(NMOS)晶体管中，比构成半导体基板101的硅(Si)具有更小的晶格常数的碳化硅(SiC)生长在外延层105中。由此，给沟道区域ch施加拉应力，并且改善载流子迁移率。例如，参照Kah Wee Ang等″Enhanced Performance in 50nm N-MOSFETs with Silicon-CarbonSource/Drain Regions(在具有碳化硅源/漏区域的50nm N-MOSFET中提高性能)″，IEDM Tech.Dig.，1069-1071，2004年12月(非专利文件1)。
在具有上述结构的半导体装置中，为了保证晶体管的特性彼此相等，重要的是抑制施加给沟道区域的应力上的变化。施加给沟道区域的应力通过外延层的深度即形成在半导体基板中的凹入部分的深度来控制。
然而，半导体基板中凹入部分的深度随着凹入部分的面积的减少而减少，这是由在半导体基板中形成凹入部分的蚀刻工艺期间产生的微载荷效应引起的。因此，外延层的深度的变化依赖于半导体基板上(在有源区域中)的栅电极的布局。
此外，关于由硅锗(SiGe)组成的外延层，随着布局面积的增加，结晶缺陷的数量增加，导致结泄漏的增加。
此外，在MOS晶体管中，布局面积可以通过采用这样的结构来降低：其中相反导电类型的扩散层与源和漏区域之一相邻设置，并且源和漏区域之一与相反导电类型的扩散层通过布置为表面层的硅化物层短路。在该结构中，若由硅锗(SiGe)组成的外延层用于PMOS晶体管的源/漏区域，则通过在半导体基板的表面层中扩散n型杂质例如砷(As)或者磷(P)形成的n型扩散层形成相反导电类型的扩散层。
然而，n型杂质在SiGe中的扩散率高于在由硅组成的半导体基板中的扩散率，即在砷(As)的情况下，约为七倍高，而在磷(P)的情况下，约为二倍高。因此，相反类型导电类型的扩散层(n型扩散层)中的n型杂质扩散进入相邻的源/漏区域(SiGe组成的外延层)中，并且易于到达沟道区域，因此增加了MOS晶体管的阈值。
因此所希望的是提供包括外延层的半导体装置，外延层的深度被控制而不依赖于布局，并且其中防止结晶缺陷的产生，因此能够改善特性，并且提供制造该半导体装置的方法。
发明内容
根据本发明的实施例，半导体装置包括设置在半导体基板上的栅电极和设置在栅电极的两侧的源/漏区域，该源/漏区域通过注入杂质形成。该源/漏区域包括外延层和扩散层，该外延层通过在该栅电极的侧部的凹入位置中外延生长晶格常数不同于半导体基板材料的晶格常数的半导体材料而形成，而该扩散层设置在半导体基板的表面层中。外延层的上表面高于半导体基底的表面。
根据本发明的另一个实施例，制造半导体装置的方法包括：第一步骤，在半导体基板上形成栅电极；第二步骤，通过掩膜图案蚀刻，在该栅电极的侧部凹陷形成该半导体基板的表面层；第三步骤，在该半导体基板的凹入部分上形成由晶格常数不同于该半导体基板材料的晶格常数的半导体材料组成的外延层；以及第四步骤，通过去除该掩膜图案来暴露该半导体基板的该表面层并且使杂质扩散进入该外延层和该半导体基板的该表面层来形成源/漏区域，该源/漏区域包括扩散有杂质的该外延层和通过在该表面层中扩散杂质形成的扩散层。所述外延层的上表面高于半导体基底的表面。
在根据本发明实施例的半导体装置和制造该半导体装置的方法中，该源/漏区域包括外延层和扩散层。因此，外延层的宽度通过改变扩散层的宽度来调整。因此，不依赖于布局，可以控制半导体基板的将要形成外延层的凹入部分的宽度，并且控制通过蚀刻凹陷形成的凹入部分的深度。因此，例如，通过改变扩散层的宽度来设定外延层的宽度为预定值，设置有外延层的半导体基板的凹入部分的深度被均等化，而不依赖于布局。此外，因为外延层的形成区域(布局区域)通过对应于扩散层的部分减少，而不依赖于布局，因此能够获得具有小量结晶缺陷的外延层。
如上所述，根据本发明的实施例，设置有外延层的半导体基板的凹入部分的深度可以得到控制，而不依赖于布局。因此，通过深度受控制的外延层能够抑制施加给栅电极下面的沟道区域的应力的变化。此外，因为可以获得具有小量结晶缺陷的外延层而不依赖于布局，所以可以减少结泄漏。从而可以改善半导体装置的特性。
附图说明
图1是显示根据本发明第一实施例的半导体结构的示意性截面图；
图2A至2E是显示制造根据本发明第一实施例的半导体装置的方法中的步骤的示意性截面图；
图3A至3D是显示在制造根据第一实施例的半导体装置的方法中图2E所示步骤的后续步骤的示意性截面图；
图4A至4D是显示在制造根据第一实施例的半导体装置的方法中图3D所示步骤的后续步骤的示意性截面图；
图5A至5D是显示图4D所示步骤的后续步骤的示意性截面图；
图6是显示根据本发明第二实施例的半导体装置的结构的示意性截面图；
图7是显示根据本发明第三实施例的半导体装置的结构的示意性截面图；
图8是显示根据本发明第四实施例的半导体装置的结构的示意性截面图；
图9是显示第四实施例的比较实例的示意性截面图；
图10是显示根据本发明第五实施例的半导体装置的结构的示意性截面图；和
图11是显示根据相关技术的半导体装置的结构的示意性截面图。
具体实施方式
下面，将参照附图详细描述本发明的实施例。这里，将描述具有设置在基板上的多个MOS晶体管的半导体装置的结构。
第一实施例
图1是显示根据第一实施例的半导体装置的结构的示意性截面图。在图1所示的半导体装置1a中，由硅(Si)组成的半导体基板3的表面由隔离膜5隔离，并且栅电极9设置为延伸以横截隔离的有源区域7。在栅电极9的两侧，半导体基板3的表面凹入。由具有不同于半导体基板3的半导体材料的晶格常数的晶格常数组成的外延层11设置在该凹入部分中，并且在该外延层11中扩散杂质。此外，相对于栅电极9，扩散层13设置在外延层11的外侧，该扩散层13通过在半导体基板3的表面层中扩散杂质形成。
在第一实施例中，在栅电极9的两侧，杂质扩散进入其中的外延层11和扩散层构成源/漏区域15。
设置在每个栅电极9的两侧每侧上的外延层形成为具有通过相应的扩散层13控制的预定厚度W。例如，相同标准的MOS晶体管假定沿沟道长度方向具有基本相同的预定厚度W。因此，扩散层13仅部分地设置在外延层11的外侧，从而外延层11具有相同的宽度。此外，外延层11的沿沟道长度方向的预定宽度W约为10至100nm。
在设置在半导体装置1a上的MOS晶体管中的p型MOS(PMOS)晶体管中，晶格常数大于构成半导体基板3的硅(Si)的晶格常数的硅锗(SiGe)用于外延层11。由此，给沟道区域ch施加压应力。
同样，在半导体装置1a上设置的MOS晶体管中的n型MOS(NMOS)晶体管中，晶格常数小于构成半导体基板3的硅(Si)的晶格常数的碳化硅(SiC)用于外延层11。由此，给沟道区域ch施加拉应力。
接下来，将参照图2A至5D来描述半导体装置1a的详细的结构。
首先，如图2A所示，准备由单晶硅组成的半导体基板3。半导体基板3具有例如约10mmΩ·cm的电阻率。作为半导体基板3，可以采用绝缘体上硅(SOI)或者包括SiGe层的基板，只要基板的表面层由单晶硅组成。
接下来，厚度约为15nm的焊盘氧化物膜21通过在半导体基板3的表面层上实行热氧化而形成。然后，厚度约为160nm的氮化硅膜22通过低压CVD(LP-CVD)沉积而成。除了氮化硅膜22设置在焊盘氧化物膜21上的结构外，也可以采用氮化硅膜设置在多晶硅膜上的结构，或者采用氮化硅膜设置在焊盘氧化物膜上的结构。
接下来，如图2B所示，对应于隔离膜形成部分的开口22a形成在氮化硅膜22和焊盘氧化物膜21中。这里，通过光刻形成抗蚀剂图案(未示出)，并且采用抗蚀剂图案为掩膜，蚀刻氮化硅膜22和焊盘氧化物膜21。为了执行蚀刻工艺，采用反应离子蚀刻(RIE)系统和电子回旋共振(ECR)系统等。在蚀刻工艺后，采用灰化系统等去除抗蚀剂图案。
接下来，如图2C所示，采用设置有开口22a的氮化硅膜22作为掩膜蚀刻半导体基板3，并且由此在半导体基板3中形成用于形成隔离膜的沟槽3a。沟槽3a的深度约为0.3μm。为了执行蚀刻工艺，采用反应离子蚀刻(RIE)系统和电子回旋共振(ECR，electron cyclotron resonance)系统等。
在此状态下，通过执行热氧化工艺，形成厚度约为4至10nm的衬底氧化物膜(未示出)。在约800℃至900℃下执行热氧化工艺。衬底氧化物膜可以是包含氮的氧化物膜。可以通过CVD沉积氮化物膜来代替衬底氧化物膜。
接下来，如图2D所示，通过用绝缘膜填充沟槽3a来形成隔离膜5，并且半导体基板3的表面分隔成多个有源区域7。隔离膜5这样形成：沉积绝缘膜，例如沉积高密度等离子(HDP)氧化膜、如旋涂玻璃(SOG，spin-on-glass)膜的无机膜或者有机氧化物膜等，以便填充沟槽3a，然后通过化学机械抛光(CMP)抛光该绝缘膜，直到暴露氮化硅膜22。
接下来，如图2E所示，为了调整隔离膜5相对于半导体基板3的表面的高度，填充在沟槽3a中的绝缘膜(例如，氧化物膜)受到湿蚀刻。蚀刻厚度例如约为40至100nm。接下来，用热磷酸去除氮化硅膜22以暴露焊盘氧化物膜21。
接下来，如图3A所示，阱扩散层23形成在半导体基板3的表面层中，并且执行沟道掺杂。这里，采用抗蚀剂图案作为掩膜，分别对每个形成p型MOS晶体管的区域(在下文称为“PMOS区域”)和形成n型MOS晶体管的区域(在下文称为“NMOS区域”)执行离子掺杂。
在PMOS区域中，形成n型阱扩散层23。在此情况下，磷(P)离子以约1E13atoms/cm2的剂量用200KeV的注入能量注入。此外，在沟道掺杂中，砷(As)离子以约1E11至2E13atoms/cm2用100keV的注入能量注入。
同样，在NMOS区域中，形成p型阱扩散层23。在此情况下，硼(B)离子以约1E13atoms/cm2的剂量用200KeV的注入能量注入。此外，在沟道掺杂中，硼(B)离子以约1E11至2E13atoms/cm2的剂量用10至20keV的注入能量注入。
在完成离子注入工艺后，去除抗蚀剂图案。此外，通过湿蚀刻去除焊盘氧化物膜21。
接下来，如图3B所示，栅极绝缘膜25形成在半导体基板3的表面之上。在该工艺中，厚栅极绝缘膜25形成在形成高电压MOS晶体管的区域中，而薄栅极绝缘膜25形成在形成低电压MOS晶体管的区域中。
首先，形成由氧化硅组成的厚栅极绝缘膜25。例如，在电源电压设计为3.3V的MOS晶体管中，厚度约为7.5nm，而在电源电压设计为2.5V的MOS晶体管中，厚度约为5.5nm。然后，通过以抗蚀剂图案为掩膜进行蚀刻，去除形成在低电压MOS晶体管区域中的厚栅极绝缘膜25。
接下来，薄栅极绝缘膜25形成在形成低电压MOS晶体管的区域中，来形成薄栅极绝缘膜25。例如，在设计为1.0V的MOS晶体管中，厚度约为1.2至1.8nm。
栅极绝缘膜25可以是通过快速热氧化(RTO)形成的热氧化膜或者氧氮化物膜。此外，为了进一步减少栅极泄漏，也可以采用由Hf基或者Zr基氧化物制造的高介电膜。
接下来，用于构成栅电极的多晶硅膜27通过LPCVD沉积在栅极绝缘膜25上。多晶硅膜28的厚度依赖于工艺节点(technology node)，在90-nm节点上约为150至200nm。此外，通常考虑到工艺控制能力，厚度倾向于随着节点而减少，以便不增加栅极的纵横比(aspect ratio)。
接下来，将杂质注入多晶硅膜27，以防止栅极损耗。在该步骤中，采用抗蚀剂图案为掩膜，磷(P)或者砷(As)离子注入NMOS区域，而硼(B)、氟化硼(BF2)或者铟(In)离子注入PMOS区域。注入剂量约为1E15至1E16atoms/cm2。这里，“防止栅极损耗”是指防止这样的事实：随着栅极绝缘膜厚度的减少，不仅关于栅极绝缘膜的物理厚度而且关于栅极多晶硅膜中的耗尽层的厚度的影响变为不可忽视，并且栅极膜的有效厚度没有减少，导致晶体管性能下降。
在这样的情况下，为了防止注入多晶硅27中的杂质渗透到栅极绝缘膜25下面的区域，可以结合注入氮(N2)。
此外，为了防止栅极损耗，可以沉积SiGe多晶膜，代替构造栅电极的多晶硅膜；栅电极可以完全硅化；或者可以采用金属栅极。
接下来，在栅极制造工艺期间用作掩膜的掩膜层29形成在多晶硅膜27上。作为掩膜层29，采用氧化硅膜或者氮化硅膜等。掩膜层29的厚度约为10至100nm。
接下来，如图3C所示，以抗蚀剂图案为掩膜，通过RIE系统等蚀刻，将掩膜层29构图形成栅电极的形状。在完成蚀刻工艺后，去除抗蚀剂图案。
然后，采用RIE系统等通过图案化的掩膜层29蚀刻多晶硅膜27，以形成由图案化的多晶硅膜27组成的栅电极9。此外，在该工艺中，也可以通过蚀刻图案化栅极绝缘膜25。
接下来，弥补垫(offset spacers)31形成在栅电极9的侧壁上。在该步骤中，首先，沉积由TEOS膜、HTO膜或氮化硅膜等组成的弥补垫用绝缘膜，并且采用RIE系统对绝缘膜实行回蚀刻工艺以获得弥补垫31。通过在栅电极9的侧壁上沉积弥补垫31，增加了有效沟道长度，并且可以减少短沟道效应。此外，在形成弥补垫31前，可以通过RTO等进行氧化栅电极侧壁的步骤。该步骤具有减少栅极重叠电容的效果，该栅极重叠电容为寄生电容。
接下来，在栅电极9两侧上的半导体基板3的表面上执行袋注入(pocketimplantation)(在附图中未示出分布)，并且形成延伸的扩散层33。在该步骤中，采用抗蚀剂图案为掩膜，分别为每个PMOS区域和NMOS区域进行离子注入。
在PMOS区域中实行袋注入时，以约为1E12至1E14atoms/cm2的剂量注入砷(As)或磷(P)。在延伸扩散层33中，以约为1E15至2E15atoms/cm2的剂量离子注入硼(B)、氟化硼(BF2)或者铟(In)。
同样，在NMOS区域中实行袋注入时，以约为1E12至1E14atoms/cm2的剂量离子注入硼(B)、氟化硼(BF2)或者铟(In)。在延伸扩散层33中，以约为1E14至2E15atoms/cm2的剂量离子注入砷(As)或磷(P)。另外，当根据本发明实施例的结构应用到NMOS区域时，可以省略形成延伸扩散层33。
此外，当在NMOS区域和PMOS区域上执行袋注入前，为了抑制注入的沟道影响(channeling)，可以通过例如注入Ge执行预非晶化(pre-amorphization)。在形成延伸扩散层33后，为了减少会引起瞬时增加扩散(TED)等的注入缺陷，可以附加执行约800℃至900℃的快速热退火(RTA)。
图3D所示步骤是根据本发明实施例的特征性步骤之一。
就是说，首先，厚度约为10nm的氧化硅35和厚度约为50nm的氮化硅膜37依次通过CVD形成。尽管附图中没有示出，但是还可以在其上进一步形成氧化硅膜。
接下来，包括氧化硅膜35和氮化硅膜37的层叠膜通过采用抗蚀剂图案(即掩膜图案，未示出)的蚀刻而被构图。在该步骤中，氧化硅膜35和氮化硅膜37被构图，使得沿沟道长度方向具有预定宽度W的开口通过由包括氧化硅膜35和氮化硅膜37的层叠膜组成的侧壁设置在栅电极9的两侧。由此，包括氧化硅膜35和氮化硅膜37的层叠膜被部分地允许残留在每个栅电极9的每侧上具有预定宽度W的部分的外侧。
应当注意的是，例如，同样标准的MOS晶体管假定具有基本上相同的预定宽度W。
接下来，采用抗蚀剂图案为掩膜通过RIE执行凹入蚀刻，其中在半导体基板3形成凹陷。由此，具有预定宽度W的凹入部分39形成在半导体基板3的表面中(阱扩散层23)。凹入部分的深度约为150nm。源/漏区域的结深度由凹入部分的深度和稍后执行的退火处理决定。因此，由于工艺节点提前，实现了最小化，并且减少了蚀刻深度。
在执行蚀刻工艺后，去除抗蚀剂图案。
接下来，如图4A所示，在凹入的半导体基板3的表面上，即在凹入部分39中，形成外延层11，该外延层11由晶格常数与半导体基板3的半导体材料的晶格常数不同的半导体材料组成。
如参考图1所描述，在PMOS区域中，晶格常数大于构成半导体基板3的硅(Si)的晶格常数的硅锗(SiGe)用于外延层11。在此工艺中，NMOS区域保持覆盖有氧化硅膜或者包括氧化硅膜和氮化硅膜的层叠膜。包含硼(B)的硅锗(SiGe)通过在600℃至800℃下采用二氯二氢硅(Si2H2Cl2)、乙硼烷(B2H6)、氯化氢(HCl)、氢(H2)等作为气体种类得以外延生长。
同样，在NMOS区域中，晶格常数比构成半导体基板3的硅(Si)的晶格常数小的碳化硅(SiC)用于外延层11。在该工艺中，PMOS区域保持覆盖有氧化硅膜或者包括氧化硅膜和氮化硅膜的层叠膜。包含磷(P)的碳化硅(SiC)通过在600℃至800℃下采用硅烷(SiH4)、丙烷(C3H6)、磷化氢(PH3)、氯化氢(HCl)等作为气体种类得以外延生长。
接下来，如图4B所示，对包括氧化硅膜35和氮化硅膜37的层叠膜实行回蚀刻工艺，以在栅电极9侧部上形成侧壁37a。由此，半导体基板3的表面A暴露在有源区域7的部分中。
接下来，如图4C所示，形成源/漏区域15。在该步骤中，采用抗蚀剂图案为掩膜，分别为每个PMOS区域和NMOS区域执行离子注入。
在PMOS区域中，作为p型杂质，硼(B)或氟化硼(BF2)以1E15至1E16atoms/cm2的剂量离子注入。
同样，在NMOS区域中，作为n型杂质，砷(As)或磷(P)以1E15至1E16atoms/cm2的剂量离子注入。
在执行离子注入工艺后，去除抗蚀剂图案，并且在约800℃至1000℃下执行活化退火(activation annealing)处理。采用RTA系统或spike-RTA系统等。
由此，获得p型或者n型MOS晶体管Tr，每个MOS晶体管都包括栅电极9和设置在栅电极9的两侧上的源/漏区域15，每个源/漏区域15都包括扩散有杂质的外延层11和扩散层13。
接下来，如图4D所示，通过硅化暴露的硅表面而形成硅化物层。在该步骤中，首先，在该氧化物膜上执行湿蚀刻，并且采用溅射系统，沉积厚度约为10nm的例如由镍(Ni)组成的金属膜。然后，暴露的硅部分通过执行300℃至400℃的退火处理而被硅化。通过湿蚀刻去除硅化后残留的金属膜。然后，在约500℃至600℃下执行退火处理，以形成由硅化镍组成的硅化物层41。硅化物层41以自对准方式仅形成在由多晶硅组成的栅电极9、由硅锗(SiGe)组成的外延层11和由单晶硅组成的扩散层13上。
此外，作为金属膜，除镍(Ni)外，可以采用钴(Co)、钛(Ti)、铂(Pt)或钨(W)等。在此情况下，获得硅化钴(CoSi2)、硅化钛(TiSi2)、硅化铂(PtSi)或硅化钨(WSi2)等。
接下来，如图5A所示，由氮化硅组成的应力膜43形成在栅电极9、外延层11和扩散层13上。在该步骤中，形成不同的应力膜43，从而拉应力施加给设置p型MOS晶体管Tr的区域，而压应力施加给设置p型MOS晶体管Tr的区域。
首先，作为应力膜43，通过LPCVD或p-CVD等，沉积厚度约为5至100nm的施加拉应力的氮化硅膜(拉伸Si3N4)。接下来，作为用于加工应力膜43的阻挡膜(未示出)，通过CVD等，沉积厚度约为100nm的氧化硅膜(TEOS膜、PSG膜、BPSG膜或SOG膜等)。然后，采用抗蚀剂图案为掩膜，通过蚀刻去除处于设置p型MOS晶体管Tr的区域中的阻挡膜，并且采用阻挡膜为掩膜，去除应力膜43。在此阶段中，pFET的侧壁膜也由于蚀刻选择性/过蚀刻而去除。
由此，设置n型MOS晶体管的区域被向沟道区域ch施加拉应力的应力膜43覆盖。
接下来，作为应力膜43，通过CVD等沉积厚度约为5至100nm的施加压应力的氮化硅膜(压缩Si3N4)。然后，在设置n型MOS晶体管Tr的区域中，去除施加压应力的应力膜43。
由此，设置p型MOS晶体管Tr的区域覆盖有给沟道区域ch施加压应力的应力膜43。
通过上述步骤获得与图1所示的结构相同的半导体装置1a。
首先，如图5B所示，通过CVD沉积厚度约为100至1,000nm的氧化硅膜45，例如TEOS膜、PSG膜、BPSG膜或者SOG膜，以覆盖应力膜43，并且通过CMP执行平坦化。
接下来，如图5C所示，通孔47形成在氧化硅膜45和应力膜43中，以便到达源/漏区域15的表面上的硅化物层41。在该步骤中，采用抗蚀剂图案(未示出)为掩膜执行RIE。在通过RIE形成通孔47后，去除抗蚀剂图案。
然后，如图5D所示，通过以导电材料填充通孔27形成触点49。在该步骤中，首先，氮化钛(TiN)/钛(Ti)的层叠膜通过溅射或者CVD沉积为阻挡膜，然后通过CVD沉积钨(W)膜。钨膜的厚度约为100至500nm。接下来，钨膜受到CMP或者回蚀刻，并且由此通过仅填充通孔47的内侧而形成触点49。
接下来，连接到触点49的互连线51形成在氧化硅膜45上。在该步骤中，首先，通过溅射沉积铝(Al)膜，然后采用抗蚀剂图案为掩膜，通过RIE使铝膜被构图蚀刻。由此，形成由铝制成的互连线51。作为互连线51的材料，可以采用低电阻率的铜(Cu)。
尽管附图中没有示出后续步骤，但是通过在上层或者多层中形成互连线，可以形成包括两层、三层、四层或者更多层的多层互连结构。由此能够获得具有多层互连结构的半导体装置。
根据上述的第一实施例，能够获得半导体装置1a，其中源/漏区域15包括外延层11和扩散层13。因此，外延层11的宽度可以通过改变扩散层13的宽度来调整。
因此，在参照图3D描述的步骤中，其中形成对应于外延层的宽度具有预定宽度W的凹入部分39，通过控制凹入部分39的宽度达到预定宽度W而且不依赖有源区域7中栅电极9的布局，可形成蚀刻深度的凹入部分39并且考虑蚀刻期间的微载荷效应(microloading effect)。具体地讲，通过设定凹入部分39的宽度为预定宽度W，能够获得抑制由微载荷效应引起的蚀刻深度的变化的凹入部分39。
因此，形成在凹入部分39中的外延层11的深度可以控制并且制造均匀。
此外，因为外延层11的形成区域(布局区域)由对应于扩散层13的部分减少并且不依赖于布局，所以能够获得具有小量晶体缺陷的外延层11。
因此，通过控制外延层11的预定深度，能够抑制施加给栅电极9下面的沟道区域ch的应力的变化。此外，因为可以获得具有小量晶体缺陷的外延层11而不依赖于布局，可以减少结泄漏。因此可以改善晶体管Tr的特性。
此外，尽管通过采用这样的结构减少了外延层11的体积，但是通过设定外延层11的深度为一定值，能够保持施加给沟道区域ch的应力(参照K.Ota等″Scalable eSiGe S/D technology with less layout dependence for 45-nmgeneration″，2006 Symposium VLSI Technology Digest of Technical Papers，2006)。
此外，如上所述，因为通过对应于扩散层13的部分减少了外延层11的形成区域(布局区域)，所以使得覆盖外延层11的侧壁的应力膜43靠近沟道区域ch。由此，可以提高通过应力膜43给沟道区域ch施加应力的效果。
第二实施例
图6是显示根据本发明第二实施例的半导体装置的结构的示意性截面图。图6所示的半导体装置1b与图1所示根据第一实施例的半导体装置1a具有相同的结构，除了构成源/漏区域15的扩散层13的深度大于外延层11的深度。
在具有该结构的半导体装置1b中，通过增加相对于栅电极9位于外延层11外侧的扩散层13的深度，除了第一实施例的效果以及减少了短沟道效应，p-n结上耗尽层的电场可以减小，并且因此可以进一步改善结泄漏。此外，通过增加扩散层13的深度，减少了基板在结上的杂质浓度。由此，可减小结电容，并且可以改善MOS晶体管Tr的工作速度。
第三实施例
图7是显示根据本发明第三实施例的半导体结构的示意性截面图。图7所示的半导体装置1c与图1所示的根据第一实施例的半导体装置1a具有相同的结构，除了构成源/漏区域15的扩散层13的表面高度小于栅电极9下面的半导体基板3的表面高度。
在具有该结构的半导体装置1c中，覆盖晶体管Tr的应力膜43延伸到低于沟道区域ch的位置。由此，除了第一实施例的效果外，可以提高通过应力膜43给沟道区域ch施加应力的效果。
第四实施例
图8是显示根据本发明第四实施例的半导体装置的结构的示意性截面图。图8所示的半导体装置61a具有设置有p型MOS晶体管Tr的结构。半导体装置61a不同于图1所示的根据第一实施例的半导体装置1a之处在于，源/漏区域15中只有一个包括外延层11，而源/漏区域15中的另一个仅包括扩散层13。此外，相反导电类型(n型)的扩散层(相反导电类型的扩散层63)设置成相邻于扩散层13。省略了与第一实施例相同结构的重复描述。
在半导体装置61a中，相反导电类型的扩散层63设置成相对阱扩散层23的接触区域。相反导电类型的扩散层63和与之相邻设置的源/漏区域15通过设置在其表面上的硅化物层41短路。在半导体装置61a中，通过采用这样的结构，减少了阱接触。
在该结构中，因为扩散层13构成相邻于并且短路到相对于阱扩散层23(相反导电类型的扩散层63)的接触区域的源/漏区域15，所以能够防止在相反导电类型的扩散层63中的n型杂质扩散进入源/漏区域15且到达沟道区域ch。
就是说，如图9的比较实例所示，在由硅锗(SiGe)组成的外延层11构成相邻于相反导电类型的扩散层63设置的源/漏区域15的情况下，相反导电类型的扩散层63中的n型杂质易于扩散进入外延层11，并且到达沟道区域ch。其原因是在SiGe中的n型杂质的扩散率大于由硅组成的半导体基板，即在砷(As)的情况下，约七倍高，而在磷(P)的情况下，约两倍高。
因此，如图8所示，通过采用源/漏区域15中仅一个包括外延层11而与相反导电类型的扩散层63相邻设置的源/漏区域15中的另一个包括扩散层13的结构，能够防止在相反导电类型的扩散层63中的n型杂质扩散进入沟道区域ch，并且可以抑制p型MOS晶体管Tr的阈值的变化。
第五实施例
图10是显示根据本发明第五实施例的半导体装置的结构的示意性截面图。图10所示的半导体装置61b具有与根据第四实施例的半导体装置61a具有相同的结构，除了源/漏区域15中的一个包括与外延层11一起的扩散层13。
在该情况下，扩散层13通过外延层11设置在栅电极9的侧部。
通过采用这样结构，外延层11的沿沟道长度方向上的宽度可以设定成通过扩散层13控制的预定宽度W。因此，可以获得与第一实施例相同的效果。
本领域的技术人员应当理解的是，在所附权利要求及其等同物的范围内，根据设计需要和其他因素，可以进行各种修改、结合、部分结合和替换。
本发明包含2007年6月27日提交日本专利局的日本专利申请JP2007-169023相关的主题事项，其全部内容在此合并作为参考。

Claims (10)

1.一种半导体装置，包括：
栅电极，设置在半导体基板上；和
源/漏区域，设置在所述栅电极的两侧，所述源/漏区域通过注入杂质形成，
其中所述源/漏区域包括：
外延层，通过在所述栅电极的侧部的凹入位置中外延生长晶格常数不同于所述半导体基板材料的晶格常数的半导体材料而形成，所述外延层的上表面高于半导体基底的表面；和
扩散层，设置在所述半导体基板的表面层中。
2.根据权利要求1所述的半导体装置，其中所述外延层设置在所述栅电极的两侧的每一侧上，并且所述扩散层设置在所述外延层的外侧。
3.根据权利要求2所述的半导体装置，其中所述外延层设置为沿沟道长度方向具有预定的宽度。
4.根据权利要求2所述的半导体装置，其中所述扩散层的表面低于所述栅电极下面的所述半导体基板的表面。
5.根据权利要求1所述的半导体装置，其中所述源/漏区域中的一个包括所述外延层，而所述源/漏区域中的另一个仅包括所述扩散层。
6.根据权利要求5所述的半导体装置，其中导电类型与所述扩散层的导电类型不同的相反导电类型的扩散层设置成与所述扩散层相邻，并且所述扩散层和所述相反导电类型扩散层通过设置在所述源/漏区域和所述相反导电类型的扩散层的表面上的硅化物层短路。
7.根据权利要求6所述的半导体装置，其中所述半导体基板由硅组成，并且所述外延层由硅锗组成。
8.根据权利要求5所述的半导体装置，其中所述源/漏区域中的一个包括所述外延层和设置在所述外延层外侧的所述扩散层。
9.根据权利要求8所述的半导体装置，其中所述扩散层的表面低于所述栅电极下面的所述半导体基板的表面。
10.一种制造半导体装置的方法，包括：
第一步骤，在半导体基板上形成栅电极；
第二步骤，通过掩膜图案实行蚀刻，从而在所述栅电极的侧部凹陷形成所述半导体基板的表面层；
第三步骤，在所述半导体基板的凹入部分上形成由晶格常数不同于所述半导体基板材料的晶格常数的半导体材料组成的外延层，所述外延层的上表面高于半导体基底的表面；以及
第四步骤，通过去除所述掩膜图案来暴露所述半导体基板的所述表面层并且使杂质扩散进入所述外延层和所述半导体基板的所述表面层来形成源/漏区域，所述源/漏区域包括杂质扩散于其中的所述外延层和通过使杂质扩散进入所述表面层中而形成的扩散层。
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