JP5172083B2 - 半導体装置及びその製造方法、並びにメモリ回路 - Google Patents
半導体装置及びその製造方法、並びにメモリ回路 Download PDFInfo
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Description
図1に、本実施の形態に係る半導体装置の断面図を示す。図1に示す半導体装置では、SOI構造を採用しており、シリコン基板1上に埋め込み酸化膜2が形成され、さらに埋め込み酸化膜2上に半導体層3が形成された構造である。この半導体層3には、Nチャネル型MOSトランジスタが形成されるため、P型のボディ領域4とN型のソース領域5及びドレイン領域6とが設けられている。
SOI構造の半導体装置において、ボディ浮遊効果を抑制するには、ホットキャリアの発生を低減することによっても可能である。このホットキャリアの発生を低減するためには、ゲート電極側のドレイン領域における電界を緩和すれば良い。つまり、ソース領域を寄生抵抗が少ないソース不純物構造にし、非対称なソース−ドレイン構造にすることで、ゲート電極側のドレイン領域における電界を緩和することが可能となる。本実施の形態に係る半導体装置では、上記の構造を採用している。
図7に、本実施の形態に係る半導体装置の断面図を示す。図7に示す半導体装置では、図1に示したソース領域5と構成が異なる。なお、図7のソース領域5以外は、図1に示した半導体装置と同じであるため、同一の構成部分については同一符号を付し詳細な説明は省略する。
図1に示した半導体装置において、ソースエクステンション層52の底面は、Coシリサイド層51とのみ接していた。そのため、ソースエクステンション層52は、Coシリサイド層51の側面部分としか接触しておらず、ソースエクステンション層52とCoシリサイド層51の接触抵抗は高くなる。従って、当該接触抵抗が、Coシリサイド層51からソースエクステンション層52を経由してゲート電極下のチャネル反転層まで流れる電流経路に対する寄生抵抗となり、トランジスタのオン電流を低下させる原因となる場合があった。
図10に、本実施の形態に係る半導体装置の断面図を示す。本実施の形態に係る半導体装置も、実施の形態4と同様、Coシリサイド層51とソースエクステンション層52との接触抵抗を抑制する構成である。具体的に、本実施の形態では、図10に示すように、Coシリサイド層51の全部又は大半部分が、半導体層3上に形成されている。このような構造にすることで、Coシリサイド層51の底面の全面がソースエクステンション層52と接することになり、図1に示したようなCoシリサイド層51の側面でのみソースエクステンション層52と接する場合に比べて接触面積が大きくなり接触抵抗を低減できる。
本実施の形態では、実施の形態5で示したようにCoシリサイド層51とボディ領域4とを接続するP型拡散層55のような拡散層を製造する方法について説明する。なお、以下の説明においては、図13に示す一般的な半導体装置の構成を用いてP型拡散層55の製造方法を説明する。図13に示す半導体装置では、図10に示した半導体装置と異なりCoシリサイド層51が半導体層3内に形成されている。なお、図13において、図10と同一の構成部分については同一の符号を付し詳細な説明は省略する。
上記実施の形態で示した半導体装置は、ボディ領域4をソース領域5に何らかの形で接続することにより、ボディ電位をソース電位に固定している。そのため、上記実施の形態で示した半導体装置の構造をとるMOSFET(Metal Oxide Semiconductor Field Effect Transistor)を、ソース側を常に固定して使用するインバータ回路部分などに適用することは可能であるが、ソース側とドレイン側が動作状況により反転するようなパストランジスタ回路部分などには適用できない。
上記実施の形態では、ボディ電位を固定することができる半導体装置の構造について説明した。本実施の形態では、従来、知られているソースタイ構造によるボディ電位を固定する構造と本発明の構造とを比較して説明する。
本実施の形態では、実施の形態1〜6に示した半導体装置の構造をSRAM(Static Random Access Memory)回路に適用する。
実施の形態9では、SRAMを構成する負荷トランジスタ102a,102b及びドライバトランジスタ103a,103bにのみ実施の形態1〜6で示した半導体装置の構造を適用し、アクセストランジスタ101a,101bはボディ浮遊構造としていた。
Claims (5)
- シリコン基板と、前記シリコン基板上に形成された埋め込み絶縁層と、前記埋め込み絶縁層上に形成された半導体層とを備えるSOI構造の半導体装置であって、
前記半導体層は、第1導電型のボディ領域、第2導電型のソース領域及び第2導電型のドレイン領域を有し、前記ソース領域と前記ドレイン領域との間の前記ボディ領域上にゲート酸化膜を介してゲート電極が形成され、
前記ソース領域は、第2導電型のエクステンション層と、前記エクステンション層と側面で接するシリサイド層を備え、前記ソース領域の底部と前記埋め込み絶縁層の間に前記ボディ領域を残し、前記シリサイド層と前記ボディ領域との境界部分に生じる空乏層の領域に結晶欠陥領域が形成され、
前記ドレイン領域は、前記ドレイン領域の底部と前記埋め込み絶縁層が接していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置であって、
前記エクステンション層は、前記ドレイン領域に形成されるエクステンション層に比べて第2導電型の不純物の実効濃度が高いことを特徴とする半導体装置。 - 請求項1に記載の半導体装置を製造する方法であって、
(a)前記エクステンション層と前記ボディ領域との接合面を含む所定の位置に、前記エクステンション層及び前記ボディ領域の少なくとも一方に結晶欠陥を生じさせるイオンを注入する工程と、
(b)前記(a)工程後に、前記ボディ領域と接する位置まで前記エクステンション層の一部をシリサイド化して前記シリサイド層を形成する工程とを備えることを特徴とする半導体装置の製造方法。 - ビット線と記憶ノードとの間に接続されるアクセストランジスタと、
電源と前記記憶ノードとの間に接続された負荷トランジスタと、
GNDと前記記憶ノードとの間に接続されたドライバトランジスタとを備えるメモリ回路であって、
前記負荷トランジスタ及び前記ドライバトランジスタは、請求項1記載の半導体装置の構成を有することを特徴とするメモリ回路。 - 請求項4に記載のメモリ回路であって、
前記アクセストランジスタは、SOI構造の半導体装置であって、ボディ部とボディ端子が分離酸化膜で分離されており、前記分離酸化膜は前記埋め込み絶縁層との間に半導体層を残して形成されおり、分離酸化膜の下層で、ボディ部とボディ端子が繋がっていることを特徴とするメモリ回路。
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