JP2008153567A - 半導体メモリ及びその製造方法 - Google Patents
半導体メモリ及びその製造方法 Download PDFInfo
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- JP2008153567A JP2008153567A JP2006342240A JP2006342240A JP2008153567A JP 2008153567 A JP2008153567 A JP 2008153567A JP 2006342240 A JP2006342240 A JP 2006342240A JP 2006342240 A JP2006342240 A JP 2006342240A JP 2008153567 A JP2008153567 A JP 2008153567A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 129
- 239000012535 impurity Substances 0.000 claims abstract description 103
- 230000015654 memory Effects 0.000 claims abstract description 43
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 10
- 238000003860 storage Methods 0.000 claims description 4
- 230000014759 maintenance of location Effects 0.000 abstract description 9
- 238000000034 method Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 239000000758 substrate Substances 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005036 potential barrier Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000013641 positive control Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000013642 negative control Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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Abstract
【解決手段】 ドレイン拡散層の高濃度不純物層領域の不純物濃度をソース拡散層の高濃度不純物層領域の不純物濃度よりも低濃度とする。ドレイン拡散層を低濃度で形成することでGIDLリークを抑制する。一方でソース拡散層の不純物濃度を高くすることで、ボティーソース拡散層間への蓄積電荷の漏れを抑制する。データ保持特性が優れたメモリセルを備えた半導体メモリが得られる。
【選択図】 図1
Description
2 絶縁膜
3 P型シリコン層(ボディ)
4 ゲート絶縁膜
5 ゲート電極(ワード線WL)
6 ソース拡散層
7 ドレイン拡散層
8 側壁絶縁膜
10 素子分離絶縁膜
11 レジスト
Claims (7)
- 1トランジスタセル方式のメモリセルで構成された半導体メモリにおいて、絶縁膜上の半導体領域に形成されたメモリセルトランジスタは、ドレイン拡散層と、ソース拡散層と、ゲート電極とを備え、前記ドレイン拡散層及びソース拡散層はそれぞれ低濃度不純物層領域と高濃度不純物層領域から形成され、前記ドレイン拡散層及びソース拡散層の高濃度不純物層領域の不純物濃度は異なり、非対称であることを特徴とする半導体メモリ。
- 前記ドレイン拡散層の高濃度不純物層領域の不純物濃度は、前記ソース拡散層の高濃度不純物層領域の不純物濃度よりも低く、前記ドレイン拡散層及びソース拡散層の低濃度不純物層領域の不純物濃度よりも高いことを特徴とする請求項1に記載の半導体メモリ。
- 前記ドレイン拡散層及びソース拡散層の高濃度不純物層領域の深さは、前記絶縁膜に接するように形成されることを特徴とする請求項2に記載の半導体メモリ。
- 前記ドレイン拡散層及びソース拡散層の高濃度不純物層領域の深さは、前記絶縁膜が形成された深さより高く、前記ドレイン拡散層及びソース拡散層の低濃度不純物層領域の深さよりも低いことを特徴とする請求項2に記載の半導体メモリ。
- 前記ドレイン拡散層はビット線に、前記ソース拡散層はソース線に、前記ゲート電極はワード線にそれぞれ接続され、前記ゲート電極の下部の半導体領域に蓄積される電荷量を記憶情報とすることを特徴とする請求項2に記載の半導体メモリ。
- 1トランジスタセル方式のメモリセルで構成された半導体メモリの製造方法において、絶縁膜上の半導体領域に素子分離絶縁膜により素子領域を分離する工程と、ゲート絶縁膜を介してゲート電極を形成する工程と、ドレイン拡散層及びソース拡散層の低濃度不純物層領域に不純物を注入する工程と、ソース拡散層の高濃度不純物層領域のみに不純物を注入する工程と、さらにドレイン拡散層及びソース拡散層の高濃度不純物層領域に不純物を注入する工程と、を備えたことを特徴とする半導体メモリの製造方法。
- 前記ソース拡散層の高濃度不純物層領域のみに不純物を注入する工程においては、前記ドレイン拡散層の高濃度不純物層領域をレジストで覆い、イオン注入法により前記ソース拡散層の高濃度不純物層領域に不純物を注入することを特徴とする請求項6に記載の半導体メモリの製造方法。
Priority Applications (2)
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JP2006342240A JP2008153567A (ja) | 2006-12-20 | 2006-12-20 | 半導体メモリ及びその製造方法 |
US12/000,878 US20080150023A1 (en) | 2006-12-20 | 2007-12-18 | Semiconductor memory and manufacturing method thereof |
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JP2006342240A JP2008153567A (ja) | 2006-12-20 | 2006-12-20 | 半導体メモリ及びその製造方法 |
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JP2008153567A true JP2008153567A (ja) | 2008-07-03 |
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JP2006342240A Pending JP2008153567A (ja) | 2006-12-20 | 2006-12-20 | 半導体メモリ及びその製造方法 |
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US (1) | US20080150023A1 (ja) |
JP (1) | JP2008153567A (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010282670A (ja) * | 2009-06-02 | 2010-12-16 | Hitachi Ltd | ダイナミック・ランダム・アクセス・メモリ装置とその検査方法 |
US9583629B2 (en) | 2014-03-06 | 2017-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10312252B2 (en) | 2016-05-11 | 2019-06-04 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
KR20190118895A (ko) * | 2018-04-11 | 2019-10-21 | 경북대학교 산학협력단 | 디램 셀 메모리 소자, 메모리 어레이 및 메모리 소자의 제조 방법 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101853316B1 (ko) | 2012-03-29 | 2018-04-30 | 삼성전자주식회사 | 반도체 소자 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63190377A (ja) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | 半導体記憶装置 |
JPH11163174A (ja) * | 1997-09-26 | 1999-06-18 | Matsushita Electron Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2000260989A (ja) * | 1999-03-12 | 2000-09-22 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP2000340679A (ja) * | 1999-05-10 | 2000-12-08 | Internatl Business Mach Corp <Ibm> | ボディ・コンタクト式ダイナミック・メモリ |
JP2000517483A (ja) * | 1996-09-03 | 2000-12-26 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 低濃度および高濃度にドープされるドレイン領域ならびに非常に高濃度にドープされるソース領域を備えた非対称形トランジスタ |
JP2001358233A (ja) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2003031696A (ja) * | 2001-05-11 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2005051186A (ja) * | 2003-07-31 | 2005-02-24 | Fujitsu Ltd | 半導体記憶装置 |
JP2005079314A (ja) * | 2003-08-29 | 2005-03-24 | Toshiba Corp | 半導体集積回路装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5648286A (en) * | 1996-09-03 | 1997-07-15 | Advanced Micro Devices, Inc. | Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region |
US7109532B1 (en) * | 2003-12-23 | 2006-09-19 | Lee Zachary K | High Ion/Ioff SOI MOSFET using body voltage control |
JP5172083B2 (ja) * | 2004-10-18 | 2013-03-27 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法、並びにメモリ回路 |
US7221006B2 (en) * | 2005-04-20 | 2007-05-22 | Freescale Semiconductor, Inc. | GeSOI transistor with low junction current and low junction capacitance and method for making the same |
-
2006
- 2006-12-20 JP JP2006342240A patent/JP2008153567A/ja active Pending
-
2007
- 2007-12-18 US US12/000,878 patent/US20080150023A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63190377A (ja) * | 1987-02-02 | 1988-08-05 | Matsushita Electronics Corp | 半導体記憶装置 |
JP2000517483A (ja) * | 1996-09-03 | 2000-12-26 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 低濃度および高濃度にドープされるドレイン領域ならびに非常に高濃度にドープされるソース領域を備えた非対称形トランジスタ |
JPH11163174A (ja) * | 1997-09-26 | 1999-06-18 | Matsushita Electron Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2000260989A (ja) * | 1999-03-12 | 2000-09-22 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP2000340679A (ja) * | 1999-05-10 | 2000-12-08 | Internatl Business Mach Corp <Ibm> | ボディ・コンタクト式ダイナミック・メモリ |
JP2001358233A (ja) * | 2000-06-15 | 2001-12-26 | Hitachi Ltd | 半導体集積回路装置および半導体集積回路装置の製造方法 |
JP2003031696A (ja) * | 2001-05-11 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2005051186A (ja) * | 2003-07-31 | 2005-02-24 | Fujitsu Ltd | 半導体記憶装置 |
JP2005079314A (ja) * | 2003-08-29 | 2005-03-24 | Toshiba Corp | 半導体集積回路装置 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010282670A (ja) * | 2009-06-02 | 2010-12-16 | Hitachi Ltd | ダイナミック・ランダム・アクセス・メモリ装置とその検査方法 |
US9583629B2 (en) | 2014-03-06 | 2017-02-28 | Kabushiki Kaisha Toshiba | Semiconductor device |
TWI601294B (zh) * | 2014-03-06 | 2017-10-01 | 東芝記憶體股份有限公司 | 半導體裝置 |
US10312252B2 (en) | 2016-05-11 | 2019-06-04 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
KR20190118895A (ko) * | 2018-04-11 | 2019-10-21 | 경북대학교 산학협력단 | 디램 셀 메모리 소자, 메모리 어레이 및 메모리 소자의 제조 방법 |
KR102086060B1 (ko) * | 2018-04-11 | 2020-03-09 | 경북대학교 산학협력단 | 디램 셀 메모리 소자, 메모리 어레이 및 메모리 소자의 제조 방법 |
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