JP2007073680A - Fbcメモリ装置 - Google Patents
Fbcメモリ装置 Download PDFInfo
- Publication number
- JP2007073680A JP2007073680A JP2005257999A JP2005257999A JP2007073680A JP 2007073680 A JP2007073680 A JP 2007073680A JP 2005257999 A JP2005257999 A JP 2005257999A JP 2005257999 A JP2005257999 A JP 2005257999A JP 2007073680 A JP2007073680 A JP 2007073680A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- memory device
- floating body
- mos transistor
- drain diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 62
- 238000006073 displacement reaction Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000009751 slip forming Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Abstract
【解決手段】ビット線に沿う断面におけるゲート電極位置を、セル中心線100aよりもドレイン拡散層側にΔ変位させた非対称構造を用いることにより、ソース拡散層70とボディ間の容量Csbに対するドレイン拡散層80とボディ間の容量Cdbの比(Cdb/Csb)を小さくし、二つのデータ状態の閾値差を広げ、信号量を大きくする。
【選択図】図1
Description
20 n型半導体層
30 p型半導体層
40 ゲート絶縁膜
50 ゲート電極
50a ワード線
60 ゲート側壁
70 ソース拡散層
70a ソース線
80 ドレイン拡散層
80a ビット線
80b ビット線コンタクト
90 素子分離領域
100 メモリセル領域
100a セル中心線
100b ゲート中心線
110 絶縁領域
140a〜140c ユニットセル
t1〜t5 t11〜t15 時刻
VBL ビット線電圧
VWL ワード線電圧
VB ボディ電圧
Δ 変位
Csb ソース−ボディ間容量
Cdb ドレイン−ボディ間容量
Claims (5)
- 基板と、
前記基板に形成されたMOSトランジスタと、
前記MOSトランジスタのゲート電極がワード線に、ドレイン拡散層がビット線に、ソース拡散層が固定電位線にそれぞれ接続され、
前記基板中に他から電気的に分離され正孔を蓄積することが可能なフローティングボディとを備え、
前記ドレイン拡散層と前記フローティングボディ間の電気容量が前記ソース拡散層と前記フローティングボディ間の電気容量未満であることを特徴とする半導体メモリ装置。 - 前記MOSトランジスタがnチャネルMOSトランジスタであり、前記フローティングボディがp型であり、前記p型のフローティングボディがn型の半導体層上に備えられることを特徴とする請求項1記載の半導体メモリ装置。
- 前記MOSトランジスタが隣り合う二つの素子分離領域の間に形成され、ビット線に平行に沿った断面における前記MOSトランジスタのゲート電極が、前記隣り合う二つの素子分離領域間の中央位置よりも前記ドレイン拡散層側に近い位置に形成されたMOSトランジスタ構造であることを特徴とする請求項1記載の半導体メモリ装置。
- 前記ドレイン拡散層の不純物濃度を前記ソース拡散層の不純物濃度に比較して薄くしたMOSトランジスタ構造であることを特徴とする請求項1記載の半導体メモリ装置。
- 前記ワード線にウィグル構造を用いることにより、前記ドレイン拡散層と前記フローティングボディ間の電気容量を前記ソース拡散層と前記フローティングボディ間の電気容量未満にすることを特徴とする請求項1記載の半導体メモリ装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005257999A JP4660324B2 (ja) | 2005-09-06 | 2005-09-06 | Fbcメモリ装置 |
US11/485,278 US20070013007A1 (en) | 2005-07-15 | 2006-07-13 | Semiconductor device and method of fabricating the same |
US12/402,920 US20090173983A1 (en) | 2005-07-15 | 2009-03-12 | Semiconductor device and method of fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005257999A JP4660324B2 (ja) | 2005-09-06 | 2005-09-06 | Fbcメモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007073680A true JP2007073680A (ja) | 2007-03-22 |
JP4660324B2 JP4660324B2 (ja) | 2011-03-30 |
Family
ID=37934885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005257999A Expired - Fee Related JP4660324B2 (ja) | 2005-07-15 | 2005-09-06 | Fbcメモリ装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4660324B2 (ja) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100904336B1 (ko) | 2007-03-22 | 2009-06-23 | 가부시끼가이샤 도시바 | 반도체 메모리 디바이스 |
US7924644B2 (en) | 2008-01-03 | 2011-04-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device including floating body transistor memory cell array and method of operating the same |
US7944759B2 (en) | 2007-10-10 | 2011-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device including floating body transistor |
US7969808B2 (en) | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
US7990779B2 (en) | 2008-11-10 | 2011-08-02 | Samsung Electronics Co., Ltd. | Method of operating semiconductor devices |
US8009473B2 (en) | 2008-01-03 | 2011-08-30 | Samsung Electronics Co., Ltd. | Semiconductor memory device including memory cell array having memory cells using floating body transistors |
US8039325B2 (en) | 2008-12-18 | 2011-10-18 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor device having capacitorless one-transistor memory cell |
US8054693B2 (en) | 2008-12-17 | 2011-11-08 | Samsung Electronics Co., Ltd. | Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same |
US8134202B2 (en) | 2008-05-06 | 2012-03-13 | Samsung Electronics Co., Ltd. | Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics |
JP2013527977A (ja) * | 2010-04-07 | 2013-07-04 | セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク | トランジスタを備えるramメモリセル |
JP2015513216A (ja) * | 2012-02-16 | 2015-04-30 | ジーノ セミコンダクター, インコーポレイテッド | 第一および第二のトランジスタと方法から成っているメモリ・セル |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05267569A (ja) * | 1992-03-18 | 1993-10-15 | Nec Corp | 半導体記憶装置 |
JP2002343885A (ja) * | 2001-05-17 | 2002-11-29 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2003017691A (ja) * | 2001-07-02 | 2003-01-17 | Toshiba Corp | 半導体装置 |
JP2003031696A (ja) * | 2001-05-11 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2004039982A (ja) * | 2002-07-05 | 2004-02-05 | Mitsubishi Electric Corp | 半導体装置 |
-
2005
- 2005-09-06 JP JP2005257999A patent/JP4660324B2/ja not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05267569A (ja) * | 1992-03-18 | 1993-10-15 | Nec Corp | 半導体記憶装置 |
JP2003031696A (ja) * | 2001-05-11 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2002343885A (ja) * | 2001-05-17 | 2002-11-29 | Toshiba Corp | 半導体メモリ装置及びその製造方法 |
JP2003017691A (ja) * | 2001-07-02 | 2003-01-17 | Toshiba Corp | 半導体装置 |
JP2004039982A (ja) * | 2002-07-05 | 2004-02-05 | Mitsubishi Electric Corp | 半導体装置 |
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7626879B2 (en) | 2007-03-22 | 2009-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
KR100904336B1 (ko) | 2007-03-22 | 2009-06-23 | 가부시끼가이샤 도시바 | 반도체 메모리 디바이스 |
US7969808B2 (en) | 2007-07-20 | 2011-06-28 | Samsung Electronics Co., Ltd. | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same |
US7944759B2 (en) | 2007-10-10 | 2011-05-17 | Samsung Electronics Co., Ltd. | Semiconductor memory device including floating body transistor |
US8009473B2 (en) | 2008-01-03 | 2011-08-30 | Samsung Electronics Co., Ltd. | Semiconductor memory device including memory cell array having memory cells using floating body transistors |
US7924644B2 (en) | 2008-01-03 | 2011-04-12 | Samsung Electronics Co., Ltd. | Semiconductor memory device including floating body transistor memory cell array and method of operating the same |
US8134202B2 (en) | 2008-05-06 | 2012-03-13 | Samsung Electronics Co., Ltd. | Capacitorless one-transistor semiconductor memory device having improved data retention abilities and operation characteristics |
US7990779B2 (en) | 2008-11-10 | 2011-08-02 | Samsung Electronics Co., Ltd. | Method of operating semiconductor devices |
US8054693B2 (en) | 2008-12-17 | 2011-11-08 | Samsung Electronics Co., Ltd. | Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same |
US8039325B2 (en) | 2008-12-18 | 2011-10-18 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor device having capacitorless one-transistor memory cell |
JP2013527977A (ja) * | 2010-04-07 | 2013-07-04 | セントレ・ナショナル・デ・ラ・レシェルシェ・サイエンティフィーク | トランジスタを備えるramメモリセル |
US9166051B2 (en) | 2010-04-07 | 2015-10-20 | Centre National De La Recherche Scientifique | RAM memory cell comprising a transistor |
KR101804197B1 (ko) | 2010-04-07 | 2017-12-04 | 상뜨르 나시오날 드 라 리쉐르쉐 샹띠피끄 | 트랜지스터를 구비한 램 메모리 셀 |
JP2015513216A (ja) * | 2012-02-16 | 2015-04-30 | ジーノ セミコンダクター, インコーポレイテッド | 第一および第二のトランジスタと方法から成っているメモリ・セル |
Also Published As
Publication number | Publication date |
---|---|
JP4660324B2 (ja) | 2011-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4660324B2 (ja) | Fbcメモリ装置 | |
US9524971B2 (en) | Techniques for providing a semiconductor memory device | |
US8508970B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
US9559216B2 (en) | Semiconductor memory device and method for biasing same | |
US8964461B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
WO2022137607A1 (ja) | 半導体素子を用いたメモリ装置の製造方法 | |
US20090213675A1 (en) | Semiconductor memory device | |
TWI517307B (zh) | 垂直式無電容dram記憶胞、dram陣列及其操作方法 | |
WO2009005075A2 (en) | A method of driving a semiconductor memory device and a semiconductor memory device | |
JP2008263133A (ja) | 半導体記憶装置およびその駆動方法 | |
US9263133B2 (en) | Techniques for providing a semiconductor memory device | |
US8144514B2 (en) | One-transistor floating-body DRAM cell device with non-volatile function | |
US20230377635A1 (en) | Semiconductor element memory device | |
US11968822B2 (en) | Memory device using semiconductor element | |
TWI816460B (zh) | 使用半導體元件的記憶裝置 | |
US8982633B2 (en) | Techniques for providing a direct injection semiconductor memory device | |
JP7490285B2 (ja) | 半導体素子を用いたメモリ装置 | |
TW202303930A (zh) | 具有記憶元件的半導體裝置 | |
US20100165757A1 (en) | Semiconductor memory device | |
WO2022239198A1 (ja) | 半導体素子を用いたメモリ装置の製造方法 | |
US20240196591A1 (en) | Memory device using semiconductor element | |
US20220415901A1 (en) | Method for manufacturing memory device using semiconductor element | |
US20230284432A1 (en) | Semiconductor-element-including memory device | |
WO2023112122A1 (ja) | 半導体素子を用いたメモリ装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080724 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100908 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100924 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101115 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20101203 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20101228 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140107 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140107 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |