JP2015513216A - 第一および第二のトランジスタと方法から成っているメモリ・セル - Google Patents
第一および第二のトランジスタと方法から成っているメモリ・セル Download PDFInfo
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- JP2015513216A JP2015513216A JP2014557836A JP2014557836A JP2015513216A JP 2015513216 A JP2015513216 A JP 2015513216A JP 2014557836 A JP2014557836 A JP 2014557836A JP 2014557836 A JP2014557836 A JP 2014557836A JP 2015513216 A JP2015513216 A JP 2015513216A
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Abstract
Description
現在の発明は半導体メモリー技術に関します。 より具体的には、現在の発明は、電気的に浮かぶ身体トランジスターおよびアクセス・トランジスタを含む半導体記憶装置に関します。
半導体記憶装置はデータを格納するために広範囲に使用されます。 メモリ素子は2つ一般型によって特徴づけることができます: 揮発性で不揮発性です。 スタティックRAM(SRAM)とダイナミック・ランダム・アクセス・メモリ(DRAM)のような不安定なメモリデバイスは、力がそれに連続的に供給されないとき、その中で格納されるデータを失います。
続行が改良する必要がある発明アドレスは、メモリセル操作の間、それを達成するのにアクセストランジスタを使用することによって、抵抗を擾乱します。
現在のメモリデバイスと方法が記述される前に、この発明が記述される特定の具体化に限られていないことを理解すべきですそのように、もちろん、異なるかもしれません。 また、ここに使用された用語が、特定の実施例だけについて説明する目的のためにあって、制限であることを意図しないのが理解されることになっています、本発明の範囲が単に追加されたクレームで制限されるので。
Claims (37)
- 半導体メモリー・セルは次のものを含みます:
トランジスタ浮いて双安定体 そして、アクセスデバイス;前述の2安定した浮体トランジスタと前述のアクセスデバイスは電気的に連続的に接続されます。 - 請求項1の半導体メモリセル; 前述のアクセスデバイスはモス・トランジスタを包括します。
- 請求項1の半導体メモリセル; 前述のアクセスデバイスはバイポーラトランジスタを包括します。
- 請求項2の半導体メモリセル; 前述のアクセストランジスタには、前述の2安定浮体トランジスタと同じ伝導率タイプがあります。
- 請求項2の半導体メモリセル; 前述のアクセストランジスタには、前述の2安定した浮体トランジスタのものと異なった伝導率タイプがあります。.
- 請求項1の半導体メモリセル; 前述の2安定した浮体トランジスタは埋まっている井戸の地域を包括します。
- 請求項1の半導体メモリセル; 前述の2安定した浮体トランジスタは複数のポート浮体トランジスタを包括します、そして、前述のアクセスデバイスは複数のアクセストランジスタを包括します。
- 請求項7の半導体メモリセル; 前述の2安定した浮体トランジスタは二元的なポート浮体トランジスタを包括します、そして、前述のアクセスデバイスは2個のアクセストランジスタを包括します。
- 半導体メモリー・セルは次のものを含みます:
最初のボディーの最初のトランジスタ;
2番目のボディーがある2番目のトランジスタ;
前述の1番目と2番目のボディーで基本的な基板;
前述の最初のボディーと2番目のボディーの前述の下層と少なくとも1つの間で挿入された埋込層;
前述の最初のボディーに連絡する最初のソース領域;
前述の最初のソースの線地域と切り離されて、前述の最初のボディーに連絡する最初のドレイン領域;
前述の最初のボディーから隔離された最初のゲート;
2番目の前述のボディーから前述の最初のボディーを隔離する絶縁部材;
2番目の前述のボディーに連絡するセカンドソース領域;
2番目のドレイン領域は前述のセカンドソース領域と2番目の前述のボディーに連絡するのから分離しました。 そして、
2番目のゲートは2番目の前述のボディーを隔離しました。 - 請求項9の半導体メモリセル; 前述の最初のゲートは前述の最初のソース領域と前述の最初のドレイン領域の間に位置決めされます; 2番目の前述のゲートは前述のセカンドソース領域と2番目の前述のドレイン領域の間に位置決めされます。
- 請求項9の半導体メモリセル; 前述の最初のトランジスタは浮体トランジスタです、そして、2番目の前述のトランジスタはアクセストランジスタです。
- 請求項9の半導体メモリセル; 前述の最初のボディーは浮体です、そして、2番目の前述のボディーは、電気的に前述の下層につなげられた井戸の地域です。
- 請求項9の半導体メモリセル; 前述の最初のドレイン領域は電気的に前述のセカンドソース領域につなげられます。
- 請求項9の半導体メモリセル; 上述の最初の体には、P型導電性タイプとn型導電性タイプから選ばれる最初の伝導率タイプがあります、そして、上述の第2の体には、上述の最初の伝導率タイプがあります; 上述の最初のソース地域と二次供給者地域と最初の排水管地域と第2の排水管地域は、第2の伝導率タイプを言われたP型導電性とn型導電性から選んでおきます、 そして、上述の最初の伝導率タイプは、上述の第2の伝導率タイプと異なります。
- 請求項9の半導体メモリセル;前述の最初のボディーは浮体です、そして、2番目の前述のボディーは、電気的に前述の埋込層につなげられる井戸の地域です; 上述の最初の体には、P型導電性とn型導電性から選ばれる最初の伝導率タイプがあります、そして、2番目の前述のボディーで、前述のp−タイプ伝導率とn型導電性から2番目の伝導率タイプを選び、また、前述の第1の導電型は、前述の第2の導電型とは異なる。
- 請求項9の半導体メモリセル; 前述の半導体メモリー・セルは対照セルを含む; さらに次のものを含む前述の対照セル:
上述の最初のソース地域と最初の排水管地域は別として間隔をあけられて、上述の最初の体に接触している感覚線地域;上述の最初の体には、P型導電性とn型導電性から選ばれる最初の伝導率タイプがあります;上述の感覚線地域には、上述の最初の伝導率タイプがあります。 - 請求項9の半導体メモリセル; 前述の第1の排水管地域は、前述の第2のゲートに電気的に接続されます。
- 請求項9の半導体メモリセル; 前述の第1のトランジスターは浮体トランジスターです。また、前述の第2のトランジスターは浮体トランジスターです。
- 請求項9の半導体メモリセル; 前述の1番目と2番目浮体トランジスターは補足的な電流を格納するように構成されます。
- 請求項9の半導体メモリセル; 少なくとも前述の最初のボディーと2番目のボディーの1つは2安定した浮体です。
- 半導体メモリー・セルは次のものを含みます:
浮体を備えた最初のトランジスター;
前述の浮体の下の埋込層; 前述の埋込層上の電圧の適用は、前述のメモリーセルの状態を維持します; そして
第2のトランジスター;
前述の1番目と2番目トランジスターは、直列に接続されます。 - 半導体メモリー・セルは次のものを含みます:
両安定した浮体トランジスター; そして
浮かぶゲート・トランジスター。 - 半導体メモリー・セルは次のものを含みます:
最初の両安定した浮体トランジスター; そして
第2の両安定浮体トランジスター;
前述の浮かぶ1番目と2番目身体トランジスターは補足的な電流を格納するように構成される。. - 両安定した浮体トランジスターおよびアクセス・トランジスタを備えた半導体メモリー・セルのオペレーションの方法; それは次のものを含んでいる:
アクセス・トランジスタをつけるためにアクセス・トランジスタに電圧をかけます; そして
アクセス・トランジスタの活性化によりオペレーション用のメモリーセルの選択を助。 - クレーム24の方法: 前述のオペレーションは、浮体トランジスターの状態を感じるためにメモリーセルによってモニタリング流れを含む、読まれたオペレーションです。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−1オペレーションである; アクセス・トランジスターにかけられた電圧は、アクセス・トランジスターのビット・ライン・ターミナルに適用された肯定的なバイアスである、 また、アクセス・トランジスタは浮体トランジスターの排水管地域に前述の正バイアスを配達します。
- クレーム26の方法は、衝突電離メカニズムによって穴の生成を最大限にするためにさらに浮体トランジスターを逸脱させます。
- クレーム26の方法: バイアスは、アクセス・トランジスタの発源地を浮かばせるためにアクセス・トランジスタにかけられた電圧にかけられます; 前述の方法は、さらに容量結合によって浮体トランジスターの浮体の可能性を増加させ。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−0オペレーションです; アクセス・トランジスタにかけられた電圧は負バイアスです、また、アクセス・トランジスタは浮体の排水管部分に前述の負バイアスを配達します。
- クレーム24の方法: 前述のオペレーションは活発な低い読まれたオペレーションです。
- クレーム24の方法: 前述のオペレーションは活発な最低値書き込みロジック−1オペレーションです。
- クレーム24の方法: 前述のオペレーションは、浮体トランジスターの状態を感じるメモリーセルによって読まれたオペレーション・モニタリング流れです; また、アクセス・トランジスターをつけるために応用の電圧は0である。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−1オペレーションです; アクセス・トランジスタにかけられた電圧はアクセス・トランジスタのワード線端子に0の電圧をかけることを含みます; また、書き込みロジック−1オペレーションは結合するバンド・トンネリング・メカニズムによって行なわれます。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−1オペレーションです; アクセス・トランジスタにかけられた電圧はアクセス・トランジスタのワード線端子に0の電圧をかけることを含みます、また、書き込みロジック−1オペレーションは衝突電離メカニズムによって行なわれます。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−1オペレーションです。また、アクセス・トランジスタにかけられた電圧は、アクセス・トランジスタの発源地を浮かばせるために偏見的である正の電圧です; 前述の方法は、さらに容量結合によって浮体トランジスターの浮体の可能性を増加させ。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−0オペレーションです。また、アクセス・トランジスタにかけられた電圧は、アクセス・トランジスタのワード線ターミナルに適用された正バイアスです。
- クレーム24の方法: 前述のオペレーションは書き込みロジック−0オペレーションおよび電圧です、当てはまられた、アクセス・トランジスタのワード線ターミナルは、浮体トランジスターの排水管地域に適用されたそれより多くの負バイアスです。
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SG11201404871TA (en) | 2014-09-26 |
JP2017195395A (ja) | 2017-10-26 |
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TW202226540A (zh) | 2022-07-01 |
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TWI639223B (zh) | 2018-10-21 |
EP2815402A4 (en) | 2015-09-30 |
EP2815402A1 (en) | 2014-12-24 |
CN104471648B (zh) | 2017-07-21 |
CN107331416A (zh) | 2017-11-07 |
CN104471648A (zh) | 2015-03-25 |
TWI605570B (zh) | 2017-11-11 |
US11974425B2 (en) | 2024-04-30 |
CN107331416B (zh) | 2020-11-10 |
TW201941405A (zh) | 2019-10-16 |
EP2815402B1 (en) | 2020-11-25 |
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JP6362542B2 (ja) | 2018-07-25 |
US20220278104A1 (en) | 2022-09-01 |
KR102059884B1 (ko) | 2019-12-27 |
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TW202119597A (zh) | 2021-05-16 |
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