WO2013123415A1 - Memory cell comprising first and second transistors and methods of operating - Google Patents

Memory cell comprising first and second transistors and methods of operating Download PDF

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Publication number
WO2013123415A1
WO2013123415A1 PCT/US2013/026466 US2013026466W WO2013123415A1 WO 2013123415 A1 WO2013123415 A1 WO 2013123415A1 US 2013026466 W US2013026466 W US 2013026466W WO 2013123415 A1 WO2013123415 A1 WO 2013123415A1
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WO
WIPO (PCT)
Prior art keywords
transistor
floating body
terminal
memory cell
region
Prior art date
Application number
PCT/US2013/026466
Other languages
English (en)
French (fr)
Inventor
Yuniarto Widjaja
Zvi Or-Bach
Original Assignee
Zeno Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/746,523 external-priority patent/US9230651B2/en
Priority to SG11201404871TA priority Critical patent/SG11201404871TA/en
Priority to EP13748573.6A priority patent/EP2815402B1/en
Priority to US14/380,779 priority patent/US9905564B2/en
Priority to KR1020147025821A priority patent/KR102059884B1/ko
Priority to JP2014557836A priority patent/JP6362542B2/ja
Application filed by Zeno Semiconductor, Inc. filed Critical Zeno Semiconductor, Inc.
Priority to CN201380009774.4A priority patent/CN104471648B/zh
Publication of WO2013123415A1 publication Critical patent/WO2013123415A1/en
Priority to US15/485,718 priority patent/US10181471B2/en
Priority to US16/219,359 priority patent/US10797055B2/en
Priority to US17/016,540 priority patent/US11348922B2/en
Priority to US17/743,248 priority patent/US11974425B2/en
Priority to US18/621,096 priority patent/US20240243492A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • G—PHYSICS
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    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
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    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
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    • G—PHYSICS
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    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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    • H01L29/0804—Emitter regions of bipolar transistors
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    • H01L29/0821—Collector regions of bipolar transistors
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
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Definitions

  • the access device comprises a bipolar transistor.
  • the first gate is positioned between the first source region and the first drain region and the second gate is positioned between the second source region and the second drain region.
  • the first drain region is electrically connected to the second gate.
  • At least one of the first and second bodies is a bi-stable floating body.
  • a semiconductor memory cell includes: a first transistor having a floating body; a buried layer below the floating body, wherein application of voltage on the buried layer maintains a state of the memory cell; and a second transistor; wherein the first and second transistors are connected in series.
  • a semiconductor memory cell includes: a first bi-stable floating body transistor; and a second bi-stable floating body transistor; wherein the first and second floating body transistors are configured to store complementary charges.
  • FIG. 1A schematically illustrates a memory cell which comprises memory device and an access device that are connected in series, according to a generic embodiment of the present invention.
  • Fig. 9B shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.
  • Fig. 16 schematically illustrates an alternative write logic-1 operation performed on a memory array according to an embodiment of the present invention.
  • FIGs. 29A and 29B are schematic, cross-sectional illustrations of a memory cell according to another embodiment of the present invention.
  • Fig. 41 is a schematic, cross-sectional illustration of a memory cell which can be used as a reference cell in sensing the state of a floating body memory cell according to an embodiment of the present invention.
  • Fig. IB illustrates a memory cell 50 according to an embodiment of the present invention, where memory device 50M is a bi-stable floating body device, for example as described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” ("Widjaja- 1"), U.S. Patent Application Publication No. 2010/0034041, "Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle" (“Widjaja-2”), U.S. Patent Application Publication No.
  • a gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24.
  • the gate 60 is insulated from the floating body region 24 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • the gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.
  • FIG. 6 shows an alternative array 122 where memory cells 100 are laid out in mirror configuration, where the source line region 16 (connected to the SL terminals 74) of one memory cell 100 is adjacent to a source line region 16 of a neighboring cell 100 with the bit line region 22 (connected to the BL terminals 76) being adjacent to the bit line region 22 of another neighboring cell 100, according to an embodiment of the present invention.
  • Figs. 16 and 17 illustrate exemplary bias conditions for a write logic- 1 operation through an impact ionization mechanism, performed on the memory array 120 and a selected memory cell 100, respectively, where the following bias conditions are applied: a positive voltage is applied to the selected WL2 terminal 72, a positive voltage is applied to the selected WL1 terminal 70, a positive voltage is applied to the selected BL terminal 76, zero voltage is applied to the SL terminal 74, zero or positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80.
  • Figs. 18 and 19 illustrate bias conditions for an exemplary write logic-1 operation through capacitive coupling from the gate 60 of the floating body transistor 40 to the floating body region 24, where the following bias conditions are applied: zero or low positive voltage is applied to the selected WL2 terminal 72, a positive bias is applied to the selected BL terminal 76, a positive voltage is applied to the SL terminal 74, a positive voltage is applied to the BW terminal 78, and zero voltage is applied to the SUB terminal 80.
  • the WL1 terminal is initially grounded, and then its potential is increased to a positive voltage.
  • Figs. 26 and 27 show alternative embodiments of memory cells 102 and 104, comprising a three-dimensional memory cell structure.
  • memory cells 102 and 104 have a fin structure 52 extending substantially perpendicular to, and above the top surface of the substrate 10.
  • Fin structure 52 is conductive and may be built on buried well layer 30 or well region 12.
  • Both memory cells 102 and 104 comprise floating body transistor 40 and access transistor 42.
  • floating body transistor 40 floating body region 24 is insulated by the buried well region 30, source line region 16, drain region 18, insulating layer 62, and insulating layer 26.
  • the well region 12 has the same conductivity type as the substrate 10.
  • the drain region 18 of the floating body transistor 40 is connected to the source region 20 of the access transistor 42 through a conductive element 44.
  • the conductive element 44 is not shown in Figs. 26 and 27.
  • Memory cells 100, 102, and 104 each have two transistors having the same conductivity type in series (two n-channel transistors 40 and 42 are used in the examples).
  • Fig. 28 illustrates another embodiment of memory cell 200, where the memory transistor 40 and the access transistor 42' are comprised of transistors having different conductivity type.
  • the floating body transistor 40 is similar to that of memory cell 100.
  • the access transistor 42' has a different conductivity type from access transistor 42 of memory cell 100, and may comprise an additional Access Transistor Substrate terminal 80'.
  • Fig. 33 shows a holding operation performed on memory array 220 according to an embodiment of the present invention, which follows the same mechanism as that of memory array 120.
  • the holding operation is performed by applying a positive back bias to the BW terminal 78, and zero bias on the WL1 terminal 70, WL2 terminal 72, SL terminal 74, SUB terminal 80, and BL terminal 76.
  • the positive back bias applied to the buried layer region 30 connected to the BW terminal 78 will maintain the state of the memory cell 200 that it is connected to by maintaining the charge stored in the floating body region 24 of the corresponding floating body transistor 40.
  • the access transistor 42 of the selected memory cell is biased such that the source region 20 of the access transistor 42 is floating, for example by having the bias applied to the BL terminal 76 to be greater than the difference between the bias applied to the gate 64 and the threshold voltage of the access transistor 42. Because the channel region of the floating body transistor 40 is now floating, when the potential of the gate region 60 (connected to the WLl terminal 70) is increased from zero (or negative voltage) to a positive voltage, the potential of the floating body region 24 will increase due to capacitive coupling. The positive bias applied to the buried well region 30 (through the BW terminal 78) will then generate holes through the impact ionization process, which maintains the positive charge of the floating body region 24.
  • Buried layer 330 may be formed by an ion implantation process on the material of substrate 310. Alternatively, buried layer 330 can be grown epitaxially on top of substrate 310.
  • Insulating layers 326 may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 326 insulate floating body transistor 340 from adjacent floating body transistor 340 and adjacent access transistor 342. The bottom of insulating layer 326 may reside inside the buried region 330 allowing buried region 330 to be continuous as shown in Fig. 45. Alternatively, the bottom of insulating layer 326 may reside below the buried region 330 (similar to how the insulating layer 26 may reside below the buried region 30 of the memory cell 100 as shown in Fig. 2). This requires a shallower insulating layer (like 28 in Fig.
  • STI shallow trench isolation
  • representative memory cell 300b will be representative of an unselected memory cell 300 sharing the same row as selected representative memory cell 300a
  • representative memory cell 300c will be representative of an unselected memory cell 300 sharing the same column as selected representative memory cell 300a
  • representative memory cell 300d will be representative of a memory cell 300 sharing neither a row or a column with selected representative memory cell 300a.
  • Fig. 51 illustrates an exemplary memory array 420 comprising memory cells 400, according to an embodiment of the present invention.
  • Present in Fig. 51 are WL terminals 470a through 470n connected to the gate regions 60, WL terminals 472a through 472n connected to the gate regions 64, SL terminals 476a through 476n connected to both the source line regions 18 and 18' of the floating body transistors 440 and 440', BL terminals 474a through 474p connected to the drain regions 16 of the floating body transistors 440, BL terminals 474'a through
  • exemplary memory array 420 shows that the source line regions 18 and 18' of the floating body transistors 440 and 440' are connected to the same SL terminal 372. However, each of the source line regions 18 and 18' may be connected to separate terminals, for example SL terminal 476 and SL terminal 476'.
  • the exemplary memory array 420 shows that the gate regions 60 and 64 are connected to separate WL terminals 470 and 472. In an alternate embodiment, the gate regions 60 and 64 may be connected to the same WL terminals.
  • Fig. 52 illustrates a schematic top-view of the memory cell 400 where the gate regions of the floating body transistors 440 and 440' are joined together, where connections between conductive materials 90 and 90' to the
  • the dual-port floating body transistor 40D is connected in series to the access transistors 42 A and 42B.
  • the drain region 18A of the floating body transistor 40D is connected to the source region 20A of the access transistor 42A of the port #1 through a conductive element 94A.
  • the drain region 18B of the floating body transistor 40D is connected to the source region 20B of the access transistor 42B of the port #2 through conductive element 94B.

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CN201380009774.4A CN104471648B (zh) 2012-02-16 2013-02-15 包括初级和二级电晶体的存储单元
EP13748573.6A EP2815402B1 (en) 2012-02-16 2013-02-15 Memory cell comprising first and second transistors and methods of operating
US14/380,779 US9905564B2 (en) 2012-02-16 2013-02-15 Memory cell comprising first and second transistors and methods of operating
KR1020147025821A KR102059884B1 (ko) 2012-02-16 2013-02-15 두개의 트랜지스터로 구성된 메모리셀과 그 동작 방법
JP2014557836A JP6362542B2 (ja) 2012-02-16 2013-02-15 第１および第２のトランジスタを備えるメモリセルおよび動作の方法
SG11201404871TA SG11201404871TA (en) 2012-02-16 2013-02-15 Memory cell comprising first and second transistors and methods of operating
US15/485,718 US10181471B2 (en) 2012-02-16 2017-04-12 Memory cell comprising first and second transistors and methods of operating
US16/219,359 US10797055B2 (en) 2012-02-16 2018-12-13 Memory cell comprising first and second transistors and methods of operating
US17/016,540 US11348922B2 (en) 2012-02-16 2020-09-10 Memory cell comprising first and second transistors and methods of operating
US17/743,248 US11974425B2 (en) 2012-02-16 2022-05-12 Memory cell comprising first and second transistors and methods of operating
US18/621,096 US20240243492A1 (en) 2007-05-02 2024-03-29 Memory Cell Comprising First and Second Transistors and Methods of Operating

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