JP4058403B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4058403B2 JP4058403B2 JP2003392342A JP2003392342A JP4058403B2 JP 4058403 B2 JP4058403 B2 JP 4058403B2 JP 2003392342 A JP2003392342 A JP 2003392342A JP 2003392342 A JP2003392342 A JP 2003392342A JP 4058403 B2 JP4058403 B2 JP 4058403B2
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- 239000004065 semiconductor Substances 0.000 title claims description 63
- 210000000746 body region Anatomy 0.000 claims description 92
- 239000000758 substrate Substances 0.000 claims description 53
- 230000002093 peripheral effect Effects 0.000 claims description 34
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000007599 discharging Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 104
- 238000004519 manufacturing process Methods 0.000 description 26
- 238000000034 method Methods 0.000 description 22
- 125000006850 spacer group Chemical group 0.000 description 18
- 239000012535 impurity Substances 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Description
前記周辺ロジック回路に用いられるトランジスタは、
前記第1の絶縁層によって前記半導体基板から絶縁された前記半導体層内に形成されており、
前記半導体層に形成された第1導電型の第2のソース領域および第1導電型の第2のドレイン領域と、前記半導体層のうち前記第2のソース領域と前記第2のドレイン領域との間に設けられた第2導電型の第2のボディ領域と、前記第2のボディ領域上に形成された第3の絶縁層と、前記第3の絶縁層上に形成され、該第3の絶縁層によって前記第2のボディ領域から絶縁されたゲート電極とを備え、
前記周辺ロジック回路の前記ゲート電極に沿った断面において、前記第2のボディ領域が前記第1の絶縁層と接する辺の長さは、該第2のボディ領域が前記第3の絶縁層と接する辺の長さと等しい。
図1は、本発明に係る第1の実施形態に従ったDRAM100の平面図である。本実施形態において、DRAM100の周辺部には、DRAM100を制御するための周辺回路が設けられていてよい。DRAM100は、ワード線WL、ビット線BLおよびソース線SLを備えている。ワード線WLおよびソース線SLはほぼ平行に延びており、ビット線BLはワード線WLおよびソース線SLに対してほぼ垂直方向へ延びている。ビット線コンタクトBCは、ビット線BLとビット線BLの下に設けられたドレイン領域(図2参照)とを電気的に接続している。
図15は、本発明に係る第3の実施形態に従ったDRAM300の平面図である。第3の実施形態は、ボディ領域336の形状が第2の実施形態のボディ領域236と異なる。ボディ領域336は、ビット線コンタクトBCに該当する領域において、側面に段差ST(図3(A)参照)を有しない。ボディ領域336は、ビット線コンタクトBCに該当する領域以外では、側面に段差STを有する。第2の実施形態の他の構成要素は、第1の実施形態の構成要素と同じでよい。
WL ワード線
BL ビット線
SL ソース線
110 半導体基板
120 BOX層
130 SOI層
132 ソース領域
134 ドレイン領域
136 ボディ領域
140 ゲート絶縁膜
150、152 ポリシリコンプラグ
160、162、164 シリサイド
170 STI
Claims (1)
- 半導体基板と、
前記半導体基板上に形成された第1の絶縁層と、
前記第1の絶縁層によって前記半導体基板から絶縁された半導体層と、
前記半導体層に形成された第1導電型のソース領域および第1導電型のドレイン領域と、
前記半導体層のうち前記ソース領域と前記ドレイン領域との間に設けられ、電荷を蓄積または放出することによってデータを記憶することができる第2導電型のボディ領域と、
前記ボディ領域上に形成された第2の絶縁層と、前記第2の絶縁層上に形成され、該第2の絶縁層によって前記ボディ領域から絶縁されたワード線と、
前記ドレイン領域に電気的に接続されたビット線と、
前記ボディ領域の底面と前記半導体基板とによって構成されるキャパシタと、
前記ボディ領域をメモリセルの一部として備えるDRAMと、
前記DRAMの周辺に形成された周辺ロジック回路とを備え、
前記ワード線に沿った断面において、前記ボディ領域は側面に段差を有し、該ボディ領域が前記第1の絶縁層と接する辺の長さは、該ボディ領域が前記第2の絶縁層と接する辺の長さよりも大きく、
前記周辺ロジック回路に用いられるトランジスタは、
前記第1の絶縁層によって前記半導体基板から絶縁された前記半導体層内に形成されており、
前記半導体層に形成された第1導電型の第2のソース領域および第1導電型の第2のドレイン領域と、
前記半導体層のうち前記第2のソース領域と前記第2のドレイン領域との間に設けられた第2導電型の第2のボディ領域と、
前記第2のボディ領域上に形成された第3の絶縁層と、
前記第3の絶縁層上に形成され、該第3の絶縁層によって前記第2のボディ領域から絶縁されたゲート電極とを備え、
前記周辺ロジック回路の前記ゲート電極に沿った断面において、前記第2のボディ領域が前記第1の絶縁層と接する辺の長さは、該第2のボディ領域が前記第3の絶縁層と接する辺の長さと等しいことを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003392342A JP4058403B2 (ja) | 2003-11-21 | 2003-11-21 | 半導体装置 |
US10/824,535 US7208799B2 (en) | 2003-11-21 | 2004-04-15 | Floating body cell dynamic random access memory with optimized body geometry |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2003392342A JP4058403B2 (ja) | 2003-11-21 | 2003-11-21 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005158869A JP2005158869A (ja) | 2005-06-16 |
JP4058403B2 true JP4058403B2 (ja) | 2008-03-12 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003392342A Expired - Fee Related JP4058403B2 (ja) | 2003-11-21 | 2003-11-21 | 半導体装置 |
Country Status (2)
Country | Link |
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US (1) | US7208799B2 (ja) |
JP (1) | JP4058403B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3898715B2 (ja) | 2004-09-09 | 2007-03-28 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP4664833B2 (ja) * | 2006-02-15 | 2011-04-06 | 株式会社東芝 | 半導体記憶装置 |
JP2007266569A (ja) | 2006-02-28 | 2007-10-11 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2007242950A (ja) * | 2006-03-09 | 2007-09-20 | Toshiba Corp | 半導体記憶装置 |
US7645617B2 (en) * | 2006-07-27 | 2010-01-12 | Hynix Semiconductor, Inc. | Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof |
JP2009117518A (ja) * | 2007-11-05 | 2009-05-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
KR100979362B1 (ko) * | 2008-04-24 | 2010-08-31 | 주식회사 하이닉스반도체 | 반도체 소자 및 그 제조 방법 |
US7933139B2 (en) * | 2009-05-15 | 2011-04-26 | Macronix International Co., Ltd. | One-transistor, one-resistor, one-capacitor phase change memory |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6424016B1 (en) * | 1996-05-24 | 2002-07-23 | Texas Instruments Incorporated | SOI DRAM having P-doped polysilicon gate for a memory pass transistor |
US5784311A (en) * | 1997-06-13 | 1998-07-21 | International Business Machines Corporation | Two-device memory cell on SOI for merged logic and memory applications |
JP4216483B2 (ja) | 2001-02-15 | 2009-01-28 | 株式会社東芝 | 半導体メモリ装置 |
JP3798659B2 (ja) | 2001-07-02 | 2006-07-19 | 株式会社東芝 | メモリ集積回路 |
JP4383718B2 (ja) | 2001-05-11 | 2009-12-16 | 株式会社東芝 | 半導体メモリ装置及びその製造方法 |
JP2003031693A (ja) * | 2001-07-19 | 2003-01-31 | Toshiba Corp | 半導体メモリ装置 |
KR100402392B1 (ko) | 2001-11-06 | 2003-10-17 | 삼성전자주식회사 | 트렌치 소자분리 구조를 갖는 반도체 소자 및 그 제조방법 |
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2003
- 2003-11-21 JP JP2003392342A patent/JP4058403B2/ja not_active Expired - Fee Related
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2004
- 2004-04-15 US US10/824,535 patent/US7208799B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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JP2005158869A (ja) | 2005-06-16 |
US20050133843A1 (en) | 2005-06-23 |
US7208799B2 (en) | 2007-04-24 |
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