TWI416678B - 半導體封裝及其製程 - Google Patents
半導體封裝及其製程 Download PDFInfo
- Publication number
- TWI416678B TWI416678B TW098106889A TW98106889A TWI416678B TW I416678 B TWI416678 B TW I416678B TW 098106889 A TW098106889 A TW 098106889A TW 98106889 A TW98106889 A TW 98106889A TW I416678 B TWI416678 B TW I416678B
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- Taiwan
- Prior art keywords
- wafer
- pins
- semiconductor package
- semiconductor wafer
- layer
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims abstract description 50
- 230000002093 peripheral effect Effects 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims description 108
- 239000002184 metal Substances 0.000 claims description 108
- 239000010410 layer Substances 0.000 claims description 98
- 239000008393 encapsulating agent Substances 0.000 claims description 65
- 238000007747 plating Methods 0.000 claims description 65
- 229910000679 solder Inorganic materials 0.000 claims description 44
- 239000012790 adhesive layer Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
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- 238000009413 insulation Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 153
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- 230000001681 protective effect Effects 0.000 description 4
- 238000000576 coating method Methods 0.000 description 3
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
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- 229910052718 tin Inorganic materials 0.000 description 2
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- 229910000881 Cu alloy Inorganic materials 0.000 description 1
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- 239000000084 colloidal system Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
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- 230000001788 irregular Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000002904 solvent Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
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Classifications
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- H01L23/495—Lead-frames or other flat leads
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Description
本發明是有關於一種半導體晶片封裝,且特別是有關於一種具有一凹穴結構的進階式四方扁平無引腳封裝(advanced Quad Flat No Lead,aQFN)及其製程。
由於使用者對於小尺寸晶片之處理能力的需求越來越大,因此半導體晶片也變得更加複雜。為了解決上述之問題,封裝技術逐漸發展,舉例而說,藉由增加引腳密度來降低一封裝體固定在一印刷電路板上的覆蓋面積。此外,有些封裝技術,例如四方扁平無引腳封裝(Quad Flat No Lead,QFN),可藉由提供多行的內引腳與外引腳連接至一導線架的一可拋棄部,來增加引腳密度。然而,這類之導線架的製作方式很難達成兩行以外的引腳,因此當使用者對於導線架之引腳密度的需求越來越高時,如何利用封裝技術來形成所需之引腳密度,實為一待解決之問題。
此外,除了增加引腳密度之外,使用者更希望能藉由其他的方式來降低封裝體的大小,例如是降低封裝體的高度。同時,也希望能維持一封裝膠體與引腳之間的結合力(mold locking),並促進封裝體能藉由表面黏著技術接合於一印刷電路板上。當然,也可以制定一符合上述之這些目的的封裝製程。然而,目前現有的封裝技術只能符合上述其中一些目的,而不符合多數或是所有的目的。
本發明提供一種半導體封裝,其包括一晶片座、多個引腳、一半導體晶片與一封裝膠體。晶片座包括(1)一具有一上表面且以一凹穴底部定義一凹穴的周圍邊緣區域,其中凹穴底部具有一中心部(2)一配置鄰接於周圍邊緣區域之上表面且面向凹穴的上傾斜部,以及(3)一配置鄰接於上傾斜部且面向凹穴的下傾斜部。這些引腳環繞晶片座。每一引腳具有一上表面、一下表面、一配置鄰接於每一引腳之上表面的上傾斜部以及一配置鄰接於每一引腳之下表面的下傾斜部。半導體晶片配置於凹穴底部的中心部且電性連接至這些引腳。封裝膠體形成於半導體晶片與這些引腳上,以實質上填充於凹穴且實質上覆蓋晶片座的上傾斜部與這些引腳的這些上傾斜部,而晶片座的下傾斜部與這些引腳的這些下傾斜部至少部分從封裝膠體的一下表面向外延伸。
本發明提出一種半導體封裝的製程。首先,提供一金屬承載板。金屬承載板包括(1)一基部,具有一上表面與一下表面(2)一中心突出部,具有一上表面且從基部向上延伸,中心突出部定義一基部之上表面的中心區域,中心區域具有一中心部(3)多個周圍突出部,每一周圍突出部具有一上表面且從基部向上延伸,並環繞中心突出部(4)一第一金屬鍍層,形成於中心突出部的上表面上與周圍突出部的上表面上,以及(5)一第二金屬鍍層,形成於對應中心區域下方、中心突出部下方以及這些周圍突出部下方之金屬承載板的下表面上。接著,貼附一第一半導體晶片於中心突出部。電性連接第一半導體晶片至這些周圍突出部至少一第一突出部上。然後,形成一封裝膠體於第一半導體晶片與這些周圍突出部上。最後,蝕刻第二金屬鍍層之外的金屬承載板之下表面的區域,以使這些周圍突出部與中心突出部分離而形成多個引腳與一晶片座,其中晶片座包括中心突出部與中心區域,每一引腳具有一配置鄰接每一引腳之一下表面的下傾斜部,晶片座具有一配置鄰接晶片座之一下表面的下傾斜部,晶片座的下傾斜部與每一引腳的下傾斜部至少部分從封裝膠體的一下表面向外延伸。
本發明更提供一種半導體封裝,其包括一晶片座、多個引腳、一半導體晶片以及一封裝膠體。晶片座包括(1)一基部,具有一上表面與一下表面(2)一突出部,從基部向上延伸且配置鄰接於基部的一周圍邊緣,其中突出部具有一上表面;(3)一第一側表面,延伸介於突出部的上表面與基部的下表面之間,其中第一側表面具有一相較於突出部之上表面更接近基部之下表面的第一尖端。這些引腳環繞晶片座。至少這些引腳之一具有一第二尖端的一第二側表面。第一半導體晶片,配置於基部的上表面,且電性連接至這些引腳。封裝膠體形成於第一半導體晶片與這些引腳上,以實質上覆蓋基部的上表面、第一尖端上方之第一側表面的至少一部分與第二尖端上方之第二側表面的至少一部分,而第一尖端下方之第一側表面的至少一部分與第二尖端下方之第二側表面的至少一部分突出於封裝膠體的一下表面。
為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
圖1為本發明之一實施例之一種半導體封裝的剖面示意圖。在本實施例中,封裝體100包括一具有一周圍邊緣區域114的晶片座101,其中周圍邊緣區域114以一凹穴底部112定義出一凹穴111。周圍邊緣區域114可完全地環繞凹穴111,但於其他實施例中,周圍邊緣區域114亦可部分地環繞凹穴111。凹穴底部112具有一中心部112a。凹穴底部112也可包括一環繞中心部112a的凹陷部112b。中心部112a例如是位於凹穴底部112的中央,但當當凹陷部112b的寬度不一致時,中心部112a亦可不位於凹穴底部112的中央。凹陷部112b可完全地可完全地環繞中心部112a,但於其他實施例中,凹陷部112b亦可部分地環繞中心部112a。晶片102藉由一黏著層(未繪示)貼附於凹穴底部112。黏著層例如是一導電黏著材料或一非導電黏著材料,其中非導電黏著材料例如是非導電環氧樹脂(epoxy)。在本實施例中,晶片102貼附於中心部112a。晶片102之主動面上的多個焊墊106透過多條焊線104電性連接至這些引腳171與至少部分周圍邊緣區域114。這些引腳171例如是完全環繞或部分地環繞晶片座101。
圖2為本發明之一實施例之一種晶片座的放大剖面示意圖。在本實施例中,晶片座101具有一側表面208,其中側表面208可完全地或部分地延伸環繞於晶片座101的一周長。圖2中,側表面208包括一配置鄰接於周圍邊緣區域114之一上表面151且面向凹穴111的上傾斜部208c。側表面208也包括一配置鄰接於上傾斜部208c且面向凹穴111的下傾斜部208a。周圍邊緣區域114亦包括一配置鄰接上表面151且朝著凹穴111的上傾斜部218。晶片座101之側表面208的上傾斜部208c與下傾斜部208a以及周圍邊緣區域114的上傾斜部218可以是直線或曲線,且不垂直於周圍邊緣區域114的上表面151。側表面208亦包括一尖端208b。
圖3為本發明之一實施例之一種引腳的放大剖面示意圖。在本實施例中,引腳171包括一側表面308,其中側表面308可完全地或部分地延伸環繞於引腳171的一周長。於圖3中,側表面308包括一配置鄰接於引腳171之一上表面155的上傾斜部308c。側表面308亦包括一配置鄰接於引腳171之一下表面157的下傾斜部308a。引腳171之側表面308的上傾斜部308c與下傾斜部308a可以是直線或曲線,且分別不垂直於引腳的上表面155與下表面157。側表面308亦包括一尖端308b。
請同時參考圖1、圖2與圖3,封裝膠體108形成於晶片102、晶片座101與引腳171上,以使封裝膠體108實質上填充於凹穴111與實質上覆蓋周圍邊緣區域114的上傾斜部218。封裝膠體108亦實質上覆蓋晶片座101的上傾斜部208c以及引腳171的上傾斜部308c。在此所述之“實質上”一詞,部分是意指封裝膠體108填充於具有晶片102配置於凹穴底部112的凹穴111,同時也意指封裝膠體108填充於凹穴111以充份地減小或降低氣泡與濕氣,且覆蓋晶片102、焊線104、側表面208的上傾斜部208c、周圍邊緣區域114的上傾斜部218以及引腳171的上傾斜部308c,用以提供足夠的保護來避免受到氧化、溼氣以及其他環境條件的影響以符合封裝需求。在本實施例中,晶片座101的下傾斜部208a與引腳171的下傾斜部308a至少部分從封裝膠體108的下表面160向外延伸。或者,晶片座101的下傾斜部208a或引腳171的下傾斜部308a至少部分從封裝膠體108的下表面160向外延伸。
側表面208的上傾斜部208c、周圍邊緣區域114的上傾斜部218以及引腳171的上傾斜部308c可顯著地增加接觸面積,因此除了封裝膠體108與晶片座101之間的黏著力以及封裝膠體108與引腳171之間的黏著力會增加之外,還可以提高封裝膠體108與晶片座101及引腳171之間的結合力(mold locking),同時亦可延長溼氣擴散於封裝體100內的時間與路徑。
在本實施例中,側表面208的上傾斜部208c與引腳171的上傾斜部308c實質上具有凹陷的輪廓。在此所述之“實質上”一詞指的是側表面208的上傾斜部208c與引腳171的上傾斜部308c大體而言為凹面,例如朝著晶片座101的中心與引腳171向內環繞,但側表面208的上傾斜部208c與引腳171的上傾斜部308c可包括不規則的表面或崎嶇不平的小尖端,例如為一粗糙表面,以遠離晶片座101的中心與引腳171向外環繞。舉例而言,圖3中引腳171的上傾斜部308c具有一整體形狀,其中此整體形狀朝著引腳171的中心向內環繞。同時,引腳171的上傾斜部308c是具有許多粗糙的結構。這些粗糙結構於封裝時可吸引封裝膠體108,因此可增加封裝膠體108內之引腳171的結合力。這些粗糙結構可以藉由精準地控制蝕刻速率或其他適合的製程來形成。同樣地,晶片座101的下傾斜部208a與引腳171的下傾斜部308a實質上具有凹陷的輪廓。在此所述之“實質上”一詞指的是晶片座101的下傾斜部208a與引腳171的下傾斜部308a大體而言為凹面,例如朝著晶片座101的中心與引腳171向內環繞。舉例而言,圖2中引腳171的下傾斜部308a具有一整體形狀,其中此整體形狀朝著引腳171的中心向內環繞。同理,周圍邊緣區域114的上傾斜部218實質上具有凹陷的輪廓。在此所述之“實質上”一詞指的是周圍邊緣區域114的上傾斜部218大體而言為凹面,例如朝著周圍邊緣區域114的中心向內環繞。舉例而言,圖2中周圍邊緣區域114的上傾斜部218具有一整體形狀,其中此整體形狀朝著周圍邊緣區域114的中心向內環繞。
在此必須了解的是,晶片座101可以有不同於上述實施例的描述。舉例來說,圖2中晶片座101包括一具有一上表面212與一下表面153的基部202,突出部213具有一上表面151,且從基部202延伸向上延伸並配置鄰接於基部202的一周圍邊緣。一側表面208延伸介於突出部213的上表面151與基部202的下表面153之間,且包括一尖端208b。一側表面218延伸介於突出部213的上表面151與基部202的上表面212之間。在本實施例中,基部202的上表面212包括一中心區域212a,其中晶片102配置於中心區域212a。基部202的上表面212可更包括一環繞中心區域212a的凹陷部212b。中心區域212a例如大約位於基部202之上表面212的中央,但當凹陷部212b的寬度不一致時,中心區域212a亦可不位於基部202之上表面212的中央。凹陷部212b例如是完全地環繞中心區域212a,但於其他實施例中,凹陷部212b亦可部分地環繞中心區域212a。
在此也必須了解的是,封裝膠體108亦可以有不同於上述實施例的描述。舉例而言,請參考圖1、圖2與圖3,封裝膠體108形成於晶片102、晶片座101與引腳171上,以使封裝膠體108實質上覆蓋基部202的上表面212與側表面218。封裝膠體108也實質上覆蓋於尖端208b上方之至少一部分的側表面208與尖端308b上方之至少一部分的側表面308。在此所述之“實質上”一詞,部分是意指封裝膠體108覆蓋於具有晶片102配置於其上表面212的基部202,同時也意指封裝膠體108覆蓋晶片102、焊線104、基板202的上表面212、側表面218、尖端208b上方之部分側表面208與尖端308b上方之部分側表面308,用以提供足夠的保護來避免受到氧化、溼氣以及其他環境條件的影響以符合封裝需求。在本實施例中,尖端208b下方的至少部分側表面208從封裝膠體108的下表面160向外突出。同理,尖端308b上方的至少部分側表面308從封裝膠體108的下表面160向外突出。
請再參考圖1,封裝體100更包括一配置於周圍邊緣區域114之上表面151的金屬鍍層116,或者,金屬鍍層116亦可以配置於突出部213之上表面151上,請參考圖2。封裝體100更包括一配置於晶片座101之下表面153的金屬鍍層117,請參考圖1,或者,金屬鍍層117亦可以配置於基部202之下表面153上,請參考圖2。請再參考圖1,封裝體100也可以更包括一配置於引腳171之上表面155的金屬鍍層126以及一配置於引腳171之下表面157的金屬鍍層127。金屬鍍層116、117、126、127例如是利用有電電鍍(electrolytic plating)或無電電鍍(electroless plating)的方式所形成。由於晶片座101的表面與引腳171的表面貼附金屬鍍層116、117、126、127,因此可於打線接合製程中有效提高焊線104的接合力,且亦可以保護晶片座101的下表面與引腳171的下表面,以避免受到氧化及其他環境條件的影響來以符合封裝需求。於較佳實施例中,金屬鍍層116、117、126、127可包括一連接於晶片座101之表面151、153以及引腳171之表面155、157的鎳層以及一覆蓋鎳層的金層或鈀層。或者,金屬鍍層116、117、126、127可包括一鎳合金以及一金層與一鈀層兩者之一或其組合。
請再同時參考圖1、圖2以及圖3,一隔開距離148是指晶片座101之下傾斜部208a與/或引腳171之下傾斜部308a從封裝膠體108的下表面160向外延伸的距離,於其他實施例中,此隔開距離148可以包括或省略金屬鍍層117、127的厚度。或者,隔開距離148可以參考尖端208b下方之部分側表面208與/或尖端308b下方之部分側表面308從封裝膠體108的下表面160向外延伸的距離。晶片座101與/或引腳171從封裝膠體108之下表面160向外延伸之突出部可藉由晶片座101與/或引腳171所暴露出的其他區域貼附焊料來提高晶片座101與引腳171於一電路板上的焊接性(solderability)。也就是說,可提高封裝體100藉由表面黏著技術而接合於電路板上的可靠度。在一實施例中,尖端208b相對於突出部213的上表面151更接近於基板202的下表面153,尖端308b相對於引腳171的上表面155更接近於引腳171的下表面157。
於其他實施例中,隔開距離148是介於晶片座101之厚度142與/或至少一引腳171的厚度142的大約20%與大約50%之間或介於大約25%與大約45%之間,但並不以此為限。於其他實施例中,隔開距離148亦可以介於厚度142的大約5%與大約75%之間。晶片座101的厚度142可以計算從周圍邊緣區域114之上表面151至晶片座101之下表面153之間的距離。如果金屬鍍層116、117配置於晶片座101的表面151、153,厚度142可以計算從金屬鍍層116之上表面150至金屬鍍層117的下表面152之間的距離。同理,以引腳171來說,如果金屬鍍層126、127配置於引腳171的表面155、157,厚度142可以計算從金屬鍍層126之上表面154至金屬鍍層127的下表面156之間的距離。在此必須說明的是,許多距離是以金屬鍍層116、117、126、127之表面作為計算的基準。然而,如果沒有金屬鍍層116、117、126、127的話,上述之這些距離可以以晶片座101的表面151、153或引腳171的表面155、157作為計算的基準來取得近似值。
在一實施例中,晶片座101包括金屬鍍層116、117的厚度142實質上等於至少一引腳171包括金屬鍍層126、127的厚度142,此厚度142大約為0.125毫米。在此實施例中,晶片座101與至少一引腳171突出於封裝膠體108之下表面160的隔開距離148是介於大約0.025毫米與大約0.0625毫米之間或介於大約0.03毫米與大約0.05毫米之間。同樣地,晶片座101之側表面208的尖端208b實質上與引腳171之側表面308的尖端308b等高。於其他實施例中,晶片座101的厚度142與/或至少一引腳171的厚度142可以大於或小於0.125毫米。
當隔開距離148在厚度142範圍之大約20%與大約55%之間所佔的百分比越大時,晶片座101與/或引腳171與封裝膠體108的結合力會趨於減少,此時,封裝體100藉由表面黏著技術而接合於一引刷電路板的可靠度會趨於增加。同時,底側所需的蝕刻時間與蝕刻成本也會相對增加,請參考圖6。也就是說,隔開距離148的選擇如同一厚度142的一百分比,其可以做為上述這些因素之間取捨的交換程度。
一模蓋厚度140可以參考封裝膠體108之一上表面164至金屬鍍層116之上表面150之間的距離。同樣地,以引腳171而言,模蓋厚度140可以計算封裝膠體108之上表面164至金屬鍍層126之上表面154之間的距離。如果模蓋厚度140夠大,晶片102與焊線104是可以被封裝膠體108包覆於內。在一實施例中,模蓋厚度140是介於大約0.4毫米與大約1毫米之間,例如是0.675毫米,雖然模蓋厚度140在晶片102與焊線104仍然被封裝膠體108包覆於內的情況下還可以更小一點。晶片102可以配置於具有凹穴111之晶片座101的凹穴底部112之中心部112a,請參考圖1。或者,晶片102可以配置於基部202之上表面212的中心區域212a,請參考圖2。
在圖1與圖2中,距離206是測量中心部112a(或中心區域212a)相對於金屬鍍層116之上表面150的一深度。距離204是測量凹陷部112b(或凹陷部212b)相對於金屬鍍層116之上表面150的一深度。在其他實施例中,距離206是介於距離204的大約55%與大約80%之間,但並不以此為限。在一實施例中,距離206大約是0.065毫米,距離204大約是0.095毫米。距離204與距離206可以大於或小於這些值,只要距離204與距離206在一極限內仍然小於晶片座101的厚度142,例如大約0.01毫米。較佳地,中心部112a(或中心區域212a)與凹陷部112b(或凹陷部212b)是蝕刻後的結果(請參考圖5),而不是利用電鍍來形成周圍邊緣區域114(或中央突出部213)。電鍍相對於後續的蝕刻製程可能需花費成本與消耗更多時間,請參考圖5。
當晶片102配置於凹穴底部112(或基部202的上表面212)時,晶片102的上表面會相對於金屬鍍層116之上表面150下降距離206,此時晶片102的上表面較鄰近金屬鍍層116的上表面150,且金屬鍍層116的上表面150相對於晶片102的上表面較低,而每一引腳171之金屬鍍層126的上表面154也相對於晶片102的上表面較低。因此,模蓋厚度140可以減小,以使封裝體100具有較薄之封裝厚度。此外,晶片102的下表面是相對鄰近金屬鍍層117的下表面152。因此,可以提高傳導晶片102所產生的熱能通過晶片座101之擴散效率。
請再同時參考圖1、圖2與圖3,一高度差146指的是通過中心部112a(或中心區域212a)之最高點的一平面166至封裝膠體108的下表面160之間的距離。封裝膠體108的下表面160至少大約對應於封裝膠體108於凹陷部112b(或凹陷部212b)內的下表面。在本發明之一實施例中,高度差146是介於大約0.02毫米與大約0.04毫米之間,但並不以此為限。在本發明之另一實施例,金屬鍍層116的上表面150可配置介於距離平面116上方大約0.05毫米與大約0.08毫米之間,但並不以此為限。晶片座101之側表面208的尖端208b與至少一引腳171之側表面308的尖端308b可配置於平面116的下方。高度差146與尖端208b、308b相對於平面166的位置可以藉由蝕刻來控制,例如經由一上側的蝕刻製程,請參考圖5。
距離144指的是封裝膠體108的側表面162至任何引腳171的側表面308之最小距離。請參考圖1,在圖1中所繪示的距離144如同從側表面162至最左側之外引腳171A之尖端308b的距離。在本發明之一實施例中,距離144是介於大約0.1毫米至大約0.3毫米之間,但本發明並不以此為限。部分的封裝膠體108在左邊最左側的外引腳171A(與在右邊最右側的外引腳171B相同)可以避免於分離製程(singulation)(請參考圖6)與使用封裝體100時外引腳171A、171B剝落(peeling)或分離的情形。
引腳間隔145指的是介於兩相鄰之引腳171中心的距離,也是指端子間距(terminal pitch)。在本發明之一實施例中,引腳間隔145是介於大約0.35毫米與0.55毫米之間,但並不以此為限。引腳間隔145可以藉由蝕刻來控制,例如經由一上側的蝕刻製程,請參考圖5。
在圖3中,一保護層310實質上覆蓋至少這些引腳171之一的下傾斜部308a。在此所述之“實質上”一詞是指保護層310覆蓋至少一引腳171的下傾斜部308a來保護下方的金屬以避免受到氧化、溼氣以及其他環境條件的影響以符合封裝需求。封裝膠體108實質上覆蓋引腳171的上傾斜部308c(或於尖端308b上方的部分側表面308),但是不完全覆蓋引腳171的下傾斜部308a(或於尖端308b下方的部分側表面308)或至少不覆蓋引腳171從封裝膠體108之下表面160向外延伸的下傾斜部308a。因此,保護層310是除了引腳171之下表面157上之保護的金屬鍍層127之外,可用來防止或減少下方金屬的氧化與腐蝕作用,其中保護層310例如是一銅或一銅合金。類似的保護層也可以應用於晶片座101的下傾斜部208a(或於尖端208b下方的部分側表面208)。在圖2中,一保護層210實質上覆蓋晶片座101的下傾斜部208a。保護層210與晶片座101之側表面153上保護的金屬鍍層117一同保護晶片座101下方的金屬,以符合封裝需求。
在一實施例中,保護層210、310可以包括一金屬鍍層。此金屬鍍層可以包括至少一錫層、一鎳層與一金層。或者,金屬鍍層可以包括一層二個或多個上述這些金屬的合金。金屬鍍層例如是利用浸沒法(immersion)、有電電鍍法(electrolytic plating)、無電電鍍法(electroless plating)或其他適合的方法而貼附於下傾斜部208a、308a。
在其他實施例中,保護層210、310可以包括一焊接材料。焊接材料可以包括一焊料膏。當保護的金屬鍍層117、127(無焊料膏)實質上覆蓋於晶片座101的下表面153與至少一引腳171的下表面157時,焊料膏可以有選擇地配置於下傾斜部208a、308a。在此所述之“實質上”一詞是指保護的金屬鍍層117、127覆蓋下表面153、157來保護在下方的金屬以避免受到氧化、溼氣以及其他環境條件的影響以符合封裝需求。保護的金屬鍍層117、127也可以於蝕刻時保護下方的金屬,請參考圖5。或者,焊料膏可以同時配置於下傾斜部208a、308a與下表面153、157上。然後,烘乾或硬化焊料膏。或者,焊料膏可以經由迴焊而硬化成一焊料凸塊。
在其他實施例中,保護層210、310可以包括一有機保焊層(organic solderability preservative layer,OSP layer)。有機保焊層可藉由浸沒法、一以有機材料為主之溶劑的漂洗法或其他適合的方法來貼附於下傾斜部208a、308a。有機材料可以是一以咪唑(imidazole)為主的材料。有機保焊層可以有選擇地配置於下傾斜部208a、308a或配置於下傾斜部208a、308a二者擇一、晶片座101的下表面153以及至少一引腳171的下表面157。如果有機保焊層配置於下表面153、157上,則去除有機保焊層之另外的處理程序也許可以被省去。詳細而言,因為當焊接晶片座101與至少一引腳171於一印刷電路板時,焊接時的溫度會蒸發有機保焊層。
使用一焊接材料與/或一有機材料作為保護層210、310的一部分,至少有以下兩個原因。第一,一般的焊接材料與有機材料相較於金屬材料較為便宜,其中金屬材料例如是鎳、金與錫。第二,焊接材料與有機材料可無須使用有電電鍍法或無電電鍍法即可以被應用於晶片座101與至少一引腳171上,可簡化保護層210、310的製作。
圖4為本發明之一實施例之一種金屬承載板之一部分的上視圖。請參考圖4,在本實施例中,金屬承載板400的形成方式如圖5所描述。金屬承載板400包括一基部402,其中基部402具有一從基部402向上延伸的中心突出部404。在此所述之“中心”一詞是指突出部404是大約位於部分金屬承載板400的中心內,請參考圖4。當然,圖4中的部分金屬承載板400可位於金屬承載板400的任何位置,包括金屬承載板400的接界邊緣。於圖4中,雖然中心突出部404是完全地延伸環繞基部402的一周長,但於其他實施例中,中心突出部404可以只有部分地延伸環繞基部402。多個周圍突出部406環繞基部402配置。於圖4中,雖然周圍突出部406實質上完全地環繞基部402,但於其他實施例中,周圍突出部406可以只有部分地延伸環繞基部402。一角落周圍突出部408位於部分金屬承載板400之一角落,且角落周圍突出部408可以有不同於周圍突出部408的外形與/或尺寸。在一封裝體進行表面黏著製程時,此角落周圍突出部408可以作為一公認標記來幫助定位。
金屬承載板400中畫斜線的部分(404、406與408)是沒有被蝕刻,也就是說,突出於金屬承載板400的其他部分(包括402)是於上側蝕刻(請參考圖5)時被蝕刻。在一實施例中,周圍突出部406配置至少三行在基部402的至少一側。在下側蝕刻(請參考圖6)之後,基部402與周圍突出部406彼此分開且形成晶片座101與引腳171,如同前述圖1至圖3所述。由於周圍突出部406不需要連接至一導線架的一可拋棄部,意即周圍突出部406如同一四方扁平無引腳封裝(QFN)導線架的框,因此相對於習之四方扁平無引腳封裝(QFN)的製作程序而言,利用圖5與圖6之製作程序可有效達成二行或多行之引腳171之設計。
在一實施例中,於下側蝕刻(請參考圖6)之後,中心突出部404可包括一接地段,其中一晶片(例如晶片102)藉由焊線(例如焊線104)電性連接至接地段。接地段可以是一包括完整中心突出部404的接地環。於其他實施例中,接地段可以是中心突出部404的一第一部分404a,一電源段可以是中心突出部404的一第二部分404b。在本實施例中,連接至接地段404a之基部402的一第一部分與連接至電源段404b之基部402的一第二部分是電性絕緣。藉由蝕刻法、分離法或其他適合的方式,例如沿著虛線410,來結構性地分開基部402的第一部分與基部402的第二部分,以達成電性絕緣。
在此必須了解的是,於圖4所示之部分金屬承載板400亦可以有以下之描述法。舉例而言,金屬層載板400包括一有一周圍邊緣區域404的一晶片放置區402。多個周圍凸塊406環繞晶片放置區402。
圖5繪示本發明之一實施例之一種金屬承載板的製程。一第一光阻層506形成於一銅板501的一上表面502上,一第二光阻層508形成銅板501的一下表面504上。第一光阻層506與第二光阻層508是利用塗佈法、電鍍法或其他適合的方法所形成。預先決定或選擇部分的第一光阻層506與第二光阻層508來進行曝光與顯影製程,以於銅板501上形成一第一曝光部510與一第二曝光部512。第一光阻層506與第二光阻層508於曝光後所產生光化學反應,可定義為一光罩。
接著,一第一金屬鍍層514形成於第一曝光部510,一第二金屬鍍層516形成於第二曝光部512。第一金屬鍍層514與第二金屬鍍層516與前述所述之金屬鍍層116、117、126、127具有相同的特性,在此不再贅述。接著,掀離第一光阻層506與第二光阻層508。之後,銅板501之上表面502沒有第一金屬鍍層514保護的區域518會被蝕刻,以形成金屬承載板500。此金屬承載板500包括前述所述之中心區域212a、中心突出部213與周圍突出部406。或者,蝕刻後可以形成如前述之部分金屬承載板500的晶片放置區402與周圍凸塊406。此種蝕刻操作方式指的是上側蝕刻。
金屬承載板500包括多個內連接部,例如內連接部500a、500b。每一內連接部500a(或500b)包括前述所述之中心區域212a、中心突出部213與周圍突出部406。
圖6繪示本發明之一實施例之一種半導體封裝的製程。請參考圖6,一晶片102貼附於一金屬承載板500之一部分的一中心區域212a(或晶片放置區402),例如內連接部500a、500b,其中每一晶片102是利用如同前述所說明之一黏著層(未繪示)來貼附。接著,每一晶片102藉由焊線104電性連接至周圍突出部406(或周圍凸塊406)。接著,一封裝膠體108形成於每一晶片102與每一周圍突出部406上。封裝膠體108材料例如是由人造樹脂(synthetic resin)之所組成,且藉由注模成形法所形成,其中注模成形法例如是移轉注模成形法(transfer molding)。接著,蝕刻金屬承載板500之下表面沒有保護之金屬鍍層516的區域620來分離周圍突出部406與中心突出部213,以形成前述所述之引腳171與晶片座101。此種蝕刻操作方式指的是下側蝕刻。引腳171與晶片座101形成於共用封裝膠體108之多個連接封裝體中之一,例如連接封裝體600a、600b。連接封裝體600a、600b可透過分離製程來彼此分離成封裝體100a、100b。分離製程可藉由例如鋸切處理來形成具有垂直側表面的封裝體100a、100b,請參考圖6。
圖7繪示本發明之一實施例之一種具有多堆疊晶片之半導體封裝的製程。一第一晶片102a貼附於一金屬承載板500之一部分的一中心區域212a(或晶片放置區402),例如內連接部500a、500b,其中每一第一晶片102a是利用如同前述所說明之一黏著層(未繪示)來貼附。然後,每一第一晶片102a藉由焊線104a電性連接至中心突出部213(或周圍邊緣區域114)至少一部分。在其他實施例中,每一第一晶片102a可以電性連接至一或多個周圍突出部406。
接著,一連接層700配置於每一第一晶片102a的上表面。接著,一第二晶片102b藉由連接層700接合至每一第一晶片102a的上表面。每一第二晶片102b可藉由焊線104b電性連接至周圍突出部406。於其他實施例中,每一第二晶片102b可以電性連接中心突出部213的至少一部份。第二晶片102b所連接之任何周圍突出部406或部分中心突出部213是與對應之第一晶片102b所連接之周圍突出部406或部分中心突出部213電性絕緣。
接著,封裝膠體108形成於每一堆疊之第一晶片102a與第二晶片102b以及周圍突出部406上。接著,蝕刻金屬承載板500之下表面沒有保護之金屬鍍層516的區域620來分離周圍突出部406與中心突出部213,以形成前述所述之引腳171與晶片座101。引腳171與晶片座101形成於共用封裝膠體108之多個連接封裝體中之一,例如連接封裝體600a、600b。連接封裝體600a、600b可透過分離製程來彼此分離成封裝體100a、100b。
在一實施例中,連接層700包括一黏著層。黏著層的材質例如是導電黏著材料或非導電黏著材料,其中非導電黏著材料例如是非導電環氧樹脂(epoxy)。黏著層可以是液體型態的黏著層或薄膜型態的黏著層,例如是一雙面膠。黏著層亦可以是一焊線上薄膜(film-on-wire)型黏著層,此焊線上薄膜型黏著層的特性與薄膜型態黏著層的特性相似,但其厚度比薄膜型態黏著層的厚度較厚。
在一實施例中,第二晶片102b延伸超過第一晶片102a的周圍。焊線上薄膜型黏著層的優點在於黏著層的厚度較厚,因此當第二晶片102b貼附於此黏著層時,仍然有間隙可以讓焊線104a焊接至第一晶片102a。如果不是使用此焊線上薄膜型黏著層,連接層700除了液體型態的黏著層與/或薄膜型態的黏著層之外還必需包括一間隙。此間隙的目的在於隔開第一晶片102a與第二晶片102b,以使焊線104a可焊接至第一晶片102a。
隨著上述製程之描述,可藉由將晶片102配置於凹穴底部112(或基部202的上表面212),而使所形成之封裝體100具有較薄之厚度。以圖7中之一具有堆疊晶片的封裝體100來說,藉由凹穴111來提供放置的空間而使得封裝體100具有較薄之厚度。此外,堆疊的順序也是很重要的。舉例來說,於圖7中,第二晶片102b延伸超過凹穴111且部分覆蓋於晶片座101的周圍邊緣區域114上’所以第二晶片102b不能放置於凹穴底部112。然而,第一晶片102a是按一定尺寸製作,所以第一晶片102a可於配置於凹穴底部112。在此實施例中,如果第一晶片102a的高度加上連接層700的高度夠大且足夠提供間隙於配置在周圍邊緣區域114上之金屬鍍層116的上表面150上方與焊線104a上方時,第二晶片102b可以堆疊於第一晶片102a的上表面。
圖8繪示本發明之一實施例之一種半導體封裝進行表面黏著製程的流程示意圖。隨著上述製程之描述,引腳171與晶片座101形成於共用封裝膠體108之多個連接封裝體中之一,例如連接封裝體600a、600b。在本實施例中,一焊料膏802實質上覆蓋至少一引腳171之一傾斜蝕刻區域308a,且一金屬鍍層127的一下表面156配置於此引腳171的下表面157上。接著,固化焊料膏802來定義一焊接介面802,以作為後序表面黏著製程之用。焊料膏802也可以實質上覆蓋晶片座101的一傾斜蝕刻區域208a與晶片座101之一金屬鍍層117的一下表面152。連接封裝體600a、600b可透過分離製程來彼此分離成封裝體100a、100b。
就表面黏著型封裝體100a而言,焊接介面800、802可以藉由迴焊製程而形成液化焊料塊804、806。接著,一印刷電路板808與液化焊料塊804、806相連接,之後,固化液化焊料塊804、806。焊接介面800、802於迴焊焊料進行表面黏著製程時具有足夠的焊料,因此焊料對所對應覆蓋之傾斜蝕刻區域208a與308a而言,如同一保護層。
除了利用焊料作為一保護層之外,圖8之表面黏著製程的其他優點在於:可以藉由迴焊焊接介面800、802來使封裝體100a進行表面黏著製程。焊接介面800、802經由迴焊會產生液態的焊料,此液態的焊料會移動於印刷電路板808上來作為封裝體100a進行表面黏著製程之用。
圖9繪示本發明之另一實施例之一種半導體封裝進行表面黏著製程的流程示意圖。在此實施例中,首先,提供一無焊接介面800、802的封裝體100來作為表面黏著製程之用。一晶片座101的一傾斜蝕刻區域208a與至少一引腳171的一傾斜蝕刻區域308a可覆蓋一保護層,例如是一有機保焊層,此有機保焊層如同前述所述。接著,焊料膏900配置於一準備用來給封裝體100進行表面黏著製程的印刷電路板908上。在封裝體100與印刷電路板908相互接近後,先迴焊焊料膏900後固化形成焊料塊902,以使封裝體100貼附於印刷電路板908上。
隨著上述製程之描述,印刷電板908上具有足夠的焊料膏900,以便於迴焊焊料膏900進行表面黏著製程時具有足夠的焊料,而焊料對所對應覆蓋之傾斜蝕刻區域208a與308a而言,如同一保護層。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、100a、100b...封裝體
101...晶片座
102...晶片
102a...第一晶片
102b...第二晶片
104、104a、104b...焊線
106...焊墊
108...封裝膠體
111...凹穴
112...凹穴底部
112a...中心部
112b...凹陷部
114...周圍邊緣區域
116、117、126、127...金屬鍍層
140...模蓋厚度
142...厚度
144...距離
145...引腳間隔
146...高度差
148...隔開距離
150、151、154、155、164...上表面
152、153、156、157、160...下表面
162...側表面
166...平面
171...引腳
171A、171B...外引腳
202...基部
204、206...距離
208...側表面
208a...下傾斜部
208b...尖端
208c...上傾斜部
210...保護層
212...上表面
212a...中心區域
212b...凹陷部
213...突出部
218...上傾斜部
308...側表面
308a...下傾斜部
308b...尖端
308c...上傾斜部
310...保護層
400...金屬承載板
402...基部(晶片放置區)
404...中心突出部(周圍邊緣區域)
404a...接地段
404b...電源段
406...周圍突出部(周圍凸塊)
408...角落周圍突出部
410...虛線
500...金屬承載板
500a、500b...內連接部
501...銅板
502...上表面
504...下表面
506、508...光阻層
510...第一曝光部
512...第二曝光部
514...第一金屬鍍層
516...第二金屬鍍層
518、620...區域
600a、600b...連接封裝體
700...連接層
800、802...焊接介面
804、806...液化焊料塊
808...印刷電路板
900...焊料
902...焊料塊
908...印刷電路板
圖1為本發明之一實施例之一種半導體封裝的剖面示意圖。
圖2為本發明之一實施例之一種晶片座的放大剖面示意圖。
圖3為本發明之一實施例之一種引腳的放大剖面示意圖。
圖4為本發明之一實施例之一種金屬承載板之一部分的上視圖。
圖5繪示本發明之一實施例之一種金屬承載板的製程。
圖6繪示本發明之一實施例之一種半導體封裝的製程。
圖7繪示本發明之一實施例之一種具有多堆疊晶片之半導體封裝的製程。
圖8繪示本發明之一實施例之一種半導體封裝進行表面黏著製程的流程示意圖。
圖9繪示本發明之另一實施例之一種半導體封裝進行表面製程的流程示意圖。
100...封裝體
101...晶片座
102...晶片
104...焊線
106...焊墊
108...封裝膠體
111...凹穴
112...凹穴底部
112a...中心部
112b...凹陷部
114...周圍邊緣區域
116、117、126、127...金屬鍍層
140...模蓋厚度
142...厚度
144...距離
145...引腳間隔
146...高度差
148...隔開距離
150、151、154、155、164...上表面
152、153、156、157、160...下表面
162...側表面
166...平面
171...引腳
171A、171B...外引腳
Claims (30)
- 一種半導體封裝,包括:一晶片座,包括:一周圍邊緣區域,具有一內傾斜表面、一外傾斜表面以及一連接該內傾斜表面與該外傾斜表面的上表面,且以一凹穴底部定義出一凹穴,其中該凹穴底部具有一晶片承載區域及一凹陷部,該凹陷部環繞並定義出該晶片承載區域,該凹陷部形成於該內傾斜表面與該晶片承載區域的一接合處,使得該內傾斜表面與該凹陷部之一表面為一連續曲面,而該外傾斜表面包括一上傾斜部、一下傾斜部及一尖端,該尖端位於該上傾斜部與該下傾斜部的一接合處;多個引腳,圍繞該晶片座,其中各該引腳包括:一上表面;一下表面;一上傾斜部,配置鄰接於各該引腳的該上表面;一下傾斜部,配置鄰接於各該引腳的該下表面;一第一半導體晶片,配置於該凹穴底部的該晶片承載區域且電性連接至該些引腳;以及一封裝膠體,形成於該第一半導體晶片與該些引腳上,以實質上填充於該凹穴且實質上覆蓋該晶片座的該內傾斜表面與該些引腳的該些上傾斜部,該晶片座的該下傾斜部與該些引腳的該些下傾斜部至少部分從該封裝膠體的一下表面向外延伸。
- 如申請專利範圍第1項所述之半導體封裝,其中該連續曲面實質上為拋物線狀。
- 如申請專利範圍第1項所述之半導體封裝,其中該晶片座的該周圍邊緣區域包括一接地段,該第一半導體晶片電性連接至該接地段。
- 如申請專利範圍第3項所述之半導體封裝,其中該晶片座的該周圍邊緣區域包括一電源段,該第一半導體晶片電性連接至該電源段,且該電源段與該接地段電性絕緣。
- 如申請專利範圍第1項所述之半導體封裝,其中至少該些引腳之一從該封裝膠體的該下表面向外延伸的一隔開距離介於0.025毫米至0.0625毫米之間。
- 如申請專利範圍第1項所述之半導體封裝,其中該晶片座包括一下表面,該周圍邊緣區域的該上表面至該晶片座的該下表面之間的一距離相當於該晶片座的厚度,該晶片座從該封裝膠體的該下表面向外延伸的一隔開距離介於該晶片座厚度的20%至50%之間。
- 如申請專利範圍第1項所述之半導體封裝,更包括:一第一金屬鍍層,配置於該周圍邊緣區域的該上表面與該些引腳的該些上表面上;一第二金屬鍍層,配置於該晶片座的該下表面與該些引腳的該些下表面上。
- 如申請專利範圍第7項所述之半導體封裝,其中至少該第一金屬鍍層與該第二金屬鍍層之一具有一第一鎳層 與一選自金與鈀所組成之族群的第二金屬層。
- 如申請專利範圍第1項所述之半導體封裝,其中該晶片承載區域相對於該周圍邊緣區域之該上表面的一深度是介於該凹陷部相對於該周圍邊緣區域之該上表面的一深度的55%至80%之間。
- 如申請專利範圍第1項所述之半導體封裝,其中該些引腳配置至少三行於該晶片座的至少一側。
- 如申請專利範圍第1項所述之半導體封裝,其中從該封裝體之一側表面至任一該些引腳之一側表面的一距離具有一介於0.1毫米與0.3毫米之間的最小值。
- 如申請專利範圍第1項所述之半導體封裝,其中該晶片座的該上傾斜部與該下傾斜部與該些引腳的該些上傾斜部與該些下傾斜部實質上皆具有凹陷的輪廓。
- 如申請專利範圍第1項所述之半導體封裝,更包括一連接層與一第二半導體晶片,該第二半導體晶片透過該連接層接合至該第一半導體晶片的一上表面,其中封裝膠體形成於該第二半導體晶片上,且該連接層包括一黏著層。
- 如申請專利範圍第1項所述之半導體封裝,更包括一連接層與一第二半導體晶片,該第二半導體晶片透過該連接層接合至該第一半導體晶片的一上表面,其中該第二半導體晶片延伸至該第一半導體晶片的一周圍邊緣之外。
- 如申請專利範圍第14項所述之半導體封裝,其中 該連接層包括一焊線上薄膜型黏著層。
- 如申請專利範圍第14項所述之半導體封裝,其中該連接層包括一間隙與一黏著層。
- 一種半導體封裝製程,包括:提供一金屬承載板,該金屬承載板包括:一基部,具有一上表面與一下表面;一中心突出部,具有一上表面且從該基部向上延伸,該中心突出部定義一該基部之該上表面的中心區域,且該中心區域具有一中心部;多個周圍突出部,各該周圍突出部具有一上表面且從該基部向上延伸,並環繞該中心突出部;一第一金屬鍍層,形成於該中心突出部的該上表面上與該周圍突出部的該上表面上;一第二金屬鍍層,形成於對應該中心區域下方、該中心突出部下方以及該些周圍突出部下方之該金屬承載板的該下表面上;貼附一第一半導體晶片於該中心突出部;電性連接該第一半導體晶片至該些周圍突出部至少一第一突出部上;形成一封裝膠體於該第一半導體晶片與該些周圍突出部上;以及蝕刻該第二金屬鍍層之外的該金屬承載板之該下表面的區域,以使該些周圍突出部與該中心突出部分離而形成多個引腳與一晶片座,其中該晶片座包括該中心突出部 與該中心區域,各該引腳具有一配置鄰接各該引腳之一下表面的下傾斜部,該晶片座具有一配置鄰接該晶片座之一下表面的下傾斜部,該晶片座的該下傾斜部與各該引腳的該下傾斜部至少部分從該封裝膠體的一下表面向外延伸。
- 如申請專利範圍第17項所述之半導體封裝製程,其中形成該金屬承載板的步驟,包括:提供一銅板,該銅板具有一上表面與一下表面;塗佈一第一光阻層於該銅板的該上表面上以及一第二光阻層與該銅板的該下表面上;對該第一光阻層與該第二光阻層進行曝光與顯影,以於該銅板之該上表面形成一第一曝光部以及於該銅板之該下表面形成一第二曝光部;形成一第一金屬鍍層於該第一曝光部以及一第二金屬鍍層於該第二曝光部;移除該第一光阻層;蝕刻該第一金屬鍍層之外的該銅層之該上表面,以形成該中心區域、該中心突出部與該些周圍突出部;以及移除該第二光阻層。
- 如申請專利範圍第17項所述之半導體封裝製程,其中該中心區域具有一環繞該中心部的凹陷部。
- 如申請專利範圍第17項所述之半導體封裝製程,其中該晶片座的該下傾斜部與至少該些引腳之一的該下傾斜部突出於該封裝膠體之該下表面的一隔開距離介於0.025毫米至0.0625毫米之間。
- 如申請專利範圍第17項所述之半導體封裝製程,更包括:藉由一連接層貼附一第二半導體晶片於該第一半導體晶片的一上表面上,該連接層包括一間隙與一黏著層,其中該第二半導體晶片延伸至該第一半導體晶片的一周圍邊緣之外;以及電性連接該第二半導體晶片至該些周圍突出部至少一第二突出部上,其中該封裝膠體形成於該第二半導體晶片上。
- 如申請專利範圍第17項所述之半導體封裝製程,更包括:藉由一連接層貼附一第二半導體晶片於該第一半導體晶片的一上表面上,該連接層包括一焊線上薄膜型黏著層,其中該第二半導體晶片延伸至該第一半導體晶片的一周圍邊緣之外;以及電性連接該第二半導體晶片至該些周圍突出部至少一第二突出部上,其中該封裝膠體形成於該第二半導體晶片上。
- 一種半導體封裝,包括:一晶片座,包括:一基部,具有一上表面與一下表面;一突出部,從該基部向上延伸且配置鄰接於該基部的一周圍邊緣,其中該突出部具有一上表面;一第一側表面,延伸介於該突出部的該上表面與 該基部的該下表面之間,其中該第一側表面具有一相較於該突出部之該上表面更接近該基部之該下表面的第一尖端;多個引腳,環繞該晶片座,至少該些引腳之一包含一第二尖端的一第二側表面;一第一半導體晶片,配置於該基部的該上表面,且電性連接至該些引腳;一封裝膠體,形成於該第一半導體晶片與該些引腳上,以實質上覆蓋該基部的該上表面、該第一尖端上方之該第一側表面的至少一部分與該第二尖端上方之該第二側表面的至少一部分,使得該第一尖端下方之該第一側表面的至少一部分與該第二尖端下方之該第二側表面的至少一部分突出於該封裝膠體的一下表面。
- 如申請專利範圍第23項所述之半導體封裝,其中至少該些引腳之一突出於該封裝膠體之該下表面的一隔開距離介於至少該些引腳之一厚度的20%至50%之間。
- 如申請專利範圍第23項所述之半導體封裝,其中該晶片座突出於該封裝膠體之該下表面的一隔開距離介於0.025毫米至0.0625毫米之間。
- 如申請專利範圍第23項所述之半導體封裝,其中該基板之該上表面包括:一中心區域,該第一半導體晶片配置於該中心區域;以及一凹陷部,環繞該中心區域。
- 如申請專利範圍第26項所述之半導體封裝,其中該中心區域定義為一平面,且該第一尖端配置於該平面的下方。
- 如申請專利範圍第27項所述之半導體封裝,其中該突出部的該上表面配置於該平面上方介於0.05毫米至0.08毫米之間。
- 如申請專利範圍第23項所述之半導體封裝,更包括一連接層與一第二半導體晶片,該第二半導體晶片透過該連接層接合至該第一半導體晶片的一上表面,其中該第二半導體晶片延伸至該第一半導體晶片的一周圍邊緣之外。
- 如申請專利範圍第23項所述之半導體封裝,其中該第一尖端的高度實質上與該第二尖端的高度相同。
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US12/192,702 US8492883B2 (en) | 2008-03-14 | 2008-08-15 | Semiconductor package having a cavity structure |
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Families Citing this family (152)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8236612B2 (en) * | 2002-04-29 | 2012-08-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7790500B2 (en) * | 2002-04-29 | 2010-09-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7799611B2 (en) * | 2002-04-29 | 2010-09-21 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US8487451B2 (en) | 2006-04-28 | 2013-07-16 | Utac Thai Limited | Lead frame land grid array with routing connector trace under unit |
US8492906B2 (en) | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
US8310060B1 (en) | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US9082607B1 (en) | 2006-12-14 | 2015-07-14 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US9761435B1 (en) | 2006-12-14 | 2017-09-12 | Utac Thai Limited | Flip chip cavity package |
US7777310B2 (en) * | 2007-02-02 | 2010-08-17 | Stats Chippac Ltd. | Integrated circuit package system with integral inner lead and paddle |
US7875988B2 (en) * | 2007-07-31 | 2011-01-25 | Seiko Epson Corporation | Substrate and manufacturing method of the same, and semiconductor device and manufacturing method of the same |
US7790512B1 (en) | 2007-11-06 | 2010-09-07 | Utac Thai Limited | Molded leadframe substrate semiconductor package |
US8212339B2 (en) * | 2008-02-05 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8350367B2 (en) | 2008-02-05 | 2013-01-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US7989928B2 (en) | 2008-02-05 | 2011-08-02 | Advanced Semiconductor Engineering Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8022511B2 (en) | 2008-02-05 | 2011-09-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20090230524A1 (en) | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Semiconductor chip package having ground and power regions and manufacturing methods thereof |
JP4567773B2 (ja) * | 2008-07-18 | 2010-10-20 | 三菱電機株式会社 | 電力用半導体装置 |
US8410584B2 (en) | 2008-08-08 | 2013-04-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
JP2010056372A (ja) * | 2008-08-29 | 2010-03-11 | Sanyo Electric Co Ltd | 樹脂封止型半導体装置とその製造方法 |
US9947605B2 (en) | 2008-09-04 | 2018-04-17 | UTAC Headquarters Pte. Ltd. | Flip chip cavity package |
TW201021119A (en) * | 2008-09-25 | 2010-06-01 | Lg Innotek Co Ltd | Structure and manufacture method for multi-row lead frame and semiconductor package |
US20100110656A1 (en) | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8106502B2 (en) * | 2008-11-17 | 2012-01-31 | Stats Chippac Ltd. | Integrated circuit packaging system with plated pad and method of manufacture thereof |
JP2010129591A (ja) * | 2008-11-25 | 2010-06-10 | Mitsui High Tec Inc | リードフレーム、このリードフレームを用いた半導体装置及びその中間製品、並びにこれらの製造方法 |
US20100207257A1 (en) * | 2009-02-17 | 2010-08-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
US8110902B2 (en) | 2009-02-19 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US8673687B1 (en) | 2009-05-06 | 2014-03-18 | Marvell International Ltd. | Etched hybrid die package |
US8044495B2 (en) * | 2009-06-22 | 2011-10-25 | Texas Instruments Incorporated | Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds |
US8212340B2 (en) | 2009-07-13 | 2012-07-03 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
US9449900B2 (en) | 2009-07-23 | 2016-09-20 | UTAC Headquarters Pte. Ltd. | Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow |
US8803300B2 (en) * | 2009-10-01 | 2014-08-12 | Stats Chippac Ltd. | Integrated circuit packaging system with protective coating and method of manufacture thereof |
US8502357B2 (en) * | 2009-10-01 | 2013-08-06 | Stats Chippac Ltd. | Integrated circuit packaging system with shaped lead and method of manufacture thereof |
US20110108966A1 (en) * | 2009-11-11 | 2011-05-12 | Henry Descalzo Bathan | Integrated circuit packaging system with concave trenches and method of manufacture thereof |
US8030750B2 (en) | 2009-11-19 | 2011-10-04 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8368185B2 (en) | 2009-11-19 | 2013-02-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
US8378466B2 (en) | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
US8368189B2 (en) * | 2009-12-04 | 2013-02-05 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US9355940B1 (en) | 2009-12-04 | 2016-05-31 | Utac Thai Limited | Auxiliary leadframe member for stabilizing the bond wire process |
US8435837B2 (en) * | 2009-12-15 | 2013-05-07 | Silicon Storage Technology, Inc. | Panel based lead frame packaging method and device |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8575732B2 (en) | 2010-03-11 | 2013-11-05 | Utac Thai Limited | Leadframe based multi terminal IC package |
TWI453844B (zh) * | 2010-03-12 | 2014-09-21 | 矽品精密工業股份有限公司 | 四方平面無導腳半導體封裝件及其製法 |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8222726B2 (en) * | 2010-03-29 | 2012-07-17 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having a jumper chip and method of fabricating the same |
KR101192181B1 (ko) * | 2010-03-31 | 2012-10-17 | (주)포인트엔지니어링 | 광 소자 디바이스 및 그 제조 방법 |
US8373279B2 (en) * | 2010-04-23 | 2013-02-12 | Infineon Technologies Ag | Die package |
TWI429043B (zh) | 2010-04-26 | 2014-03-01 | Advance Materials Corp | 電路板結構、封裝結構與製作電路板的方法 |
US20110316163A1 (en) * | 2010-06-24 | 2011-12-29 | Byung Tai Do | Integrated circuit packaging system with molded interconnects and method of manufacture thereof |
US9059151B2 (en) * | 2010-07-20 | 2015-06-16 | Stats Chippac Ltd. | Integrated circuit packaging system with island terminals and embedded paddle and method of manufacture thereof |
TWI540698B (zh) | 2010-08-02 | 2016-07-01 | 日月光半導體製造股份有限公司 | 半導體封裝件與其製造方法 |
US8669654B2 (en) * | 2010-08-03 | 2014-03-11 | Stats Chippac Ltd. | Integrated circuit packaging system with die paddle and method of manufacture thereof |
US8476772B2 (en) | 2010-09-09 | 2013-07-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die |
US8304277B2 (en) * | 2010-09-09 | 2012-11-06 | Stats Chippac, Ltd. | Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking |
US9007273B2 (en) | 2010-09-09 | 2015-04-14 | Advances Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
TWI420630B (zh) * | 2010-09-14 | 2013-12-21 | Advanced Semiconductor Eng | 半導體封裝結構與半導體封裝製程 |
US8404524B2 (en) | 2010-09-16 | 2013-03-26 | Stats Chippac Ltd. | Integrated circuit packaging system with paddle molding and method of manufacture thereof |
KR101121862B1 (ko) | 2010-09-17 | 2012-03-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
US8669649B2 (en) * | 2010-09-24 | 2014-03-11 | Stats Chippac Ltd. | Integrated circuit packaging system with interlock and method of manufacture thereof |
CN101944520B (zh) * | 2010-09-26 | 2012-06-27 | 日月光半导体制造股份有限公司 | 半导体封装结构与半导体封装工艺 |
US8912046B2 (en) | 2010-10-28 | 2014-12-16 | Stats Chippac Ltd. | Integrated circuit packaging system with lead frame and method of manufacture thereof |
TWI419290B (zh) | 2010-10-29 | 2013-12-11 | Advanced Semiconductor Eng | 四方扁平無引腳封裝及其製作方法 |
US20120119342A1 (en) * | 2010-11-11 | 2012-05-17 | Mediatek Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
TWI455213B (zh) * | 2010-12-15 | 2014-10-01 | Chipmos Technologies Inc | 無外引腳封裝結構及其製作方法 |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US20120200281A1 (en) * | 2011-02-07 | 2012-08-09 | Texas Instruments Incorporated | Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing |
US8735224B2 (en) * | 2011-02-14 | 2014-05-27 | Stats Chippac Ltd. | Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof |
US20120205811A1 (en) * | 2011-02-14 | 2012-08-16 | Byung Tai Do | Integrated circuit packaging system with terminal locks and method of manufacture thereof |
US8969136B2 (en) * | 2011-03-25 | 2015-03-03 | Stats Chippac Ltd. | Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof |
TW201241970A (en) * | 2011-04-08 | 2012-10-16 | Advanced Semiconductor Eng | Semiconductor package with recesses in the edged leadas |
US20120261689A1 (en) * | 2011-04-13 | 2012-10-18 | Bernd Karl Appelt | Semiconductor device packages and related methods |
CN102184908A (zh) * | 2011-04-26 | 2011-09-14 | 日月光半导体制造股份有限公司 | 进阶式四方扁平无引脚封装结构及其制作方法 |
CN102214635A (zh) * | 2011-05-27 | 2011-10-12 | 日月光半导体制造股份有限公司 | 半导体封装结构及其制作方法 |
US9035440B2 (en) | 2011-06-23 | 2015-05-19 | Stats Chippac Ltd. | Integrated circuit packaging system with a lead and method of manufacture thereof |
US8957509B2 (en) * | 2011-06-23 | 2015-02-17 | Stats Chippac Ltd. | Integrated circuit packaging system with thermal emission and method of manufacture thereof |
CN103843133B (zh) * | 2011-07-03 | 2017-10-27 | 联达科技控股有限公司 | 具有热熔接封装部件的引线载体 |
US8502363B2 (en) | 2011-07-06 | 2013-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with solder joint enhancement element and related methods |
CN102263079B (zh) * | 2011-07-18 | 2017-06-09 | 日月光半导体制造股份有限公司 | 半导体封装结构 |
TWI441296B (zh) * | 2011-07-19 | 2014-06-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
CN102263081A (zh) * | 2011-07-29 | 2011-11-30 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法 |
CN102263080B (zh) * | 2011-07-29 | 2015-06-17 | 天水华天科技股份有限公司 | 带双凸点的四边扁平无引脚三ic芯片封装件及其生产方法 |
CN105448877B (zh) * | 2011-08-01 | 2019-08-23 | 日月光半导体制造股份有限公司 | 半导体封装 |
US20130133193A1 (en) * | 2011-11-28 | 2013-05-30 | Mediatek Singapore Pte. Ltd. | Surface mount technology process for advanced quad flat no-lead package process and stencil used therewith |
US8541883B2 (en) | 2011-11-29 | 2013-09-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device having shielded conductive vias |
TWI505425B (zh) * | 2012-01-30 | 2015-10-21 | Advanced Semiconductor Eng | 整合屏蔽膜之半導體封裝件及其製造方法 |
US8674487B2 (en) * | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
US9653656B2 (en) | 2012-03-16 | 2017-05-16 | Advanced Semiconductor Engineering, Inc. | LED packages and related methods |
US9799589B2 (en) * | 2012-03-23 | 2017-10-24 | STATS ChipPAC Pte. Ltd. | Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof |
US8937376B2 (en) | 2012-04-16 | 2015-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with heat dissipation structures and related methods |
US8786060B2 (en) | 2012-05-04 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package integrated with conformal shield and antenna |
US9029198B2 (en) | 2012-05-10 | 2015-05-12 | Utac Thai Limited | Methods of manufacturing semiconductor devices including terminals with internal routing interconnections |
US9449905B2 (en) | 2012-05-10 | 2016-09-20 | Utac Thai Limited | Plated terminals with routing interconnections semiconductor device |
US8704341B2 (en) | 2012-05-15 | 2014-04-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with thermal dissipation structures and EMI shielding |
US8653634B2 (en) | 2012-06-11 | 2014-02-18 | Advanced Semiconductor Engineering, Inc. | EMI-shielded semiconductor devices and methods of making |
US9397031B2 (en) | 2012-06-11 | 2016-07-19 | Utac Thai Limited | Post-mold for semiconductor package having exposed traces |
TWI459517B (zh) | 2012-06-14 | 2014-11-01 | 矽品精密工業股份有限公司 | 封裝基板暨半導體封裝件及其製法 |
US9153542B2 (en) | 2012-08-01 | 2015-10-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having an antenna and manufacturing method thereof |
US9059379B2 (en) | 2012-10-29 | 2015-06-16 | Advanced Semiconductor Engineering, Inc. | Light-emitting semiconductor packages and related methods |
US9324584B2 (en) * | 2012-12-14 | 2016-04-26 | Stats Chippac Ltd. | Integrated circuit packaging system with transferable trace lead frame |
US20140165389A1 (en) * | 2012-12-14 | 2014-06-19 | Byung Tai Do | Integrated circuit packaging system with routable grid array lead frame |
CN103021879B (zh) * | 2012-12-28 | 2015-09-09 | 日月光半导体(昆山)有限公司 | 无外引脚半导体封装构造及其制造方法与导线架条 |
CN103021892B (zh) * | 2012-12-28 | 2016-05-11 | 日月光半导体(昆山)有限公司 | 无外引脚半导体封装构造及其制造方法与导线架条 |
US9013028B2 (en) * | 2013-01-04 | 2015-04-21 | Texas Instruments Incorporated | Integrated circuit package and method of making |
US9978688B2 (en) | 2013-02-28 | 2018-05-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package having a waveguide antenna and manufacturing method thereof |
US20140357022A1 (en) * | 2013-06-04 | 2014-12-04 | Cambridge Silicon Radio Limited | A qfn with wettable flank |
US9012268B2 (en) * | 2013-06-28 | 2015-04-21 | Stmicroelectronics, Inc. | Leadless packages and method of manufacturing same |
US9368423B2 (en) * | 2013-06-28 | 2016-06-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using substrate with conductive posts and protective layers to form embedded sensor die package |
CN103400825B (zh) | 2013-07-31 | 2016-05-18 | 日月光半导体制造股份有限公司 | 半导体封装件及其制造方法 |
US9978667B2 (en) * | 2013-08-07 | 2018-05-22 | Texas Instruments Incorporated | Semiconductor package with lead frame and recessed solder terminals |
CN104425396A (zh) * | 2013-09-02 | 2015-03-18 | 日月光半导体制造股份有限公司 | 半导体封装结构及其制造方法 |
GB201318911D0 (en) * | 2013-10-25 | 2013-12-11 | Litecool Ltd | LED Package |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
CN104112728B (zh) * | 2013-11-22 | 2017-10-31 | 广东美的制冷设备有限公司 | 器件安装结构和集成电路模块 |
US9484278B2 (en) * | 2013-11-27 | 2016-11-01 | Infineon Technologies Ag | Semiconductor package and method for producing the same |
GB2525585B (en) * | 2014-03-20 | 2018-10-03 | Micross Components Ltd | Leadless chip carrier |
TWI550784B (zh) * | 2014-04-18 | 2016-09-21 | 南茂科技股份有限公司 | 扁平無引腳封裝及其製造方法 |
US9219025B1 (en) * | 2014-08-15 | 2015-12-22 | Infineon Technologies Ag | Molded flip-clip semiconductor package |
DE102014114982B4 (de) * | 2014-10-15 | 2023-01-26 | Infineon Technologies Ag | Verfahren zum Bilden einer Chip-Baugruppe |
DE102014117897B4 (de) | 2014-12-04 | 2022-01-13 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung von optoelektronischen Modulen und Anordnung mit einem solchen Modul |
US9748187B2 (en) | 2014-12-19 | 2017-08-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Wafer structure and method for wafer dicing |
KR102334377B1 (ko) * | 2015-02-17 | 2021-12-02 | 삼성전자 주식회사 | 실링 영역 및 디커플링 커패시터 영역을 포함하는 반도체 소자 |
US9570381B2 (en) | 2015-04-02 | 2017-02-14 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages and related manufacturing methods |
JP2016219520A (ja) * | 2015-05-18 | 2016-12-22 | Towa株式会社 | 半導体装置及びその製造方法 |
JP6555927B2 (ja) * | 2015-05-18 | 2019-08-07 | 大口マテリアル株式会社 | 半導体素子搭載用リードフレーム及び半導体装置の製造方法 |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
US9515032B1 (en) * | 2015-08-13 | 2016-12-06 | Win Semiconductors Corp. | High-frequency package |
US9373569B1 (en) * | 2015-09-01 | 2016-06-21 | Texas Instruments Incorporation | Flat no-lead packages with electroplated edges |
US9922843B1 (en) | 2015-11-10 | 2018-03-20 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple molding routing layers and a method of manufacturing the same |
WO2017181399A1 (en) * | 2016-04-22 | 2017-10-26 | Texas Instruments Incorporated | Improved lead frame system |
US10276477B1 (en) | 2016-05-20 | 2019-04-30 | UTAC Headquarters Pte. Ltd. | Semiconductor package with multiple stacked leadframes and a method of manufacturing the same |
JP6788825B2 (ja) * | 2016-07-20 | 2020-11-25 | 大日本印刷株式会社 | リードフレームおよび半導体装置 |
JP6761738B2 (ja) * | 2016-11-15 | 2020-09-30 | 新光電気工業株式会社 | リードフレーム及びその製造方法、電子部品装置の製造方法 |
JP6777365B2 (ja) * | 2016-12-09 | 2020-10-28 | 大口マテリアル株式会社 | リードフレーム |
CN106783792A (zh) * | 2017-03-22 | 2017-05-31 | 江苏长电科技股份有限公司 | 一种塑封体侧面引脚具有侧边爬锡性能的封装结构 |
US9972558B1 (en) * | 2017-04-04 | 2018-05-15 | Stmicroelectronics, Inc. | Leadframe package with side solder ball contact and method of manufacturing |
US20180315725A1 (en) * | 2017-04-26 | 2018-11-01 | Nanya Technology Corporation | Package structure having bump with protective anti-oxidation coating |
CN107146777A (zh) * | 2017-05-27 | 2017-09-08 | 江苏长电科技股份有限公司 | 一种免切割封装结构及其制造工艺 |
US10204814B1 (en) * | 2017-07-28 | 2019-02-12 | Stmicroelectronics, Inc. | Semiconductor package with individually molded leadframe and die coupled at solder balls |
US10529672B2 (en) * | 2017-08-31 | 2020-01-07 | Stmicroelectronics, Inc. | Package with interlocking leads and manufacturing the same |
CN108417522B (zh) * | 2018-01-17 | 2021-01-01 | 桂林电子科技大学 | 三层板结构电路封装方法 |
US10593612B2 (en) | 2018-03-19 | 2020-03-17 | Stmicroelectronics S.R.L. | SMDs integration on QFN by 3D stacked solution |
US20190287881A1 (en) | 2018-03-19 | 2019-09-19 | Stmicroelectronics S.R.L. | Semiconductor package with die stacked on surface mounted devices |
US10361148B1 (en) * | 2018-03-30 | 2019-07-23 | Semiconductor Components Industries, Llc | Leadframe with efficient heat dissipation for semiconductor device package assembly |
CN108364930B (zh) * | 2018-05-04 | 2024-01-26 | 扬州扬杰电子科技股份有限公司 | 一种vdmos功率器件芯片焊接层空洞补偿结构 |
US20200161206A1 (en) * | 2018-11-20 | 2020-05-21 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and semiconductor manufacturing process |
CN109712955B (zh) * | 2018-11-23 | 2021-05-11 | 华为技术有限公司 | 一种基于pcb本体出引脚的封装模块及其制备方法 |
DE102019112778B4 (de) * | 2019-05-15 | 2023-10-19 | Infineon Technologies Ag | Batchherstellung von Packages durch eine in Träger getrennte Schicht nach Anbringung von elektronischen Komponenten |
CN112309873B (zh) * | 2019-07-26 | 2023-11-10 | 江苏长电科技股份有限公司 | 电磁屏蔽封装结构及其封装方法 |
DE102019220215A1 (de) * | 2019-12-19 | 2021-06-24 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung von Halbleiterbauelementen und Halbleiterbauelement |
US11887916B2 (en) * | 2020-09-09 | 2024-01-30 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US11569179B2 (en) * | 2020-11-19 | 2023-01-31 | Advanced Semiconductor Engineering, Inc. | Package structure including an outer lead portion and an inner lead portion and method for manufacturing package structure |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030127711A1 (en) * | 2002-01-09 | 2003-07-10 | Matsushita Electric Industrial Co., Ltd. | Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same |
TW200522320A (en) * | 2003-12-31 | 2005-07-01 | Advanced Semiconductor Eng | Leadless package |
US20070052076A1 (en) * | 2002-04-29 | 2007-03-08 | Ramos Mary J | Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging |
US7262491B2 (en) * | 2005-09-06 | 2007-08-28 | Advanced Interconnect Technologies Limited | Die pad for semiconductor packages and methods of making and using same |
Family Cites Families (167)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4948032A (en) | 1988-11-21 | 1990-08-14 | Atmel Corporation | Fluxing agent |
EP0476664B1 (en) * | 1990-09-20 | 1995-07-05 | Dainippon Screen Mfg. Co., Ltd. | Method of forming small through-holes in thin metal plate |
US5389739A (en) * | 1992-12-15 | 1995-02-14 | Hewlett-Packard Company | Electronic device packaging assembly |
US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
JPH08115989A (ja) * | 1994-08-24 | 1996-05-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
US5646831A (en) * | 1995-12-28 | 1997-07-08 | Vlsi Technology, Inc. | Electrically enhanced power quad flat pack arrangement |
US7166495B2 (en) * | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
US6001671A (en) | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
KR0185512B1 (ko) * | 1996-08-19 | 1999-03-20 | 김광호 | 칼럼리드구조를갖는패키지및그의제조방법 |
ID19548A (id) * | 1996-09-24 | 1998-07-23 | Bavarian Nordic Res Inst As | Virus mva rekombinan yang mengekspresikan antigen-antigen virus demam dan penggunaan daripadanya dalam vaksin-vaksin |
US6097098A (en) * | 1997-02-14 | 2000-08-01 | Micron Technology, Inc. | Die interconnections using intermediate connection elements secured to the die face |
US6201292B1 (en) * | 1997-04-02 | 2001-03-13 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member used therefor |
JP2928190B2 (ja) * | 1997-04-09 | 1999-08-03 | 九州日本電気株式会社 | テーピングリードフレーム |
KR100235308B1 (ko) * | 1997-06-30 | 1999-12-15 | 윤종용 | 2중 굴곡된 타이바와 소형 다이패드를 갖는 반도체 칩 패키지 |
US6395582B1 (en) * | 1997-07-14 | 2002-05-28 | Signetics | Methods for forming ground vias in semiconductor packages |
JP3097653B2 (ja) * | 1998-04-17 | 2000-10-10 | 日本電気株式会社 | 半導体装置用パッケージおよびその製造方法 |
US6949816B2 (en) * | 2003-04-21 | 2005-09-27 | Motorola, Inc. | Semiconductor component having first surface area for electrically coupling to a semiconductor chip and second surface area for electrically coupling to a substrate, and method of manufacturing same |
US6132593A (en) * | 1998-06-08 | 2000-10-17 | Tan; Yong-Jun | Method and apparatus for measuring localized corrosion and other heterogeneous electrochemical processes |
US6933594B2 (en) * | 1998-06-10 | 2005-08-23 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6989294B1 (en) * | 1998-06-10 | 2006-01-24 | Asat, Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6498099B1 (en) * | 1998-06-10 | 2002-12-24 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US6635957B2 (en) | 1998-06-10 | 2003-10-21 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation and die attach pad array |
US7271032B1 (en) | 1998-06-10 | 2007-09-18 | Asat Ltd. | Leadless plastic chip carrier with etch back pad singulation |
US7247526B1 (en) * | 1998-06-10 | 2007-07-24 | Asat Ltd. | Process for fabricating an integrated circuit package |
US6585905B1 (en) * | 1998-06-10 | 2003-07-01 | Asat Ltd. | Leadless plastic chip carrier with partial etch die attach pad |
US7226811B1 (en) | 1998-06-10 | 2007-06-05 | Asat Ltd. | Process for fabricating a leadless plastic chip carrier |
US7049177B1 (en) * | 2004-01-28 | 2006-05-23 | Asat Ltd. | Leadless plastic chip carrier with standoff contacts and die attach pad |
JP3764587B2 (ja) * | 1998-06-30 | 2006-04-12 | 富士通株式会社 | 半導体装置の製造方法 |
JP4030200B2 (ja) * | 1998-09-17 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体パッケージおよびその製造方法 |
US6667541B1 (en) * | 1998-10-21 | 2003-12-23 | Matsushita Electric Industrial Co., Ltd. | Terminal land frame and method for manufacturing the same |
US6303985B1 (en) * | 1998-11-12 | 2001-10-16 | Micron Technology, Inc. | Semiconductor lead frame and package with stiffened mounting paddle |
CN100370612C (zh) | 1998-12-02 | 2008-02-20 | 株式会社日立制作所 | 半导体装置 |
DE19905055A1 (de) * | 1999-02-08 | 2000-08-17 | Siemens Ag | Halbleiterbauelement mit einem Chipträger mit Öffnungen zur Kontaktierung |
SG75154A1 (en) * | 1999-02-23 | 2000-09-19 | Inst Of Microelectronics | Plastic ball grid array package |
JP3780122B2 (ja) | 1999-07-07 | 2006-05-31 | 株式会社三井ハイテック | 半導体装置の製造方法 |
US20020100165A1 (en) * | 2000-02-14 | 2002-08-01 | Amkor Technology, Inc. | Method of forming an integrated circuit device package using a temporary substrate |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
US6451627B1 (en) * | 1999-09-07 | 2002-09-17 | Motorola, Inc. | Semiconductor device and process for manufacturing and packaging a semiconductor device |
TW423133B (en) * | 1999-09-14 | 2001-02-21 | Advanced Semiconductor Eng | Manufacturing method of semiconductor chip package |
US6525406B1 (en) * | 1999-10-15 | 2003-02-25 | Amkor Technology, Inc. | Semiconductor device having increased moisture path and increased solder joint strength |
US6580159B1 (en) * | 1999-11-05 | 2003-06-17 | Amkor Technology, Inc. | Integrated circuit device packages and substrates for making the packages |
JP2001185651A (ja) * | 1999-12-27 | 2001-07-06 | Matsushita Electronics Industry Corp | 半導体装置およびその製造方法 |
US6333252B1 (en) | 2000-01-05 | 2001-12-25 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6342730B1 (en) * | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6261864B1 (en) * | 2000-01-28 | 2001-07-17 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
US6548328B1 (en) * | 2000-01-31 | 2003-04-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
JP3706533B2 (ja) * | 2000-09-20 | 2005-10-12 | 三洋電機株式会社 | 半導体装置および半導体モジュール |
US7173336B2 (en) * | 2000-01-31 | 2007-02-06 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device |
US7091606B2 (en) * | 2000-01-31 | 2006-08-15 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device and semiconductor module |
US6306685B1 (en) | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
US6238952B1 (en) | 2000-02-29 | 2001-05-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
EP1143509A3 (en) * | 2000-03-08 | 2004-04-07 | Sanyo Electric Co., Ltd. | Method of manufacturing the circuit device and circuit device |
US6242284B1 (en) * | 2000-05-05 | 2001-06-05 | Advanced Semiconductor Engineering, Inc. | Method for packaging a semiconductor chip |
JP3883784B2 (ja) | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP2001338947A (ja) * | 2000-05-26 | 2001-12-07 | Nec Corp | フリップチップ型半導体装置及びその製造方法 |
TW506236B (en) * | 2000-06-09 | 2002-10-11 | Sanyo Electric Co | Method for manufacturing an illumination device |
TW507482B (en) * | 2000-06-09 | 2002-10-21 | Sanyo Electric Co | Light emitting device, its manufacturing process, and lighting device using such a light-emitting device |
US6683368B1 (en) | 2000-06-09 | 2004-01-27 | National Semiconductor Corporation | Lead frame design for chip scale package |
JP3650001B2 (ja) | 2000-07-05 | 2005-05-18 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US6429536B1 (en) * | 2000-07-12 | 2002-08-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device |
TW473965B (en) * | 2000-09-04 | 2002-01-21 | Siliconware Precision Industries Co Ltd | Thin type semiconductor device and the manufacturing method thereof |
TW497371B (en) * | 2000-10-05 | 2002-08-01 | Sanyo Electric Co | Semiconductor device and semiconductor module |
US6762118B2 (en) * | 2000-10-10 | 2004-07-13 | Walsin Advanced Electronics Ltd. | Package having array of metal pegs linked by printed circuit lines |
JP4417541B2 (ja) * | 2000-10-23 | 2010-02-17 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3653460B2 (ja) * | 2000-10-26 | 2005-05-25 | 三洋電機株式会社 | 半導体モジュールおよびその製造方法 |
US6689640B1 (en) | 2000-10-26 | 2004-02-10 | National Semiconductor Corporation | Chip scale pin array |
US6906414B2 (en) * | 2000-12-22 | 2005-06-14 | Broadcom Corporation | Ball grid array package with patterned stiffener layer |
JP3895570B2 (ja) | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
US6720207B2 (en) * | 2001-02-14 | 2004-04-13 | Matsushita Electric Industrial Co., Ltd. | Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device |
US6551859B1 (en) * | 2001-02-22 | 2003-04-22 | National Semiconductor Corporation | Chip scale and land grid array semiconductor packages |
US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
US6545347B2 (en) * | 2001-03-06 | 2003-04-08 | Asat, Limited | Enhanced leadless chip carrier |
US6545345B1 (en) * | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
JP3609737B2 (ja) * | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
KR100393448B1 (ko) * | 2001-03-27 | 2003-08-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
JP4034073B2 (ja) * | 2001-05-11 | 2008-01-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP2003017646A (ja) | 2001-06-29 | 2003-01-17 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置およびその製造方法 |
WO2003007373A1 (fr) | 2001-07-09 | 2003-01-23 | Sumitomo Metal Mining Co., Ltd. | Cadre de montage |
TW538658B (en) * | 2001-08-27 | 2003-06-21 | Sanyo Electric Co | Manufacturing method for circuit device |
JP2003124421A (ja) * | 2001-10-15 | 2003-04-25 | Shinko Electric Ind Co Ltd | リードフレーム及びその製造方法並びに該リードフレームを用いた半導体装置の製造方法 |
US7001798B2 (en) | 2001-11-14 | 2006-02-21 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
TW523887B (en) * | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
JP4173346B2 (ja) | 2001-12-14 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US7247938B2 (en) * | 2002-04-11 | 2007-07-24 | Nxp B.V. | Carrier, method of manufacturing a carrier and an electronic device |
US6812552B2 (en) | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6777265B2 (en) | 2002-04-29 | 2004-08-17 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US7790500B2 (en) | 2002-04-29 | 2010-09-07 | Unisem (Mauritius) Holdings Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
JP4095827B2 (ja) * | 2002-05-10 | 2008-06-04 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2004063615A (ja) | 2002-07-26 | 2004-02-26 | Nitto Denko Corp | 半導体装置の製造方法、半導体装置製造用接着シートおよび半導体装置 |
KR20040030283A (ko) * | 2002-09-05 | 2004-04-09 | 신꼬오덴기 고교 가부시키가이샤 | 리드 프레임 및 그 제조 방법 |
US6818973B1 (en) * | 2002-09-09 | 2004-11-16 | Amkor Technology, Inc. | Exposed lead QFP package fabricated through the use of a partial saw process |
US6777788B1 (en) * | 2002-09-10 | 2004-08-17 | National Semiconductor Corporation | Method and structure for applying thick solder layer onto die attach pad |
JP2006511080A (ja) | 2002-12-20 | 2006-03-30 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電子デバイスおよびその製造方法 |
US20040124505A1 (en) | 2002-12-27 | 2004-07-01 | Mahle Richard L. | Semiconductor device package with leadframe-to-plastic lock |
US6927483B1 (en) | 2003-03-07 | 2005-08-09 | Amkor Technology, Inc. | Semiconductor package exhibiting efficient lead placement |
DE10310144A1 (de) | 2003-03-07 | 2004-09-16 | Patent-Treuhand-Gesellschaft für elektrische Glühlampen mbH | Entladungslampe für dielektrisch behinderte Entladungen mit zurückspringend überhändenden Entladungselektrodenabschnitten |
TW200425427A (en) * | 2003-05-02 | 2004-11-16 | Siliconware Precision Industries Co Ltd | Leadframe-based non-leaded semiconductor package and method of fabricating the same |
US6927479B2 (en) * | 2003-06-25 | 2005-08-09 | St Assembly Test Services Ltd | Method of manufacturing a semiconductor package for a die larger than a die pad |
US20040262781A1 (en) * | 2003-06-27 | 2004-12-30 | Semiconductor Components Industries, Llc | Method for forming an encapsulated device and structure |
JP2005026466A (ja) * | 2003-07-02 | 2005-01-27 | Renesas Technology Corp | 半導体装置およびリードフレーム |
TWI233674B (en) | 2003-07-29 | 2005-06-01 | Advanced Semiconductor Eng | Multi-chip semiconductor package and manufacturing method thereof |
US7563648B2 (en) * | 2003-08-14 | 2009-07-21 | Unisem (Mauritius) Holdings Limited | Semiconductor device package and method for manufacturing same |
TWI257693B (en) * | 2003-08-25 | 2006-07-01 | Advanced Semiconductor Eng | Leadless package |
US7060535B1 (en) | 2003-10-29 | 2006-06-13 | Ns Electronics Bangkok (1993) Ltd. | Flat no-lead semiconductor die package including stud terminals |
KR100568225B1 (ko) | 2003-11-06 | 2006-04-07 | 삼성전자주식회사 | 리드 프레임 및 이를 적용한 반도체 패키지 제조방법 |
JP2005191240A (ja) * | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2005191342A (ja) * | 2003-12-26 | 2005-07-14 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7122406B1 (en) * | 2004-01-02 | 2006-10-17 | Gem Services, Inc. | Semiconductor device package diepad having features formed by electroplating |
JP2005203390A (ja) | 2004-01-13 | 2005-07-28 | Seiko Instruments Inc | 樹脂封止型半導体装置の製造方法 |
US7009286B1 (en) * | 2004-01-15 | 2006-03-07 | Asat Ltd. | Thin leadless plastic chip carrier |
US7494557B1 (en) * | 2004-01-30 | 2009-02-24 | Sandia Corporation | Method of using sacrificial materials for fabricating internal cavities in laminated dielectric structures |
US7215009B1 (en) | 2004-02-23 | 2007-05-08 | Altera Corporation | Expansion plane for PQFP/TQFP IR—package design |
US7008820B2 (en) * | 2004-06-10 | 2006-03-07 | St Assembly Test Services Ltd. | Chip scale package with open substrate |
CN2726111Y (zh) | 2004-06-22 | 2005-09-14 | 胜开科技股份有限公司 | 堆叠集成电路封装组件 |
JP2008507123A (ja) | 2004-07-13 | 2008-03-06 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 集積回路を備える電子デバイス |
US7087461B2 (en) | 2004-08-11 | 2006-08-08 | Advanced Semiconductor Engineering, Inc. | Process and lead frame for making leadless semiconductor packages |
TWI256096B (en) * | 2004-10-15 | 2006-06-01 | Advanced Semiconductor Eng | Method for fabricating quad flat non-leaded package |
US7598606B2 (en) | 2005-02-22 | 2009-10-06 | Stats Chippac Ltd. | Integrated circuit package system with die and package combination |
US7846775B1 (en) * | 2005-05-23 | 2010-12-07 | National Semiconductor Corporation | Universal lead frame for micro-array packages |
US7087462B1 (en) * | 2005-06-07 | 2006-08-08 | Advanced Semiconductor Engineering, Inc. | Method for forming leadless semiconductor packages |
US7348663B1 (en) * | 2005-07-15 | 2008-03-25 | Asat Ltd. | Integrated circuit package and method for fabricating same |
TWI287275B (en) * | 2005-07-19 | 2007-09-21 | Siliconware Precision Industries Co Ltd | Semiconductor package without chip carrier and fabrication method thereof |
JP3947750B2 (ja) | 2005-07-25 | 2007-07-25 | 株式会社三井ハイテック | 半導体装置の製造方法及び半導体装置 |
WO2007018237A1 (ja) | 2005-08-10 | 2007-02-15 | Mitsui High-Tec, Inc. | 半導体装置及びその製造方法 |
TWI264091B (en) | 2005-09-15 | 2006-10-11 | Siliconware Precision Industries Co Ltd | Method of manufacturing quad flat non-leaded semiconductor package |
US8536689B2 (en) | 2005-10-03 | 2013-09-17 | Stats Chippac Ltd. | Integrated circuit package system with multi-surface die attach pad |
US8163604B2 (en) | 2005-10-13 | 2012-04-24 | Stats Chippac Ltd. | Integrated circuit package system using etched leadframe |
US7372133B2 (en) * | 2005-12-01 | 2008-05-13 | Intel Corporation | Microelectronic package having a stiffening element and method of making same |
TW200729444A (en) | 2006-01-16 | 2007-08-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
TW200729429A (en) | 2006-01-16 | 2007-08-01 | Siliconware Precision Industries Co Ltd | Semiconductor package structure and fabrication method thereof |
US20090215159A1 (en) * | 2006-01-23 | 2009-08-27 | Quidel Corporation | Device for handling and analysis of a biological sample |
JP2007221045A (ja) | 2006-02-20 | 2007-08-30 | Oki Electric Ind Co Ltd | マルチチップ構造を採用した半導体装置 |
US7301225B2 (en) * | 2006-02-28 | 2007-11-27 | Freescale Semiconductor, Inc. | Multi-row lead frame |
TWI286375B (en) * | 2006-03-24 | 2007-09-01 | Chipmos Technologies Inc | Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same |
US7683461B2 (en) | 2006-07-21 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit leadless package system |
TW200810044A (en) * | 2006-08-04 | 2008-02-16 | Advanced Semiconductor Eng | Non-lead leadframe and package therewith |
US20080029855A1 (en) * | 2006-08-04 | 2008-02-07 | Yi-Ling Chang | Lead Frame and Fabrication Method thereof |
CN100559577C (zh) * | 2006-08-23 | 2009-11-11 | 南茂科技股份有限公司 | 具有阵列接垫的晶片封装构造及其制造方法 |
US9281218B2 (en) * | 2006-08-30 | 2016-03-08 | United Test And Assembly Center Ltd. | Method of producing a semiconductor package |
JP4533875B2 (ja) | 2006-09-12 | 2010-09-01 | 株式会社三井ハイテック | 半導体装置およびこの半導体装置に使用するリードフレーム製品並びにこの半導体装置の製造方法 |
US20080079124A1 (en) * | 2006-10-03 | 2008-04-03 | Chris Edward Haga | Interdigitated leadfingers |
US20080079127A1 (en) | 2006-10-03 | 2008-04-03 | Texas Instruments Incorporated | Pin Array No Lead Package and Assembly Method Thereof |
US7741704B2 (en) * | 2006-10-18 | 2010-06-22 | Texas Instruments Incorporated | Leadframe and mold compound interlock in packaged semiconductor device |
US7608484B2 (en) * | 2006-10-31 | 2009-10-27 | Texas Instruments Incorporated | Non-pull back pad package with an additional solder standoff |
US7608482B1 (en) | 2006-12-21 | 2009-10-27 | National Semiconductor Corporation | Integrated circuit package with molded insulation |
US7605477B2 (en) * | 2007-01-25 | 2009-10-20 | Raytheon Company | Stacked integrated circuit assembly |
KR100950378B1 (ko) * | 2007-01-31 | 2010-03-29 | 야마하 가부시키가이샤 | 반도체 장치와 패키징 구조체 |
TWI337387B (en) * | 2007-04-20 | 2011-02-11 | Chipmos Technologies Inc | Leadframe for leadless package, package structure and manufacturing method using the same |
US7800211B2 (en) * | 2007-06-29 | 2010-09-21 | Stats Chippac, Ltd. | Stackable package by using internal stacking modules |
US7675146B2 (en) * | 2007-09-07 | 2010-03-09 | Infineon Technologies Ag | Semiconductor device with leadframe including a diffusion barrier |
US7838974B2 (en) * | 2007-09-13 | 2010-11-23 | National Semiconductor Corporation | Intergrated circuit packaging with improved die bonding |
US20090127682A1 (en) | 2007-11-16 | 2009-05-21 | Advanced Semiconductor Engineering, Inc. | Chip package structure and method of fabricating the same |
US7808089B2 (en) * | 2007-12-18 | 2010-10-05 | National Semiconductor Corporation | Leadframe having die attach pad with delamination and crack-arresting features |
US20090189261A1 (en) | 2008-01-25 | 2009-07-30 | Lay Yeap Lim | Ultra-Thin Semiconductor Package |
US20090230524A1 (en) | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Semiconductor chip package having ground and power regions and manufacturing methods thereof |
US7834431B2 (en) | 2008-04-08 | 2010-11-16 | Freescale Semiconductor, Inc. | Leadframe for packaged electronic device with enhanced mold locking capability |
TWI368983B (en) | 2008-04-29 | 2012-07-21 | Advanced Semiconductor Eng | Integrated circuit package and manufacturing method thereof |
TW200947654A (en) | 2008-05-12 | 2009-11-16 | Advanced Semiconductor Eng | Stacked type chip package structure and method of fabricating the same |
TWI372458B (en) | 2008-05-12 | 2012-09-11 | Advanced Semiconductor Eng | Stacked type chip package structure |
US7786557B2 (en) | 2008-05-19 | 2010-08-31 | Mediatek Inc. | QFN Semiconductor package |
US20090315159A1 (en) | 2008-06-20 | 2009-12-24 | Donald Charles Abbott | Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same |
US20100044850A1 (en) * | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
CN101442035B (zh) | 2008-12-14 | 2011-03-16 | 天水华天科技股份有限公司 | 一种扁平无引线封装件及其生产方法 |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20110163430A1 (en) * | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
-
2008
- 2008-08-15 US US12/192,742 patent/US20090230524A1/en not_active Abandoned
- 2008-08-15 US US12/192,702 patent/US8492883B2/en active Active
- 2008-08-15 US US12/192,805 patent/US8115285B2/en active Active
- 2008-08-15 US US12/192,761 patent/US8120152B2/en active Active
-
2009
- 2009-03-02 TW TW098106674A patent/TWI419269B/zh active
- 2009-03-03 TW TW098106889A patent/TWI416678B/zh active
- 2009-03-06 TW TW098107362A patent/TWI380416B/zh active
- 2009-03-06 TW TW098107357A patent/TWI459513B/zh active
- 2009-03-13 CN CN2009101274987A patent/CN101540310B/zh active Active
- 2009-03-13 CN CN2009101274968A patent/CN101540305B/zh active Active
- 2009-03-13 CN CN2009101274934A patent/CN101533825B/zh active Active
- 2009-03-13 CN CN2009101274953A patent/CN101540309B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030127711A1 (en) * | 2002-01-09 | 2003-07-10 | Matsushita Electric Industrial Co., Ltd. | Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same |
US20070052076A1 (en) * | 2002-04-29 | 2007-03-08 | Ramos Mary J | Partially Patterned Lead Frames and Methods of Making and Using the Same in Semiconductor Packaging |
TW200522320A (en) * | 2003-12-31 | 2005-07-01 | Advanced Semiconductor Eng | Leadless package |
US7262491B2 (en) * | 2005-09-06 | 2007-08-28 | Advanced Interconnect Technologies Limited | Die pad for semiconductor packages and methods of making and using same |
Also Published As
Publication number | Publication date |
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TWI459513B (zh) | 2014-11-01 |
TW200939418A (en) | 2009-09-16 |
US8115285B2 (en) | 2012-02-14 |
TW200939417A (en) | 2009-09-16 |
CN101540305B (zh) | 2011-03-30 |
CN101540309B (zh) | 2011-06-29 |
US8120152B2 (en) | 2012-02-21 |
CN101540309A (zh) | 2009-09-23 |
US8492883B2 (en) | 2013-07-23 |
TWI380416B (en) | 2012-12-21 |
TWI419269B (zh) | 2013-12-11 |
CN101540310B (zh) | 2011-01-05 |
CN101540310A (zh) | 2009-09-23 |
CN101533825A (zh) | 2009-09-16 |
TW200939427A (en) | 2009-09-16 |
US20090230525A1 (en) | 2009-09-17 |
CN101540305A (zh) | 2009-09-23 |
CN101533825B (zh) | 2011-01-05 |
TW200939416A (en) | 2009-09-16 |
US20090230526A1 (en) | 2009-09-17 |
US20090230524A1 (en) | 2009-09-17 |
US20090230523A1 (en) | 2009-09-17 |
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