TW569411B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- TW569411B TW569411B TW091123964A TW91123964A TW569411B TW 569411 B TW569411 B TW 569411B TW 091123964 A TW091123964 A TW 091123964A TW 91123964 A TW91123964 A TW 91123964A TW 569411 B TW569411 B TW 569411B
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Description
569411 玖、發明說明 (#明說明應救明^發明所1之技術領域、先前技術、內容、實施方式及_式簡單說明) ,.:、*.: : i:: -一 : v s : : ; ,Γ· ' {i:i : . . ,ΐν '' · > ' - - - .- · · - " : · -.· -ί·- :/ - f-r- · ·· · ν,,, L發明戶斤屬之技術領域3 發明領域 本發明概括有關於半導體元件,且更特定言之,有關 於一種具有一堆疊複數個半導體元件及半導體部件的立體 5 結構之半導體元件、以及此半導體元件之製造方法。 隨著近年來電子設備的發展,益加需要半導體元件的 尺寸與厚度微小化、多功能性、尚效能、南密度。為了應 付此需求,半導體元件的結構已轉移至一種堆疊複數個半 導體元件或複數個半導體部件之立體結構。 10 【先前技術】 發明背景 曰本專利申請公開2001-223297號揭露一種半導體元件 的範例,其中具有一由複數個半導體元件堆疊而成的立體 結構,第1圖為上述專利文件所揭露的半導體元件之剖視圖。 15 第1圖中,半導體晶片3分別安裝在各中介層1的兩側且 受到一密封樹脂2所包封。兩中介層1藉由其間用於包封半 導體晶片3的密封樹脂2進行堆疊,藉由將錫球7結合至在一 阻焊劑4中形成的通孔6所露出之球墊5而使中介層1彼此連 接,亦即,上及下中介層1藉由錫球7彼此電性連接且亦彼 20 此機械性連接。 第1圖所示的半導體元件中,因為安裝在堆疊式中介層 上之各半導體晶片受到密封樹脂所包封,需要在兩中介層 之間提供一距離,此距離係大於兩中介層之間的密封樹脂 層的厚度。因此,若可降低中介層之間的距離,則亦可降 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 6 569411 發明說明$賣 玖、發明說明 · 低半導體元件的整體高度。 此外,因為中介層係藉由設置於令介層周邊部份的錫 球而彼此連接且㈣,若在半導體封裝件組餘序的—堆 叠程序中於中介層發生彎曲,則中介層之間的連接部份可 能=生瑕痴。並且,當完成的半導體封裝件安裝在—基材 上時,由於十介層的熱變形及錫球的再融化,在中介層之 間的連接部份可能發生瑕疵。 並且’因4完成的半導體封裝件只與錫球具有小面積 1的機械性連接’應力傾向於集中在中介層之間的連接部份 0内,而可能破壞封裝件的機械可靠度。 【潑^明内容】 發明概要 本發明之-概括目的係提供一種可消除上述問題之改 良且有效的半導體元件。 1本發明之—較特定目的係提供-種具有-立體結構之 半V體7G件,此Jt體結構t係堆疊複數財導體元件或複 數個半導體部件,半導體元件具有降低的整體高度及改良 之堆疊結構機械強度的可靠度。 本發明之另一目的係提供一種具有一立體結構之半導 體兀件’此立體結構中係堆疊複數個半導體元件或複數個 半導體部件,半導體元件具有改良的熱釋放特徵。 為了達成上述目的,根據本發明的一型態提供一種包 含下列各物之半導體元件:-第—半導體元件,其具有一電 路形成表面及一與電路形成表面相對之背表面;一第一中 0續次頁(發_明頁不敷使用時,請註記並使用顧) 569411 玖、發明說明 ·: 、· ' =二具有—可供形成第一獅及安裝第"1^ 一一、^ 且其中使電路形成表面面對第一中介層;一第 面’其具有―電路形成表面及一與電路形成表 • 3表面第二令介層,其具有一可供形成第二 电極墊及文裝第二半導體部件之表面,且其中使電路形 表面面對第二中介声, 乂 曰弟一電極墊用於連接第一中介層; =外部連接端子,其設置於與可供安裝第二半導體部二 、面相對之第二中介層的_表面上,其中藉由第—及第二 ίο 15 之間的傳導性構件使第一中介層及第二中介層彼此 、北、接」且第—半導體部件的背表面及第二半導體部件 的月表面藉由一黏劑彼此固定。 根據上述發明,不需要包封位於第一及第二中介層之 間的第-及第二半導體部件。因此可減小第一及第二中介 層之間的距離,使得半導體元件的整體厚度降低。此外, 因=第-及第二半導體部件藉由黏劑彼此接合,故改善了 « 中:層之間連接部的機械強度以免中介層產生彎曲。並且 ★ 口為第一及第二半導體部件藉由黏劑彼此接合,可經由 第二半導體部件及第二中介層將第一半導體部件中產生的 熱量釋出外部。 20 ^根據本發明的半導體元件可進一步包含至少一第三半 =體件’此第二半導體部件係、安褒在與可供安裝第一半 ㈣部件的表面相對之第一中介層的一表面上。因此,堆 叠在半導體元件中之半導體部件數量可能增加,藉以改良 封裳密度。此外,複數個第三半導體部件可以一堆疊及固 0續次頁(翻麵财_觸,_鍵_顧) 569411 、發明說明: ‘ • ' 定㈣«及包封在第—中介層的表面= 型或尺寸的半導體部件可有效率地配置於半導體元件内。 亚且,-用於釋放熱量的金屬層係可設置於與可供安裝第 -半導體部件的表面相對之第 ,、 T;|;f的一表面上。因此 ,金屬層作為熱分散器’可藉以將半導體部件的熱量有效 率地釋放至半導體元件外。 此外,根據本發明另一型態提供一種包含下列各物之 半導體第—半導體部件,其具有—電路形成表面及 10 -與電路形成表面相對之背表m介層,其具有 -可供形成第一電極墊及安裝第一半導體部件之表面,且 其中使電路形成表面面對第—中介層;_第二半導體部件 其具有-電路形成表面及—與電路形成表面相對之背表 面’第—中介層’其具有—可供形成第二電極墊及安裝 15 第二半導體部件之表面,且其中使電路形成表面面對第二 中介層’第二電極墊用於連接第一令介層;及外部連接端 子其。又置於與可供安裝第二半導體部件的表面相對之第 二中介層的—表面上,其中藉由第—及第二電極塾之間的 傳導性構件使第一中介層及第二中介層彼此電性連接,且 第中介層及第二半導體部件的背表面藉由一黏劑彼此固 20 定。 根據上述發明,不需要包封位於第一及第二中介層之 間的第二半導體部件。因此,可降低第一及第二尹介層之 門的距離’使得半導體元件的整體厚度降低。此外,因為 第-半導體部件及第—中介層藉由黏劑彼此接合,故改善 _次頁(發明說赌不敷使觸,證記並使用顯) 569411 玫、聲明說明 .·〜人... >· · '. ·.'·'·· ·'· >: .··>.' ' ^ :. - _.「:··. · · · r介層之間連接部的機械強度以免中介層^7^77 因為第一半導體部件藉由黏劑接合至第一中介層,可 經由第一中介層、第二半導體部件及第二中介層將第一半 導體部件中產生的熱量釋出外部。 5 10 、曾根據本發明的半導體元件可進一步包含至少一第三半 ―體。P件,此第三半導體部件係安裝在可供安裝第一半導 I部件之第-中介層的表面上。因此,堆疊在半導體元件 、,半導體4件數量可能增加,.藉以改良封I密度。此外 ’半導體元件可進一步包含堆疊在第-半導體部件上之至 少一第三半導體部件,且第一及第三半導體部件可包封在 第一中介層上。 此外’根據本發明的半導體it件中,可將至少一第四 半導體部件安裝在設有外部連接端子之第二中介層的表面 上,複數個第四半導體部件可設置及包封在第二中介層上。 i5 ϋ且’各外部連接端子可能為平坦墊或可能為突起形 狀’各外部連接端子可能係為從第二中介層往外方向延伸 之導線端子。 此外,用於將第一半導體部件的背表面及第二半導體 部件的背表面彼此接合之黏劑可能係為_種熱固型樹脂: 劑’此熱固型樹脂黏劑可能包含銀及銅的其中至少一者。 並且,根據本發明的半導體元件令,可提供一強化黏 劑來連接傳導性材料及第—及第二中介層之間的部份,強 化黏劑可能由一絕緣熱固型樹脂材料製成,強化黏劑可能 為一膜狀並此膜具有對應於傳導性構件位置之開口。 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 569411 發明說明 、,發明說明 10 因此’根據本發明另一型態提供—種包含一第一半導 體部件及一第二半導體部件之半導體元件的製造方法,此 方法包含以下步驟:以使第-半導體部件的—電路形成表面 面對第-令介層的-狀態將第—半導體部件安裝在一第— 中介層上’·以使第二半導體部件的一電路形成表面面對第 二中介層的一狀態將第二半導體部件安裝在一第二中介層 上;藉由堆疊第一及第二中介層使第一令介層及第二中: 層,此電性連接,且在其間設有第二半導體部件以及設置 於第-及第二’介層之間的熱傳導性構件,藉以融化傳導 性構件;及藉由電性連接步驟中的熱量來固化一熱固性黏 劑’此熱固性黏劑係位於第二半導體元件的一背表面與第 -半導體部件的-背表面及第—中介層的其中—者之間。 可由下列詳細描述參照圖式得知本發明之其他目的、 特性及優點。 15 圖式簡單說明 第1圖為一習知半導體元件之剖視圖; 第2圖為根據本發明第_實施例之一半導體元件的剖視 圖; 第3圖為根據本發明第二實施例之—半導體元件的剖視 20 圖; 第4圖為根據本發明第三實施例之一半導體元件的剖視 圖; 第5圖為根據本發明第四實施例之一半導體元件的剖视 0續次頁(翻說頓不敷使鹏,請註記並使用續頁) 11 569411 玖、發明說明 圖;
圖; 第6圖為根據本發明第五實施例之一半導體元件的 第7圖為根據本發明第六實施例之一半導體元件的剖视 剖视 5 第8圖為根據本發明第七實施例之一半導體元件的 圖; 圖; 第9圖為根據本發明第八實施例之一半導體元件的剖 視 第丨〇圖為根據本發明第九實施例之一半導體元件的剖 10 視圖; 第11圖為根據本發明第十實施例之一半導體元件的剖 視圖; 的 第12圖為根據本發明第十一實施例之一半導體元件 剖視圖, 15 第13A及13B圖顯示第11圖所示之一黏劑的構造; 第14圖為根據本發明第十一實施例之一半導體元件的 剖視圖; 第15圖顯示身為第14圖所示之半導體元件的變化方式 之一半導體基材的剖視圖; 20 第16圖為根據本發明第十二實施例之一半導體元件的 剖視圖。 C實施方式2 較佳實施例之詳細說明 現在參照第2圖描述根據本發明第一實施例之一半導體 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 12 砍、發明說明.發明說明續頁 元件,第2圖為根據本發明第一實施例之一半導體元件的剖 視圖。 第2圖所示的半導體元件係具有一種將一可供安裝一半 導體晶片3a的中介層la及一可供安裝一半導體晶片%的中 介層lb加以堆疊之構造,中介層1&及中介層“係為重新配 置式基材(rearranging substrate)並由一聚醯亞胺帶基材、一 玻璃環氧樹脂基材、一有機性基材(聚碳酸酯)等形成。中介 層la及中介層lb藉由身為傳導性構件的錫球7彼此電性連接。 半導體晶片3a藉由覆晶接合安裝在中介層“上,這一 般稱為面向下式安裝。亦即,半導體晶片3a經由位於半導 體晶片3的電路形成表面上之凸塊8電性連接至中介層“底 側所形成之電極墊,凸塊8由金、銅、焊錫、聚合物等形成 ,半V體晶片3a及中介層la係由其間的一充填不足的黏劑9 接合藉以彼此固定。採用一諸如環氧樹脂、丙烯酸或聚醯 亞胺等樹脂材料作為充填不足的黏劑9。 同樣地,半導體晶片3b藉由面向下式安裝(覆晶接合)安 裝在中介層lb上,亦即,半導體晶片3b經由半導體晶片儿 之電路形成表面上的凸塊8電性連接至中介層lb頂表面上形 成之電極墊。半導體晶片3b及中介層11}係由其間的充填不 足的黏劑9加以接合並彼此固定。 中介層la及中介層lb堆疊而具有介於其間之半導體晶 片3a及3b,因此,半導體晶片3a及儿的背表面(與電路形成 表面相對之一表面)係處於一種彼此面對的狀態。本實施例 中,彼此面對之半,導體晶片3a及3b的背表面係由一黏劑12 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 569411 玖、發明說明:. ..發明說明續頁 接合’使得半導體晶片3aA3b彼此機械性固定。對於黏劑 12使用一諸如環氧樹脂、丙烯酸或聚醯亞胺等樹脂材料, 且樹脂材料較佳為熱固型。此外,為了改善所接合之半導 體晶片的電性質,上述樹脂可能包含銀或銅。 錫球7 Α σ又置作為下中介層1 &底表面上的外部連接端子 ,且設有錫球7A的部份以外之部份係受到一阻焊劑4所覆蓋。 用於電性連接中介層la及中介層lb之錫球7係結合至中 介層la底表面上所形成之球墊元以及中介層化頂表面上所 形成之球墊5b。因此,錫球7的高度幾乎等於半導體晶片% 10及半^體晶片3b向度的總和。球墊5a及球墊5b形成為在阻 焊劑4中形成的開口中露出之部份。 此處,因為半導體晶片3a的電路形成表面係面對中介 層h且其間充填有充填不足的黏劑9,不需藉由密封樹脂來 包封半導體晶片3a。同樣地,因為半導體晶片儿的電路形 15成表面係面對中介層化且其間充填有充填不足的黏劑9,不 需藉由密封樹脂來包封半導體晶片3b。 因此,不需要維持中介層la與中介層lb之間的密封樹 脂部份所需要之高度(距離),只需要對應於半導體晶片“及 3b高度總和以及黏劑12厚度之一距離。因此,根據本實施 20例之半導體元件的厚度可小於第1圖所示的習知半導體元件 之厚度。 此外,除了錫球7的連接之外藉由黏劑12將半導體晶片 3a及半導體晶片3b接合,以使中介層la及中介層lb機械性 穩固地接合。因此,可防止熱應力及外力集中於錫球7的連 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 14 )69411 玖、發明說明 (\ … 發明說明續頁 ''' ' 〜…: - ' 接部份内,藉以改善中介層之間的機械連接之可靠度。 亚且,藉由將黏劑接合12製成一種快速固化型熱固性 樹脂,可在-項用於使錫球7結合至中介層回流程 序期間藉由加熱將㈣_化。因為_〗2在錫球7融化及 再度固體化之前即已固化,當錫球7固化時,中介層“及中 介層lb彼此固定’所以錫球的連接位置無法移位。因此可 達成精確的定位,且可防止在回流程序中於錫球中產生殘 留應力。 ίο 15 並且’本實施例中,因為半導體晶片3a藉由—黏劑12 薄層接合至半導體晶片扑’在半導體晶“内產生的熱量 亦經由黏劑結合12及半導體晶片3b傳遞至下中介料。中 介層lb的熱量係經由錫球7八有效率地發散出外部,因此, 根據本實施例,因為用於從安裝在上中介層^上的半導體 晶片將熱量傳遞至下中介層11?之路徑數量增加,來自半導 體晶片的熱量可經由中介層lb有效率地釋出外部。 應注意,雖然半導體晶片3a·藉由覆晶接合安裝在 各別的中介層Mlb上,其亦可能採用tab(卷帶自動接合 技術)作為一種進行面向下式安裝的方法。並且,雖麸中介 20 層1❹藉由錫球7電性連接,接合材料及方法並不限於所 揭露者。譬如,若不接, 右不知用錫球7,則可藉由使其表面受到一 諸如Ni/Au及類似物等導電材料所覆蓋之銅柱電極或樹脂球 產生連接。 接下來’參照第3圖描述根據本發明第二實施例之—半 導體元件’第3圖為根據本發明第二實施例之半導體元件的 0續次頁(翻說頓不驗_,麵使用續頁) 15 569411 發明說明續頁 同之元件係具有相同 玖、:發明說明, ..... ,1·:' . 剖視圖,第3圖中與第2圖所示元件相 的編號而不再贅述。 根據本發明第二實施例之半導體元件係以一種堆属狀 態將複數個半導體晶m、3e安裝在第2圖所示^介 層的頂表面而構成。 10 半導體晶片3c經由凸塊8電性連接至中介層_頂表面 ’半導體晶片3e及中介層13係由充填不足的黏劑9所接合。 t半導體晶片3d以-種堆疊狀態安裝在半導體晶片㈣ 背表面、並藉由黏晶黏劑10接合至半導體晶片&。黏晶黏 劑10可抓用-諸如環氧樹脂、丙稀酸或聚酿亞胺等樹脂材 料,半導體晶片3d以電路形成表面幸月±安裝在半導體晶片 3c上、並藉^Au線電性連接至中介層u頂表面所形成之電 極塾。 半導體晶片3 e小於半導體晶片3 d並以一堆疊狀態配置 15於不形成電極墊處之半導體晶片%的電路形成表面中心部 份。半導體晶片3e以電路形成表面朝上堆疊在半導體晶片 3d上並以Au線電性連接至在中介仏的頂表面所形成之電 極墊。 上述結構中,半導體晶片3c、^受到中介層^頂 20表面上的密封樹脂2所包封,密封樹脂2可採用諸如環氧樹 脂、丙烯酸或聚醯亞胺等材料。 根據本實施例的半導體元件可提供與根據上述第一實 施例的半導體元件相同之效果。此外,亦經由半導體晶片 3a及接合至半導體晶片3a的半導體晶片几將來自堆疊在中 0綸次頁(翻翻頁不雖鱗,驗記雌騰頁) 569411 玖、發明說明 . : 介層u頂表面的半導體晶片3c、3d、3e之熱 ’|層lb目此’來自堆疊在中介層以頂表面的半導體晶片 3c、3d、3e之熱量亦可經由下中介層化有效率地發散出外 部。 5 應、注意’雖然三個半導體晶片堆疊在中介層la並由一 讀樹脂所包封,本發明並不限於此半導體晶片數量及安 裝方法,亦可由不同安裝方法安裝不同數量的半導體晶片。 接下來,參照第4圖描述根據本發明第三實施例之一半 導體元件,第4圖為根據本發明第三實施例之半導體元件的 1〇剖視圖,第4圖中與第2圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明第三實施例之半導體元件係具有一種使半 導體晶片3〇安褒在第2圖所示之半導體元件的中介層la頂表 面上之結構,半導體晶片允經由凸塊8電性連接至中介層u 15頂表面’半導體晶片3c及中介層丨&係由充填不足的黏劑9所 接合。 因為堆疊在中介層la上的半導體晶片氕係安装為使電 路形成表面朝下,且充填不足的黏劑9充填在電路形成表面 與中介層la之間,所以不需以密封樹脂來包封半導體晶片 20 3c 〇 如上述,半導體晶片3b經由凸塊8電性連接至中介層^ 的頂表面。並且,中介層la&lb經由錫球7電性連接,作為 外部連接端子的錫球7A係設置於中介層比的底表面。因此 ,半導體晶片3b及3c經由錫球7電性連接至中介層lb、並可 叼續次頁(發明說明頁不敷使用時,請註記並使用續頁) 17 569411 發明說明續頁 外部電路。 玖、發明說明 .......'…· ·· …… ' 經由作為外部連接端子的錫球7A電性連接至一 根據本發明的半導體元件係可提供與根據上述第一實 施例的半導體元件相同之效果,並且,經由安裝在中介層 la底表面的半導體晶片3a及接合至半導體晶片3&的半導體 5晶片3b將來自堆疊在中介層la的半導體晶片3c之熱量傳遞 至下中介層lb。因此,來自安裝在中介層ia頂表面上的半 導體晶片3c之熱量可經由下中介層lb有效率地釋出外部。 接下來,參照第5圖描述根據本發明第四實施例之一半 導體元件,第5圖為根據本發明第四實施例之半導體元件的 1〇剖視圖,第5圖中與第2圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明第四實施例之半導體元件係具有一種使一 熱分散器13設置在第2圖所示之半導體元件的中介層la頂表 面上之結構,散熱用的熱分散器13形成為由一種包含Cu、 CuW W、Al、A1C、Ag等材料構成之一金屬層並且為一片 狀或箔狀構件以施加至中介層la的頂表面上。當製造熱分 散13時,可利用一諸如銅箔等配線材料將熱分散器13形 成於中介層的頂表面上。 本實施例中,來自半導體晶片3a的熱量係傳遞至半導 2〇體晶片3b且亦經由中介層“傳遞至熱分散器⑴,因此,來 自半導體曰曰曰片3a的熱量可經由熱分散器財效率地釋出外 部。此外,當半導體晶片儿中產生大的熱量時,來自半導 體晶片3b的熱量係傳遞至半導體晶片“及中介層h,因此 熱量經由熱分散器13有效率地發散出外部。 0續次頁(發明說頓不敷使鱗,請註記並使騰頁) 18 玖、發明說明: 發明說明,續頁 應注意,熱分散器之構造、形成方法及配置方法並不 限於特定構造及方法,可依需要採用適當的構造及方法。 接下來’參照第6圖描述根據本發明第五實施例之一半 ' _ _件第6圖為根據本發明第五實施例之半導體元件的 視圖,第6圖中與第3圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明第五實施例之半導體元件係具有一種與根 據第3圖所不的第二實施例之半導體元件相同的基本結構, 亚進一步设有一半導體晶片灯。半導體晶片3f經由凸塊8電 性連接至中介層1b底表面,半導體晶片3f及中介層11}係由 充填不足的黏劑9所接合。 本實施例中,作為外部連接端子的錫球7A係配置於中 介層lb的圓周部份,且半導體晶片3f藉由覆晶接合安裝在 中介層ib底表面的中心部份。因此,錫球7A形成為比半導 體晶片3f高度更大之高度,根據本實施例,堆疊的半導體 晶片數可增加,故可改善半導體晶片的封裝密度。 接下來,參照第7圖描述根據本發明第六實施例之一半 導體元件,第7圖為根據本發明第六實施例之半導體元件的 視圖帛7圖中與第6圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明帛六實施例之半導體元件係具有與根據第6 圖所不的第五實施例之半導體元件相同之基本結構,且進 一步設有一半導體晶片3g。半導體晶片3g經由Al^^U電性 連接至令介層ib的底表面,半導體晶片3g藉由黏晶黏劑1〇 0續次頁(翻麵頁不離觸,識記搬用續頁) 569411 玖、'發明說明, . ·發明說_續頁 接合至半導體晶片3f的背表面。或者,因為半導體晶片3g 由Au線加以連接,半導體晶片打及3§係由中介層讣底表面 的密封樹脂2加以一體包封。 本實施例中,作為外部連接端子的錫球7A係配置於中 5介層lb的圓周部份,且半導體晶片取城由覆晶接合堆
疊及安裝在中介層lb底表面的中心部份上。因此,錫球7A 形成為比密封樹脂2的高度更大之高度。根據此實施例,堆 豐半導體晶片數可增加,並可改善半導體晶片的封裝密度。 接下來,參照第8圖描述根據本發明第七實施例之一半 1〇 ‘體疋件,第8圖為根據本發明第七實施例之半導體元件的 剖視圖,第8圖中與第3圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明第七實施例之半導體元件係具有一種與根 據第3圖所示的第二實施例之半導體元件相同之基本結構, 15亦即’雖然根據第3圖所示的第二實施例之半導體元件係為 將錫球7A設置於中介層底表面之球栅陣列(bga)型半導體 凡件’此實施例中並未提供錫球,且電極墊14在中介層化 底表面露出使電極墊作為外部連接端子。 接下來,參照第9圖描述根據本發明第八實施例之一半 導體元件,第9圖為根據本發明第八實施例之半導體元件的 剖視圖,第9圖中與第6圖所示元件相同之元件係具有相同 的編號而不再贅述。 根據本發明第八實施例之半導體元件係具有一種與根 據第6圖所示的第五實施例之半導體元件相同之基本結❹ 續次頁(發明說明頁不敷使用時,請註記並使用續頁) 20 、 玖、發明說明、 發明說明I賣頁 ^ , · - ' ' · 且構成為導線-端子型半導體元件,亦即,雖然根據第6圖 所不的第五實施例之半導體元件係為將錫球7 A設置於中介 層底表面之BGA(球栅陣列)型半導體元件,根據此實施例的 半導體元件並未設有錫球7A,取而代之將導線15設置於中 介層lb底表面以作為外部連接端子。 接下來,參照第10圖描述根據本發明第九實施例之一 半導體元件,第10圖為根據本發明第九實施例之半導體元 件的剖視圖,第H)圖中與第3圖所示元件相同之元件係具有 相同的編號而不再贅述。 根據本發明第九實施例之半導體元件係具有一種與根 據第3圖所示的第二實施例之半導體元件相同之基本結構並 進一步設有中介層1〇及1(1。藉由與具有位於中介層“及化 之間的半導體晶片3&及3b的結構相同之配置將半導體晶片 及錫球設置於t介層lb及1c之間以及中介層“及“之間, 作為外部連接端子的錫球7A係設置於最下方的中介層W底 表面。 根據本實施例,堆疊的半導體晶片數可增加,且可改 善半導體晶片的封裝密度。堆疊的中介層數及半導體晶片 數並不限於所顯示的數量,可藉由增加堆疊的中介層數來 增加半導體晶片數。 接下來,參照第11圖描述根據本發明第十實施例之一 半導體元件,第11圖為根據本發明第十實施例之半導體元 件的剖視圖,第11圖中與第3圖所示元件相同之元件係具有 相同的編號而不再贅述。 E續次頁(翻麵則观細肖, 569411 玖、發明說明 , 。、翻說明續頁 , ,、、 ........ 根據本發明第十實施例之半導體元件係具有一種與根 據第3圖所示的第二實施例之半導體元件相同之基本結構, 且錫球7的連接部份由一黏劑16加以強化。亦即,在藉由錫 球7將中介層以錢相互連接之後,將黏_施加在锡球7 5周圍並固化,黏劑16可採用一諸如環氧樹脂、丙烯酸或聚 酸亞胺等絕緣樹脂材料,且較佳使用一熱固型樹脂。 根據本實施例,因為錫球7的連接部份受到黏劑16所強 化,故改善了連接部份的可靠度。此外,因為錫球7受到黏 劑16覆蓋及保護’即使譬如可導電的異物或類似物進入中 10 "層之間仍可防止相鄰錫球之間發生電性短路。 第12圖為一身為第u圖所示半導體元件的變化之半導 體元件的剖視圖,在第12圖所示的半導體元件中,將一片 狀或膜狀的黏劑16A施加至錫球7的連接部份上而非施加液 體型式的黏劑16,且黏劑16 A藉由熱量加以固化。 15 第13A及13B圖顯示一片或膜狀的黏劑16A構造的範例 ,如第13A圖所示,黏劑16A可能由與錫球7列對應的一條 狀黏劑膜所構成,且利用壓模進行沖壓使開口 16Aa先行形 成於與錫球對應之位置。當錫球7配置於圓周時,如第13B 圖所示,黏劑膜16A可構成一框架的形狀,且開口丨6八&形 20成於與錫球7對應之位置,可在錫球7受到回流之前放置黏 劑16A,以使黏劑16A融化並受到回流的熱量所固化。 接下來,參照第14圖描述根據本發明第十一實施例之 一半導體元件,第14圖為根據本發明第十一實施例之半導 體元件的剖視圖’第14圖中與第2圖所示元件相同之元件係 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 569411
玖、發明說明 具有相同的編號而不再贅述。 根據本發明第十—實施例之半導體元件與根據第2圖的 第-實施例的半導體元件之差異係為:只有半導體晶片儿設
置於中介層lamb之間,且半導體晶片^安裝在上中介層 5 la的頂表面上。 S 10 此處’半導體晶片3b係由覆晶連接安裝在下中介層^ 上,且半導體晶片3e藉由覆晶連接安裝在上中介層13的頂 表面上。因此’半導體晶片3b的背表面係面對上中介層u 的底表面且半‘體晶片3b的背表面係由黏劑U接合至上 中介層la的底表面。錫球7延伸經過上中介層u中所形成的 通孔内侧、並連接至上中介層la之頂表面的球墊&及下中 介層1 b之頂表面所形成的球塾5b。 本貝施例中,不需保持中介層以及1}^之間的一樹脂密 封部份所需要之-高度(距離),只需要維持身為半導體晶片 15 3b同度及黏劑12厚度的總和之一距離。因在匕,可降低根據 本實施例之半導體晶片的厚度。 此外’本實施例中,類似於根據第2圖所示的上述半導 體元件的情形,因為半導體晶片3b的背表面藉由黏劑12直 接固疋至上中介層1c,可防止熱應力及外力集中在錫球7的 2〇連接部份内,藉以改善中介層之間的機械連接可靠度。 並且’在藉由回流將錫球7結合至中介層1&及lb之程序 中,可將黏劑12製成快速固化熱固性樹脂藉以在回流時利 用加熱使黏劑12固化。因為黏劑12在錫球7融化及再度固體 化之前已經固化,當錫球固體化時,中介層la&lb彼此固 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 23 569411 玖、發明說明 .· 疋’因此錫球7連接位置不會移位。藉此達成精確定位且可 防止在回流時於錫球7中發生殘留應力。 並且,本實施例中,因為中介層la藉由薄層的黏劑12 接合至半導體晶片3b,半導體晶片3c内產生的熱量亦經由 5中介層la、黏劑接合12及半導體晶片3b傳遞至下中介層lb 。中介層lb中的熱量經由錫球7A有效率地釋出外部。因此 ,因為根據本實施例將熱量從安裝在上中介層1&上的半導 體晶片傳遞至下中介層lb之路徑數量係增加,故來自半導 體晶片的熱量可經由中介層lb有效率地釋出外部。 10 此外,雖然半導體晶片3b及3c分別藉由覆晶連接安裝 在中介層la及lb上,亦可採用TAB(卷帶自動接合技術)作為 一種面向下安裝方法。並且,雖然中介層“及化以錫球7彼 此電性連接,其連接方式並不限於所揭露的方法,譬如若 不採用錫球7,則可利用譬如一具有由諸如沁或八以膜等傳導 15性材料所覆蓋的一表面之鋼柱電極或樹脂球等材料來連接 中介層la及lb。 應注意在本實施例中雖將一個半導體晶片孔安裝在上 中介層la上,如第15圖所示,亦可將複數個半導體晶片孔 安裝在上中介層la上。 2〇 接下來,參照第16圖描述根據本發明第十二實施例之 半V體元件,第1 6圖為根據本發明第十二實施例之半導 體元件的剖視圖,第16圖中與第14圖所示元件相同之元件 係具有相同的編號而不再贅述。 根據本發明第十二實施例之半導體元件係藉由堆疊複 嗎次頁(獅_頁不驗觸,證記雖用顧) 24 569411 玖,、發明說明 ::‘ 〈發明說明續 · '· .. :;,: >::>. .. .: · . : :.. ;:. ·. .. *-: . ......... 數個半導體晶片3c、3d、3e於第14圖所示半導體晶片的中 介層la.頂表面上而形成。 半導體晶片3c經由凸塊8電性連接至中介層^的頂表面 ,半導體晶片3c及中介層la係由充填不足的黏劑9所接合。 5 半導體晶片3d安裝在半導體晶片3c的背表面上、並由 黏晶黏劑10接合至半導體晶片3c,黏晶黏劑1〇可採用一諸 如環氧樹脂、丙烯酸或聚醯亞胺等樹脂材料,半導體晶片 刊以電路形成表面朝上安裝在半導體晶片3c上並以八^線。 電性連接至中介層la頂表面上所形成之電極墊。 1〇 半導體晶片化係小於半導體晶片3d並配置及堆疊於未 設有電極墊之半導體晶片3d的中心部份,半導體晶片乂以 電路形成表面朝上堆疊及安裝在半導體晶片3e上並由八口線 11電性連接至中介層la頂表面上所形成之電極墊。 上述結構中,半導體晶片3c、3d、3e由中介層以底表 15面的密封樹脂加以包封,密封樹脂2可採用諸如環氧樹脂、 丙埽酸或聚醯亞胺等材料。 〃根據本實施例之半導體元件可提供與根據本發明上述 第十一貫施例的半導體元件相同之效果,並且,來自堆疊 在中介層la頂表面的半導體晶片3c、>之熱量係經 20接合至中介層la頂表面的半導體晶片%傳遞至下中介層化 口此,來自堆豐及安裝在中介層i a頂表面的半導體晶片 3c、3d、3e之熱量亦可經由下中介層lb有效率地釋出外部。 應注意,雖然將三個半導體晶片堆疊及包封在中介層 la頂表面上,本發明並不限於所描述的半導體晶片數量及 0續次頁(發明說明頁不敷使觸’請註記並使騰頁) 569411 V Λ ·ν... ν.·:Λ ............ _ - - Γ#明說明續頁 ' ' - ' - 亦可藉由不同安裝方法來堆疊及安 坎 '發明說明 半導體晶片安裝方法, 裝不同數量的半導體晶片。 、隸本發明的實施例已描述於上文中,本發明不限於 上述實施例所揭露的特性,可將上述實施例的組合視為位 5 =本發明範圍内。譬如,可藉由將黏劑_i6A施加至具有 #圖斤示、、、α構之錫球7的連接部份來強化錫球7的連接部 伤。此外,採用第16圖所示的結構作為一種基本結構,並 可添加第6至1〇圖所示的特性。 本發明不限於特定揭露的實施例,亦可作出變化及修 10改而不脫離本發明之範圍。 本申請案係基於2〇〇2年4月D日的日本優先申請MOL 117534唬,該案以引用方式併入本文中。 【圖式簡單說明】 第1圖為一習知半導體元件之剖視圖; 15 第2圖為根據本發明第一實施例之一半導體元件的剖視 圖; 第3圖為根據本發明第二實施例之一半導體元件的剖視 圖; 第4圖為根據本發明第三實施例之一半導體元件的剖視 20 圖; 第5圖為根據本發明第四實施例之一半導體元件的剖視 圖; 第6圖為根據本發明第五實施例之一半導體元件的剖才 圖; °現 0續认頁(發明說明頁不敷使用時,請註記並使用續頁) 26 569411
回第7圖為根據本發明第六實施例之一半導體元 玖、發明說明 第8圖為根據本發明第七實施例之一半導體元件的剖 圖; 〇子 5 第9圖為根據本發明第八實施例之一半導體元件的剖視 圖, 第10圖為根據本發明第九實施例之一半導體元件的剖 視圖, 第π圖為根據本發明第十實施例之一半導體元件的剖 10 視圖; 第12圖為根據本發明第十一實施例之一半導體元件的 剖視圖; 第13 A及13B圖顯示第11圖所示之一黏劑的構造; 第14圖為根據本發明第十一實施例之一半導體元件的 15 剖視圖; 第15圖顯示身為第14圖所示之半導體元件的變化方式 之一半導體基材的剖視圖; 第16圖為根據本發明第十二實施例之一半導體元件的剖視 圖。 20 0續次頁(發明說明頁不敷使用時,請註記並使用續頁) 27 569411 發明說明 玖、發明說明 【圖式之主要元件代表符號表】 la…上中介層 10…黏晶黏劑 lb…下中介層 11…Au線 3a,3b,3c,3d53e53f,3g···半導體晶片 12.16…黏劑 4···阻焊劑 13…熱分散器 5a,5b…球塾 14…電極墊 7,7A…錫球 15…導線 8…凸塊 16A…黏劑膜 9···充填不足的黏劑 16Aa···開口
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Claims (1)
- 569411 拾:、申請專利範 5 1· 一種半導體元件,包含·· -第:半導體部件’其具有—電路形成表面及一 與該電路形成表面相對之背表面; …-第二介層’其具有—可供形成第—電極墊及 女凌/弟半導體邛件的表面’其中該電路 面對該第一中介層; 一第二半導體料,其具有-電㈣成表面及一 與該電路形成表面相對之背表面; 第二 10 中介層,其具有一可供形成第 電極墊及 15 2〇 安褒該第二半導體部件的表面且其中該電路形成表係 面對該第二中介層,該等第二電極塾用於連接該第一 中介層;及 ^ 外部連接端子,其設置於與可供安震該第二半導 體部件的表面相對之該第二中介層的一表面上, 其中該第一中介層及該第二中介層藉由該等第— 及第二電極墊之間的傳導性構件彼此電性連接,且,亥 第-半導體部件的背表面及該第二半導體部件的背: 面以一黏劑彼此固定。 2·如申請專利範圍第1項之半導體元件,進一步包含至少 一第三半導體部件,該至少一第三半導體部件係安裝 在與可供安裝該第一半導體部件的表面相對之該第一 中介層的一表面上。 3·如申請專利範圍第2項之半導體元件,其中複數個該等 第二半導體部件以一種堆疊及固定狀態安裝及包封在 續’人頁(申請專利範圓頁不驗觸,請註記並使臟頁) 29 569411 拾、申請專利範圍 申碑專利範圓續頁 該第一中介層的表面上。 4·如申請專利範圍第丨項之半導體元件,其中一用於釋放 熱量的金屬層係設置於與可供安裝該第一半導體部件 的表面相對之該第一中介層的一表面上。 5·如申請專利範圍第丨項之半導體元件,其中至少一第四 半導體部件係安裝在設有該等外部連接端子之該第二 中介層的表面上。 6. 如申請專利範圍第5項之半導體元件,其_複數個該等 第四半導體部件係設置及包封在該第二中介層上。 7. 如申請專利範圍第1項之半導體元件,其十1該等外部 連接端子為一平坦塾。 8. 如令請專利範圍第】項之半導體元件,其令各該等外部 連接端子具有一突起形狀。 9·如申請專利範圍第!項之半導體元件,其十各該等外部 連接端子係為從該第二中介層往外方向延伸之一導線 端子。 、 1〇.如申請專利範圍第1項之半導體元件,其中該用於將該 苐f半導體部件的背表面及該第二半導體部件的背表 彼此接5之黏劑係為_熱固型樹脂黏劑。 U·”請專利範圍第10項之半導體元件,其中該熱固型 樹脂黏劑包含銀及銅的其中至少一者。 12·如申請專利範圍第】項之半導 、、干V體7G件,其中提供一強化 黏劑以連接該等傳導性姑 ^ Γ生材枓及该等第一及第二中介層 之間的部份。 0續次頁(申請專利麵頁不敷使觸,請註記並使甩續頁) 30 申請專利範圍|實頁 拾、申請專利範圍.. ^ …v U Λ,.: 其中該強化黏 13.如申請專利範圍第12項之半導體元件 劑由一絕緣熱固型樹脂材料製成。 14·如申請專利範圍第12項 只 < 午¥體7〇件,其中該強化黏 劑係為一具有與該等傳導袖 X于1寻V性構件位置相對應的開口之 骠的形式。 15·—種半導體元件,包含: 電路形成表面及一一第一半導體部件,其具有一 與該電路形成表面相對之背表面; 可供形成第一電極墊及 ’其中該電路形成表係 一第一中介層,其具有一 安裝該第一半導體部件的表面 面對該第一中介層; 一第二半導體部件,其具有_電路形成表面及一 與#亥電路形成表面相對之背表面; 第一t介層’其具有一可供形成第二電極墊及 安裝該第二半導體部件的表面且其中該電路形成表係 m -令"層’該等第二電極墊用於連接該第一 申介層;及 外部連接端子,其設置於與可供安裝該第二半導 體部件的表面相對之該第二中介層的-表面上, 其尹6亥第一中介層及該第二尹介層藉由該等第一 及第二電極塾之間的傳導性構件彼此電性連接’且該 第一半導體部件及該第二半導體部件的背表面以一^ 劑彼此固定。 # 16·如申請專利範圍第15項之半導體元件,進-步包含至 3續次頁(申請專利範贿不敷使觸,請註記並使纖頁) 569411拾、申請專利範圍 ........_ ; )-弟二半導體部件,該至少—第三半導體部件係安裝 在可供安裝該第一半導體部件之該第-中介層的表面上。 17·如申:青專利範圍第15項之半導體元件,進一步包含至 少-第三半導體部件,該至少—第三半導體部件堆疊 在該第一半導體部件上,且該等第一及第三半導體部 件包封在該第一中介層上。 18·如申請專利範圍第叫之半導體元件,其中至少一第 四半導體部件係安裝在設有該等外部連接端子之該第 二中介層的表面上。 9.如申請專利範圍第18項之半導體元件,其中複數個該 專第四半導體部件設置及包封在該第二中介層上。 2〇.如申請專利範圍第15項之半導體元件,其中各該等外 部連接端子為一平坦塾。 21·如申料㈣圍第15奴半«元件,其巾各該等外 部連接端子具有一突起形狀。 &如申料㈣圍㈣項之半導體元件,其中各該等外 部連接端子係為從該第二中介層往外方向延伸之 線端子。 •如申料利範圍第15項之半導體元件,其中該用於將 該第一半導體部件的背表面及該第二半導體部件的背 表面彼此接合之黏劑係為—熱㈣樹脂黏劑。 24·如申凊專利範圍第23項之半導俨开杜 千¥體70件,其中該熱固型 樹脂黏劑包含銀及銅的其中至少一者。 技如申請專利範圍第15項之半導體元件,其令提供一強 0續次頁(申請專利範圍頁不酸觸,請註記並麵鑛) 32 第二中介 化黏劑以連接該等傳導性材料及該等第 層之間的部份。 26.如申請專利範圍第25項之半導體元件 劑由-絕緣熱固型樹脂材料製成。 〃 X強化黏 27·如申請專利範圍第25項之半 劑侍為g ^ 豆牛,其中該強化黏 撕-具有與該等傳導性構 獏的形式。直相對應的開口之 28·—種一半導體元件製 第-丰衣、方去’該半導體元件包含一 弟+V體部件及一第二半導 10含以下步驟: 件,該製造方法包 以使該第一半導體部件 ^^ ^ 电路形成表面面對該 -中介層上; “體部件安裝在一第 15 以使該第二半導體部件 电路形成表面面對該 :中"層的一狀態將該第二半導體部件安裝在一第 一中介層上; 藉由堆疊該等第-及第二中介層及介於其間的該 苐二半導體部件並加熱設置於該等第一及第二中介声 2〇之間的傳導性構件以融化該等傳導性構件,以使該第 -中介層及該第二中介層彼此電性連接;及 藉由該電性連接步驟中的熱量以固化-熱固性點 劑,該熱固性黏劑係設置於該第二半導體元件的一背 表面與該第—半導體部件的一背表面及該第-中介層 的其中一者之間。 33
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI466265B (zh) * | 2006-12-13 | 2014-12-21 | Shinko Electric Ind Co | 積層型封裝體及其製造方法 |
Families Citing this family (125)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
USRE44438E1 (en) * | 2001-02-27 | 2013-08-13 | Stats Chippac, Ltd. | Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate |
US20020121707A1 (en) * | 2001-02-27 | 2002-09-05 | Chippac, Inc. | Super-thin high speed flip chip package |
US8143108B2 (en) * | 2004-10-07 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate |
KR100480437B1 (ko) * | 2002-10-24 | 2005-04-07 | 삼성전자주식회사 | 반도체 칩 패키지 적층 모듈 |
KR100701380B1 (ko) * | 2002-12-30 | 2007-03-28 | 동부일렉트로닉스 주식회사 | 열발산형 반도체 패키지 구조 |
JP3891123B2 (ja) * | 2003-02-06 | 2007-03-14 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法 |
JP4110992B2 (ja) * | 2003-02-07 | 2008-07-02 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004259886A (ja) * | 2003-02-25 | 2004-09-16 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281818A (ja) * | 2003-03-17 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法 |
JP4069771B2 (ja) * | 2003-03-17 | 2008-04-02 | セイコーエプソン株式会社 | 半導体装置、電子機器および半導体装置の製造方法 |
JP3846437B2 (ja) * | 2003-03-17 | 2006-11-15 | 株式会社日立製作所 | 自動車用コントロールユニット |
JP2004281919A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP2004281920A (ja) * | 2003-03-18 | 2004-10-07 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP3680839B2 (ja) * | 2003-03-18 | 2005-08-10 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
JP4096774B2 (ja) * | 2003-03-24 | 2008-06-04 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 |
JP2004349495A (ja) * | 2003-03-25 | 2004-12-09 | Seiko Epson Corp | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
JP3786103B2 (ja) * | 2003-05-02 | 2006-06-14 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器および半導体装置の製造方法 |
JP3912318B2 (ja) | 2003-05-02 | 2007-05-09 | セイコーエプソン株式会社 | 半導体装置の製造方法および電子デバイスの製造方法 |
EP1636842B1 (en) | 2003-06-03 | 2011-08-17 | Casio Computer Co., Ltd. | Stackable semiconductor device and method of manufacturing the same |
TW200504895A (en) * | 2003-06-04 | 2005-02-01 | Renesas Tech Corp | Semiconductor device |
US7309923B2 (en) * | 2003-06-16 | 2007-12-18 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
US6984881B2 (en) * | 2003-06-16 | 2006-01-10 | Sandisk Corporation | Stackable integrated circuit package and method therefor |
JP2005072523A (ja) * | 2003-08-28 | 2005-03-17 | Hitachi Ltd | 半導体装置及びその製造方法 |
US20050046034A1 (en) | 2003-09-03 | 2005-03-03 | Micron Technology, Inc. | Apparatus and method for high density multi-chip structures |
US7180165B2 (en) * | 2003-09-05 | 2007-02-20 | Sanmina, Sci Corporation | Stackable electronic assembly |
DE10343255B4 (de) * | 2003-09-17 | 2006-10-12 | Infineon Technologies Ag | Verfahren zum Herstellen elektrischer Verbindungen zwischen einem Halbleiterchip in einem BGA-Gehäuse und einer Leiterplatte |
JP3867796B2 (ja) * | 2003-10-09 | 2007-01-10 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
US20050082526A1 (en) * | 2003-10-15 | 2005-04-21 | International Business Machines Corporation | Techniques for layer transfer processing |
TWI278048B (en) | 2003-11-10 | 2007-04-01 | Casio Computer Co Ltd | Semiconductor device and its manufacturing method |
JP4321758B2 (ja) * | 2003-11-26 | 2009-08-26 | カシオ計算機株式会社 | 半導体装置 |
KR100564585B1 (ko) * | 2003-11-13 | 2006-03-28 | 삼성전자주식회사 | 이중 스택된 bga 패키지 및 다중 스택된 bga 패키지 |
TW200536089A (en) * | 2004-03-03 | 2005-11-01 | United Test & Assembly Ct Ltd | Multiple stacked die window csp package and method of manufacture |
JP3925809B2 (ja) | 2004-03-31 | 2007-06-06 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
JP3972209B2 (ja) * | 2004-05-26 | 2007-09-05 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4051570B2 (ja) | 2004-05-26 | 2008-02-27 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6987314B1 (en) * | 2004-06-08 | 2006-01-17 | Amkor Technology, Inc. | Stackable semiconductor package with solder on pads on which second semiconductor package is stacked |
JP4865197B2 (ja) * | 2004-06-30 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR100630690B1 (ko) * | 2004-07-08 | 2006-10-02 | 삼성전자주식회사 | 열 소산 경로를 구비한 멀티 칩 패키지 |
JP4626445B2 (ja) * | 2004-08-24 | 2011-02-09 | ソニー株式会社 | 半導体パッケージの製造方法 |
CN100378993C (zh) * | 2004-08-26 | 2008-04-02 | 财团法人工业技术研究院 | 一种立体堆栈式封装结构 |
KR100688500B1 (ko) * | 2004-09-06 | 2007-03-02 | 삼성전자주식회사 | 반도체 칩 보호용 더미 패키지 기판을 구비하는 멀티스택패키지와 그 제조 방법 |
JP4601365B2 (ja) * | 2004-09-21 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7106079B2 (en) * | 2004-10-22 | 2006-09-12 | Sun Microsystems, Inc. | Using an interposer to facilate capacitive communication between face-to-face chips |
US20060108676A1 (en) * | 2004-11-22 | 2006-05-25 | Punzalan Nelson V Jr | Multi-chip package using an interposer |
US7235870B2 (en) * | 2004-12-30 | 2007-06-26 | Punzalan Jr Nelson V | Microelectronic multi-chip module |
JP2006196709A (ja) * | 2005-01-13 | 2006-07-27 | Sharp Corp | 半導体装置およびその製造方法 |
US7709943B2 (en) | 2005-02-14 | 2010-05-04 | Daniel Michaels | Stacked ball grid array package module utilizing one or more interposer layers |
US7875966B2 (en) * | 2005-02-14 | 2011-01-25 | Stats Chippac Ltd. | Stacked integrated circuit and package system |
US7659623B2 (en) | 2005-04-11 | 2010-02-09 | Elpida Memory, Inc. | Semiconductor device having improved wiring |
JP2006324568A (ja) * | 2005-05-20 | 2006-11-30 | Matsushita Electric Ind Co Ltd | 多層モジュールとその製造方法 |
US20060267173A1 (en) * | 2005-05-26 | 2006-11-30 | Sandisk Corporation | Integrated circuit package having stacked integrated circuits and method therefor |
US7638866B1 (en) * | 2005-06-01 | 2009-12-29 | Rockwell Collins, Inc. | Stacked packaging designs offering inherent anti-tamper protection |
JP2006352008A (ja) * | 2005-06-20 | 2006-12-28 | Nec Electronics Corp | 半導体装置および回路基板 |
JP4551321B2 (ja) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
US7265441B2 (en) * | 2005-08-15 | 2007-09-04 | Infineon Technologies Ag | Stackable single package and stacked multi-chip assembly |
JP5116268B2 (ja) * | 2005-08-31 | 2013-01-09 | キヤノン株式会社 | 積層型半導体装置およびその製造方法 |
US7485969B2 (en) * | 2005-09-01 | 2009-02-03 | Micron Technology, Inc. | Stacked microelectronic devices and methods for manufacturing microelectronic devices |
JP4473807B2 (ja) * | 2005-10-27 | 2010-06-02 | パナソニック株式会社 | 積層半導体装置及び積層半導体装置の下層モジュール |
US7737539B2 (en) * | 2006-01-12 | 2010-06-15 | Stats Chippac Ltd. | Integrated circuit package system including honeycomb molding |
US8409921B2 (en) * | 2006-01-12 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit package system including honeycomb molding |
US7750482B2 (en) * | 2006-02-09 | 2010-07-06 | Stats Chippac Ltd. | Integrated circuit package system including zero fillet resin |
US7684205B2 (en) * | 2006-02-22 | 2010-03-23 | General Dynamics Advanced Information Systems, Inc. | System and method of using a compliant lead interposer |
US7652361B1 (en) * | 2006-03-03 | 2010-01-26 | Amkor Technology, Inc. | Land patterns for a semiconductor stacking structure and method therefor |
US8367465B2 (en) * | 2006-03-17 | 2013-02-05 | Stats Chippac Ltd. | Integrated circuit package on package system |
JP2007287906A (ja) * | 2006-04-17 | 2007-11-01 | Elpida Memory Inc | 電極と電極の製造方法、及びこの電極を備えた半導体装置 |
US20070252260A1 (en) * | 2006-04-28 | 2007-11-01 | Micron Technology, Inc. | Stacked die packages |
CN101449377B (zh) * | 2006-05-19 | 2011-04-20 | 住友电木株式会社 | 半导体器件 |
US7550680B2 (en) * | 2006-06-14 | 2009-06-23 | Stats Chippac Ltd. | Package-on-package system |
JP4901384B2 (ja) * | 2006-09-14 | 2012-03-21 | パナソニック株式会社 | 樹脂配線基板とそれを用いた半導体装置および積層型の半導体装置 |
JP2008085089A (ja) * | 2006-09-28 | 2008-04-10 | Matsushita Electric Ind Co Ltd | 樹脂配線基板および半導体装置 |
KR100885911B1 (ko) * | 2006-11-16 | 2009-02-26 | 삼성전자주식회사 | 열방출 특성을 개선한 반도체 패키지 |
JP2008166440A (ja) * | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置 |
KR101332861B1 (ko) * | 2007-01-03 | 2013-11-22 | 삼성전자주식회사 | 아이씨 패키지 및 그 제조방법 |
JP2008198916A (ja) * | 2007-02-15 | 2008-08-28 | Spansion Llc | 半導体装置及びその製造方法 |
JP4751351B2 (ja) * | 2007-02-20 | 2011-08-17 | 株式会社東芝 | 半導体装置とそれを用いた半導体モジュール |
US8124451B2 (en) | 2007-09-21 | 2012-02-28 | Stats Chippac Ltd. | Integrated circuit packaging system with interposer |
KR20090033605A (ko) * | 2007-10-01 | 2009-04-06 | 삼성전자주식회사 | 적층형 반도체 패키지, 그 형성방법 및 이를 구비하는전자장치 |
TWI415201B (zh) * | 2007-11-30 | 2013-11-11 | 矽品精密工業股份有限公司 | 多晶片堆疊結構及其製法 |
TW200931634A (en) * | 2008-01-10 | 2009-07-16 | Abounion Technology Corp | Multi-channel stacked semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device |
JP5543071B2 (ja) * | 2008-01-21 | 2014-07-09 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置およびこれを有する半導体モジュール |
TWM342699U (en) * | 2008-03-12 | 2008-10-11 | Askey Computer Corp | Wireless-signal processing circuit |
KR100997793B1 (ko) | 2008-09-01 | 2010-12-02 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이의 제조 방법 |
KR101198411B1 (ko) * | 2008-11-17 | 2012-11-07 | 삼성전기주식회사 | 패키지 온 패키지 기판 |
US8716868B2 (en) * | 2009-05-20 | 2014-05-06 | Panasonic Corporation | Semiconductor module for stacking and stacked semiconductor module |
JP5271861B2 (ja) * | 2009-10-07 | 2013-08-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR101665556B1 (ko) * | 2009-11-19 | 2016-10-13 | 삼성전자 주식회사 | 멀티 피치 볼 랜드를 갖는 반도체 패키지 |
US8476775B2 (en) * | 2009-12-17 | 2013-07-02 | Stats Chippac Ltd. | Integrated circuit packaging system with embedded interconnect and method of manufacture thereof |
TWI416700B (zh) * | 2009-12-29 | 2013-11-21 | Chipmos Technologies Inc | 晶片堆疊封裝結構及其製造方法 |
US9355939B2 (en) * | 2010-03-02 | 2016-05-31 | Stats Chippac Ltd. | Integrated circuit package stacking system with shielding and method of manufacture thereof |
US8618654B2 (en) * | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
KR101132304B1 (ko) | 2010-05-06 | 2012-04-05 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조방법 |
US8434222B2 (en) * | 2010-08-27 | 2013-05-07 | International Business Machines Corporation | Method to manufacture a circuit apparatus having a rounded differential pair trace |
US8304880B2 (en) * | 2010-09-14 | 2012-11-06 | Stats Chippac Ltd. | Integrated circuit packaging system with package-on-package and method of manufacture thereof |
US8378477B2 (en) * | 2010-09-14 | 2013-02-19 | Stats Chippac Ltd. | Integrated circuit packaging system with film encapsulation and method of manufacture thereof |
WO2012035972A1 (ja) * | 2010-09-17 | 2012-03-22 | 住友ベークライト株式会社 | 半導体パッケージおよび半導体装置 |
US9865310B2 (en) * | 2011-02-24 | 2018-01-09 | Interconnect Systems, Inc. | High density memory modules |
KR101740483B1 (ko) * | 2011-05-02 | 2017-06-08 | 삼성전자 주식회사 | 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지 |
KR20130005465A (ko) * | 2011-07-06 | 2013-01-16 | 삼성전자주식회사 | 반도체 스택 패키지 장치 |
US9123763B2 (en) * | 2011-10-12 | 2015-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material |
US8975741B2 (en) | 2011-10-17 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process for forming package-on-package structures |
CN105977180B (zh) * | 2012-01-06 | 2020-05-08 | 日月光半导体制造股份有限公司 | 具有测试结构的半导体封装元件及其测试方法 |
US8907469B2 (en) | 2012-01-19 | 2014-12-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package assembly and method of forming the same |
JP2013243263A (ja) * | 2012-05-21 | 2013-12-05 | Internatl Business Mach Corp <Ibm> | 3次元積層パッケージにおける電力供給と放熱(冷却)との両立 |
US9385006B2 (en) * | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
CN103887263B (zh) * | 2012-12-21 | 2016-12-28 | 碁鼎科技秦皇岛有限公司 | 封装结构及其制作方法 |
WO2014171403A1 (ja) * | 2013-04-17 | 2014-10-23 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
CN104347557A (zh) * | 2013-07-26 | 2015-02-11 | 日月光半导体制造股份有限公司 | 半导体封装件及其的制造方法 |
CN104795368B (zh) * | 2014-01-17 | 2017-10-20 | 日月光半导体制造股份有限公司 | 半导体封装结构及半导体工艺 |
KR102186203B1 (ko) * | 2014-01-23 | 2020-12-04 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
US20150221570A1 (en) * | 2014-02-04 | 2015-08-06 | Amkor Technology, Inc. | Thin sandwich embedded package |
JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
CN103985695B (zh) * | 2014-05-19 | 2017-07-25 | 中国科学院微电子研究所 | 一种扇出型封装结构及其制作工艺 |
US9355898B2 (en) | 2014-07-30 | 2016-05-31 | Qualcomm Incorporated | Package on package (PoP) integrated device comprising a plurality of solder resist layers |
KR102341755B1 (ko) | 2014-11-10 | 2021-12-23 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR101619455B1 (ko) * | 2014-11-18 | 2016-05-11 | 주식회사 프로텍 | 적층형 반도체 패키지의 제조방법 |
KR101672622B1 (ko) | 2015-02-09 | 2016-11-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
WO2016174899A1 (ja) * | 2015-04-27 | 2016-11-03 | 富士電機株式会社 | 半導体装置 |
US10163867B2 (en) | 2015-11-12 | 2018-12-25 | Amkor Technology, Inc. | Semiconductor package and manufacturing method thereof |
US10068866B2 (en) * | 2016-09-29 | 2018-09-04 | Intel Corporation | Integrated circuit package having rectangular aspect ratio |
US10636774B2 (en) | 2017-09-06 | 2020-04-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a 3D integrated system-in-package module |
US10468384B2 (en) | 2017-09-15 | 2019-11-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same |
US10410999B2 (en) | 2017-12-19 | 2019-09-10 | Amkor Technology, Inc. | Semiconductor device with integrated heat distribution and manufacturing method thereof |
US10636756B2 (en) | 2018-07-05 | 2020-04-28 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming protrusion E-bar for 3D SIP |
US11296065B2 (en) * | 2020-06-15 | 2022-04-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor packages and methods of forming same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2856782B2 (ja) * | 1989-10-12 | 1999-02-10 | レール・リキード・ソシエテ・アノニム・プール・レテユード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード | 低温cvdによる銅薄膜の形成方法 |
US5394608A (en) * | 1992-04-08 | 1995-03-07 | Hitachi Maxwell, Ltd. | Laminated semiconductor device and fabricating method thereof |
US5247423A (en) * | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
US6784023B2 (en) * | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
US6225688B1 (en) * | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
JPH10294423A (ja) * | 1997-04-17 | 1998-11-04 | Nec Corp | 半導体装置 |
US5956233A (en) * | 1997-12-19 | 1999-09-21 | Texas Instruments Incorporated | High density single inline memory module |
TW472330B (en) * | 1999-08-26 | 2002-01-11 | Toshiba Corp | Semiconductor device and the manufacturing method thereof |
JP3798597B2 (ja) * | 1999-11-30 | 2006-07-19 | 富士通株式会社 | 半導体装置 |
DE10029259A1 (de) * | 2000-06-14 | 2001-12-20 | Orient Semiconductor Elect Ltd | Verbesserte Struktur eines Stapelmoduls für Chips |
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2002
- 2002-04-19 JP JP2002117534A patent/JP2003318361A/ja active Pending
- 2002-10-17 TW TW091123964A patent/TW569411B/zh active
- 2002-10-17 US US10/272,013 patent/US6781241B2/en not_active Expired - Fee Related
- 2002-10-30 KR KR1020020066352A patent/KR20030083553A/ko not_active Application Discontinuation
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2003
- 2003-03-19 EP EP03006051A patent/EP1355352A3/en not_active Withdrawn
- 2003-04-17 CN CN03123119A patent/CN1452245A/zh active Pending
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI466265B (zh) * | 2006-12-13 | 2014-12-21 | Shinko Electric Ind Co | 積層型封裝體及其製造方法 |
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JP2003318361A (ja) | 2003-11-07 |
US20030197260A1 (en) | 2003-10-23 |
US6781241B2 (en) | 2004-08-24 |
EP1355352A2 (en) | 2003-10-22 |
CN1452245A (zh) | 2003-10-29 |
KR20030083553A (ko) | 2003-10-30 |
EP1355352A3 (en) | 2005-10-05 |
US6960827B2 (en) | 2005-11-01 |
US20040188855A1 (en) | 2004-09-30 |
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