DE10029259A1 - Verbesserte Struktur eines Stapelmoduls für Chips - Google Patents

Verbesserte Struktur eines Stapelmoduls für Chips

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Publication number
DE10029259A1
DE10029259A1 DE10029259A DE10029259A DE10029259A1 DE 10029259 A1 DE10029259 A1 DE 10029259A1 DE 10029259 A DE10029259 A DE 10029259A DE 10029259 A DE10029259 A DE 10029259A DE 10029259 A1 DE10029259 A1 DE 10029259A1
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Germany
Prior art keywords
chips
substrate
substrates
connections
stack module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10029259A
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English (en)
Inventor
Xie Wan Le
Chuang Yung Cheng
Huang Ning
Chen Hui Pin
Chiang Hua Wen
Chang Chuang Ming
Tu Feng Chang
Huang Fu Yu
Chang Hsuan Jui
Hu Chia Chieh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Semiconductor Electronics Ltd
Original Assignee
Orient Semiconductor Electronics Ltd
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Publication date
Application filed by Orient Semiconductor Electronics Ltd filed Critical Orient Semiconductor Electronics Ltd
Priority to DE10029259A priority Critical patent/DE10029259A1/de
Publication of DE10029259A1 publication Critical patent/DE10029259A1/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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    • H01L2225/1047—Details of electrical connections between containers
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

Ein Stapelmodul für Chips enthält wenigstens ein Substrat (20a), auf dem auf beiden Seiten wenigstens ein Chip (21a, 21b) befestigt ist und zum Schutz vor der Umgebung gekapselt ist, wodurch die Herstellungsdauer verringert wird, Material für das Substrat und die Anschlüsse eingespart wird und die Höhe des Stapelmoduls erheblich verringert wird. Ferner kann die Unterseite des Substrats (20a) auf einer Oberseite eines ähnlichen Substrats (20b) gestapelt werden, wobei auf beiden Seiten Chips (21a, 21b, 21c, 21d) befestigt und zum Schutz vor der Umgebung gekapselt sind mittels Anschlüssen (23a, 23b) zwischen den Substraten (20a, 20b), wodurch ein Stapelmodul aus mehreren Schichten gebildet wird.

Description

Die Erfindung bezieht sich auf eine Verbesserung der Struktur eines Stapel­ moduls für Chips und insbesondere auf eine Struktur, die wenigstens ein Sub­ strat enthält, das mit einem Chip an seiner Oberseite und seiner Unterseite versehen ist und ermöglicht, zwei oder mehr Substrate zu stapeln, um ein Modul zu bilden.
Wie in den Fig. 1 und 3 gezeigt, enthält das herkömmliche Stapelmodul von vier Schichten 1A für Chips vier Substrate 10a, 10b, 10c und 10d, auf deren Oberseiten jeweils Chips 11a, 11b, 11c und 11d montiert sind, die anschlie­ ßend gekapselt werden, um sie vor der Umgebung zu schützen. Anschließend werden die Anschlüsse 13a, 13b und 13c jeweils zwischen den Substraten 10a und 10b, 10b und 10c, 10c und 10d angeordnet, wobei die Anschlüsse 13d an der Unterseite des Substrats 10d befestigt werden, um eine Packung von vier Chips zu bilden.
In ähnlicher Weise kann der Chip 11e an der Unterseite des Substrats ange­ bracht sein (siehe Fig. 2), um ein Stapelmodul zu bilden.
Das herkömmliche Stapelmodul verwendet jedoch nur eine einzelne Seite des Substrats, um einen Chip zu montieren, so daß dann, wenn mehrere Substrate aufeinander gestapelt werden, das Stapelmodul ein großes Volumen erreicht, wodurch es für die Verwendung in einer Vorrichtung mit geringer Höhe, wie z. B. einem Notebook-Computer, einem Mobiltelephon, einem persönlichen digitalen Notizbuch (PDA) oder einer Digitalkamera, ungeeignet wird.
Ferner müssen die Chips zuerst am Substrat angebracht werden und durch Kapselung vor der Umgebung geschützt werden, woraufhin die Anschlüsse auf dem Substrat montiert werden, bevor das Substrat auf einem ähnlichen Substrat gestapelt wird, was bei der Herstellung sehr unbequem ist und die Produktionsrate senkt.
Es ist daher die Aufgabe der Erfindung, die Nachteile des obenerwähnten Standes der Technik zu beseitigen und eine verbesserte Struktur eines Stapel­ moduls für Chips zu schaffen.
Diese Aufgabe wird erfindungsgemäß gelöst durch ein Stapelmodul für Chips, das die Anspruch 1 angegebenen Merkmale besitzt. Der abhängige Anspruch ist auf eine bevorzugte Ausführungsform gerichtet.
Weitere Merkmale und Vorteile der Erfindung werden deutlich beim Lesen der folgenden Beschreibung bevorzugter Ausführungsformen, die auf die beigefügten Zeichnungen Bezug nimmt; es zeigen:
Fig. 1 die bereits erwähnte Schnittansicht eines Stapelmoduls für Chips des Standes der Technik;
Fig. 2 die bereits erwähnte Schnittansicht eines weiteren Stapelmoduls für Chips des Standes der Technik;
Fig. 3 die bereits erwähnte Schnittansicht eines Stapelmoduls des Standes der Technik mit zwei Schichten;
Fig. 4 eine Schnittansicht eines Stapelmoduls mit zwei Schichten gemäß der Erfindung; und
Fig. 5 eine Schnittansicht eines Stapelmoduls mit einer einzelnen Schicht gemäß der Erfindung.
Wie in den Zeichnungen und insbesondere in Fig. 4 gezeigt, umfaßt das Sta­ pelmodul 2A gemäß der Erfindung mehrere Substrate (in dieser bevorzugten Ausführungsform zwei) 20a und 20b. Ein Chip 21a ist an der Oberseite des Substrats 20a befestigt, während ein weiterer Chip 21b an der Unterseite des Substrats 20b befestigt ist. In ähnlicher Weise sind die Chips 21c und 21d an der Oberseite und der Unterseite des Substrats 20b befestigt. Anschließend werden die Chips 21a und 21b, 21c und 21d gekapselt, um diese vor der Um­ gebung zu schützen. Anschließend werden die Anschlüsse 23a zwischen der Unterseite des Substrats 20a und der Oberseite des Substrats 20b eingesetzt, während die Anschlüsse 23b an der Unterseite des Substrats 20b angebracht werden, wodurch ein Stapelmodul für Chips gebildet wird.
Es ist jedoch zu beachten, daß die Chips an der Oberseite des Substrats befe­ stigt und gleichzeitig gekapselt werden können, wenn die Chips an der Unter­ seite des Substrats befestigt und vor der Umgebung geschützt gekapselt wer­ den, wodurch die für den Produktionsprozeß erforderliche Zeitspanne redu­ ziert werden kann.
Wie in Fig. 5 gezeigt, umfaßt das Stapelmodul 2B gemäß der Erfindung ein einzelnes Substrat 20a, auf dessen Oberseite und Unterseite die Chips 21a bzw. 21b befestigt sind, so daß ein Stapelmodul 2B mit einer einzelnen Sub­ stratschicht gemäß der Erfindung verwendet werden kann, um das herkömmli­ che Stapelmodul 1 C mit zwei Schichten von Substraten zu ersetzen, wodurch die Höhe des Stapelmoduls erheblich verringert wird und Material für das Substrat und die Anschlüsse eingespart wird und die Produktionsrate erhöht wird.

Claims (2)

1. Stapelmodul für Chips, gekennzeichnet durch wenigstens ein Substrat (20a), auf dem auf beiden Seiten wenigstens jeweils ein Chip (21a, 21b) befestigt ist und zum Schutz vor der Umgebung gekapselt ist.
2. Stapelmodul nach Anspruch 1, dadurch gekennzeichnet, daß die Unterseite des Substrats (20a) auf einer Oberseite eines ähnlichen Substrats (20b) gestapelt werden kann, wobei auf beiden Seiten Chips (21a, 21b, 21c, 21d) befestigt und zum Schutz vor der Umgebung gekapselt sind mittels Anschlüssen (23a, 23b) zwischen dem Substrat (20a) und dem ähnli­ chen Substrat (20b).
DE10029259A 2000-06-14 2000-06-14 Verbesserte Struktur eines Stapelmoduls für Chips Withdrawn DE10029259A1 (de)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1355352A2 (de) * 2002-04-19 2003-10-22 Fujitsu Limited Stapelhalbleiterbauteil und seine Herstellung
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US7103970B2 (en) 2001-03-14 2006-09-12 Legacy Electronics, Inc. Method for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
US7405471B2 (en) 2000-10-16 2008-07-29 Legacy Electronics, Inc. Carrier-based electronic module
DE102013217301A1 (de) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Bauteil

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7102892B2 (en) 2000-03-13 2006-09-05 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US7796400B2 (en) 2000-03-13 2010-09-14 Legacy Electronics, Inc. Modular integrated circuit chip carrier
US7405471B2 (en) 2000-10-16 2008-07-29 Legacy Electronics, Inc. Carrier-based electronic module
US7103970B2 (en) 2001-03-14 2006-09-12 Legacy Electronics, Inc. Method for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
EP1355352A2 (de) * 2002-04-19 2003-10-22 Fujitsu Limited Stapelhalbleiterbauteil und seine Herstellung
EP1355352A3 (de) * 2002-04-19 2005-10-05 Fujitsu Limited Stapelhalbleiterbauteil und seine Herstellung
DE102013217301A1 (de) * 2013-08-30 2015-03-05 Robert Bosch Gmbh Bauteil

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