DE19821916C2 - Halbleitereinrichtung mit einem BGA-Substrat - Google Patents
Halbleitereinrichtung mit einem BGA-SubstratInfo
- Publication number
- DE19821916C2 DE19821916C2 DE19821916A DE19821916A DE19821916C2 DE 19821916 C2 DE19821916 C2 DE 19821916C2 DE 19821916 A DE19821916 A DE 19821916A DE 19821916 A DE19821916 A DE 19821916A DE 19821916 C2 DE19821916 C2 DE 19821916C2
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor chip
- semiconductor device
- bga substrate
- insulating layer
- bga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L2224/732—Location after the connecting process
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
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- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/161—Cap
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- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
Claims (3)
einem BGA-Substrat (1), welches eine obere Isolierschicht (1b) aufweist, in der eine Mehrzahl von Isolierschichten übereinandergeschichtet sind, eine Zwi schenschicht (1a), die als Kernschicht dient, eine untere Isolierschicht (13), in der eine Mehrzahl von Isolierschichten übereinandergeschichtet sind;
einer Mehrzahl von Leitungen (9), die jeweils auf jeder obersten Oberfläche der Isolierschichten vorgesehen sind, die in der oberen Isolierschicht (1b), der Zwischenisolierschicht (1a) und der unteren Isolierschicht (1b) enthalten sind;
einer Mehrzahl von Lötkugeln (6), die auf der äußersten Oberfläche der unte ren Isolierschicht (1b) vorgesehen sind; und
einem Halbleiterchip (2) mit einer Mehrzahl von Elektroden zum jeweils Ver binden mit der Mehrzahl von Leitungen, wobei der Halbleiterchip elektrisch mit der Mehrzahl von Lötkugeln (6) über eine Mehrzahl von Durchgangslöchern (12) verbunden ist, die in jeder der Isolierschichten vorgesehen sind,
dadurch gekennzeichnet, daß
die Mehrzahl von Elektroden in einem ringförmigen Bereich auf dem Halb leiterchip vorgesehen sind, und die Spannungsversorgung und Masse jeweils sowohl mit Elektroden auf der äußersten Umfangszeile als auch der innersten Umfangszeile verbunden sind.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19861009A DE19861009B4 (de) | 1997-08-28 | 1998-05-15 | Halbleitereinrichtung |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23192797A JP4190602B2 (ja) | 1997-08-28 | 1997-08-28 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19821916A1 DE19821916A1 (de) | 1999-03-11 |
DE19821916C2 true DE19821916C2 (de) | 2002-01-10 |
Family
ID=16931250
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19821916A Expired - Lifetime DE19821916C2 (de) | 1997-08-28 | 1998-05-15 | Halbleitereinrichtung mit einem BGA-Substrat |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP4190602B2 (de) |
KR (1) | KR100286746B1 (de) |
DE (1) | DE19821916C2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6091603A (en) * | 1999-09-30 | 2000-07-18 | International Business Machines Corporation | Customizable lid for improved thermal performance of modules using flip chips |
FR2803435A1 (fr) * | 1999-12-30 | 2001-07-06 | Schlumberger Systems & Service | Procede de montage en flip-chip de circuits integres sur des circuits electriques |
JP4715035B2 (ja) * | 2001-05-28 | 2011-07-06 | パナソニック電工株式会社 | 半導体装置 |
KR100708041B1 (ko) * | 2001-07-28 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
US6979894B1 (en) | 2001-09-27 | 2005-12-27 | Marvell International Ltd. | Integrated chip package having intermediate substrate |
KR20030060268A (ko) * | 2002-01-08 | 2003-07-16 | 주식회사 심텍 | 본딩패드 접속용 비아홀을 이용한 비지에이 반도체패키지의 제조방법 및 그 구조 |
JP4072523B2 (ja) | 2004-07-15 | 2008-04-09 | 日本電気株式会社 | 半導体装置 |
JP5017881B2 (ja) * | 2006-02-17 | 2012-09-05 | 日本電気株式会社 | 半導体装置 |
JP4953132B2 (ja) | 2007-09-13 | 2012-06-13 | 日本電気株式会社 | 半導体装置 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
DE4325668A1 (de) * | 1992-07-30 | 1994-02-03 | Toshiba Kawasaki Kk | Mehrebenen-Verdrahtungssubstrat und dieses verwendende Halbleiteranordnung |
JPH088359A (ja) * | 1994-06-21 | 1996-01-12 | Hitachi Ltd | 半導体集積回路装置 |
EP0713359A1 (de) * | 1994-11-21 | 1996-05-22 | International Business Machines Corporation | Leiterplatten mit selektiv gefüllten plattierten Durchgangslöchern |
US5574630A (en) * | 1995-05-11 | 1996-11-12 | International Business Machines Corporation | Laminated electronic package including a power/ground assembly |
JPH08330474A (ja) * | 1995-03-31 | 1996-12-13 | Toshiba Corp | 半導体用パッケージ |
JPH0945809A (ja) * | 1995-07-31 | 1997-02-14 | Fujitsu Ltd | 半導体装置及び半導体装置実装用基板 |
JPH0964090A (ja) * | 1995-08-25 | 1997-03-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
EP0883173A1 (de) * | 1996-09-12 | 1998-12-09 | Ibiden Co., Ltd. | Leiterplatte zur montage elektronischer bauelemente |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3450477B2 (ja) * | 1994-12-20 | 2003-09-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
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1997
- 1997-08-28 JP JP23192797A patent/JP4190602B2/ja not_active Expired - Lifetime
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1998
- 1998-05-15 DE DE19821916A patent/DE19821916C2/de not_active Expired - Lifetime
- 1998-05-19 KR KR1019980018023A patent/KR100286746B1/ko not_active IP Right Cessation
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
DE4325668A1 (de) * | 1992-07-30 | 1994-02-03 | Toshiba Kawasaki Kk | Mehrebenen-Verdrahtungssubstrat und dieses verwendende Halbleiteranordnung |
JPH088359A (ja) * | 1994-06-21 | 1996-01-12 | Hitachi Ltd | 半導体集積回路装置 |
EP0713359A1 (de) * | 1994-11-21 | 1996-05-22 | International Business Machines Corporation | Leiterplatten mit selektiv gefüllten plattierten Durchgangslöchern |
JPH08330474A (ja) * | 1995-03-31 | 1996-12-13 | Toshiba Corp | 半導体用パッケージ |
US5574630A (en) * | 1995-05-11 | 1996-11-12 | International Business Machines Corporation | Laminated electronic package including a power/ground assembly |
JPH0945809A (ja) * | 1995-07-31 | 1997-02-14 | Fujitsu Ltd | 半導体装置及び半導体装置実装用基板 |
US5760469A (en) * | 1995-07-31 | 1998-06-02 | Fujitsu Limited | Semiconductor device and semiconductor device mounting board |
JPH0964090A (ja) * | 1995-08-25 | 1997-03-07 | Hitachi Ltd | 半導体装置およびその製造方法 |
US5849606A (en) * | 1995-08-25 | 1998-12-15 | Hitachi, Ltd. | Semiconductor device and manufacturing of the same |
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KR100286746B1 (ko) | 2001-04-16 |
DE19821916A1 (de) | 1999-03-11 |
JP4190602B2 (ja) | 2008-12-03 |
JPH1174417A (ja) | 1999-03-16 |
KR19990023135A (ko) | 1999-03-25 |
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