KR19990023135A - 반도체 장치 - Google Patents
반도체 장치 Download PDFInfo
- Publication number
- KR19990023135A KR19990023135A KR1019980018023A KR19980018023A KR19990023135A KR 19990023135 A KR19990023135 A KR 19990023135A KR 1019980018023 A KR1019980018023 A KR 1019980018023A KR 19980018023 A KR19980018023 A KR 19980018023A KR 19990023135 A KR19990023135 A KR 19990023135A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating layer
- semiconductor chip
- semiconductor device
- wirings
- substrate
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 229910000679 solder Inorganic materials 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000011368 organic material Substances 0.000 claims abstract description 12
- 239000011347 resin Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 description 86
- 239000012790 adhesive layer Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 3
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011162 core material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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Abstract
Description
Claims (3)
- 적층된 복수의 절연층으로 되는 상부 절연층, 중부절연층, 적층된 복수의 절연층으로 되는 하부절연층, 상부절연층, 중부절연층, 및 하부절연층에 포함된 전체의 절연층의 각각의 상면에 설치된 복수의 배선, 및 상기 하부절연층의 외측표면상에 설치된 복수의 땜납볼로 된 BGA 기판과, 상기 복수의 배선에 각각 접속되는 복수의 전극을 가지는 반도체칩을 포함하게되고, 상기 전체의 절연층의 각각에 설치된 비어홀을 개재해서 상기 반도체칩과 상기 땜납볼이 전기적으로 접속하게되는 반도체 장치에 있어서,상기 복수의 절연층의 재료가 반도체 장치가 실장되는 실장 기판의 열팽창특성에 맞춘 유기재료로 되는 반도체 장치.
- 적층된 복수의 절연층으로 된 상부절연층, 중부절연층, 적층된 복수의 절연층으로 된 하부절연층, 상부절연층, 중부절연층, 및 하부절연층에 포함되는 전체의 절연층의 각각의 상면에 설치된 복수의 배선, 및 상기 하부절연층의 외측표면상에 설치된 복수의 땜납볼로 되는 BGA 기판과, 상기 복수의 배선에 각각 접속되는 복수의 전극을 가지는 반도체칩을 포함하게되고, 상기 전체의 절연층의 각각에 설치된 비어홀을 개재해서 상기 반도체칩과 상기 땜납볼이 전기적으로 접속되게 되는 반도체 장치에 있어서,상기 복수의 전극이 상기 반도체칩의 링모양의 영역으로 설치되어, 최외주 및 최내주의 열상의 전극에 각각 전원, 및 접지가 접속되는 반도체 장치.
- 적층된 복수의 절연층으로 되는 상부절연층, 중부절연층, 적층된복수의 절연층으로된 하부절연층, 상부절연층, 중부절연층, 및 하부절연층에 포함된 전체의 절연층의 각각의 상면에 설치된 복수의 배선 및 상기 하부절연층의 외측표면상에 설치된 복수의 땜납볼로 된 BGA 기판과,상기 복수의 배선에 각각 접속된 복수의 전극을 가지는 반도체칩과, 해당 반도체칩을 BGA 기판에 밀착시킨 봉지수지로 된 봉지부재와,상기 반도체칩에서 발생된 열을 외부로 발산하는 히트 스프레더와,상기 BGA 기판 및 히트 스프레더 사이에 소정의 간격을 설치하고 또 양자를 접합하기 위한 링을 포함하게 되며, 상기 전체의 절연층의 각각에 설치된 비어홀을 개재해서 상기 반도체칩과 상기 땜납볼이 전기적으로 접속하게 되는 반도체 장치에 있어서, 상기 복수의 절연층의 재료가 반도체 장치가 실장된 기판의 열팽창특성에 맞춘 유기재료로 되는 반도체 장치.
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JP23192797A JP4190602B2 (ja) | 1997-08-28 | 1997-08-28 | 半導体装置 |
JP231927 | 1997-08-28 |
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KR19990023135A true KR19990023135A (ko) | 1999-03-25 |
KR100286746B1 KR100286746B1 (ko) | 2001-04-16 |
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KR1019980018023A KR100286746B1 (ko) | 1997-08-28 | 1998-05-19 | 반도체 장치 |
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JP (1) | JP4190602B2 (ko) |
KR (1) | KR100286746B1 (ko) |
DE (1) | DE19821916C2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100708041B1 (ko) * | 2001-07-28 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6091603A (en) * | 1999-09-30 | 2000-07-18 | International Business Machines Corporation | Customizable lid for improved thermal performance of modules using flip chips |
FR2803435A1 (fr) * | 1999-12-30 | 2001-07-06 | Schlumberger Systems & Service | Procede de montage en flip-chip de circuits integres sur des circuits electriques |
JP4715035B2 (ja) * | 2001-05-28 | 2011-07-06 | パナソニック電工株式会社 | 半導体装置 |
US6979894B1 (en) | 2001-09-27 | 2005-12-27 | Marvell International Ltd. | Integrated chip package having intermediate substrate |
KR20030060268A (ko) * | 2002-01-08 | 2003-07-16 | 주식회사 심텍 | 본딩패드 접속용 비아홀을 이용한 비지에이 반도체패키지의 제조방법 및 그 구조 |
JP4072523B2 (ja) | 2004-07-15 | 2008-04-09 | 日本電気株式会社 | 半導体装置 |
JP5017881B2 (ja) * | 2006-02-17 | 2012-09-05 | 日本電気株式会社 | 半導体装置 |
JP4953132B2 (ja) * | 2007-09-13 | 2012-06-13 | 日本電気株式会社 | 半導体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
JP2960276B2 (ja) * | 1992-07-30 | 1999-10-06 | 株式会社東芝 | 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法 |
JPH088359A (ja) * | 1994-06-21 | 1996-01-12 | Hitachi Ltd | 半導体集積回路装置 |
US5487218A (en) * | 1994-11-21 | 1996-01-30 | International Business Machines Corporation | Method for making printed circuit boards with selectivity filled plated through holes |
JP3450477B2 (ja) * | 1994-12-20 | 2003-09-22 | 富士通株式会社 | 半導体装置及びその製造方法 |
JPH08330474A (ja) * | 1995-03-31 | 1996-12-13 | Toshiba Corp | 半導体用パッケージ |
US5574630A (en) * | 1995-05-11 | 1996-11-12 | International Business Machines Corporation | Laminated electronic package including a power/ground assembly |
WO1998011605A1 (fr) * | 1995-06-19 | 1998-03-19 | Ibiden Co., Ltd. | Carte de circuit permettant le montage de pieces electroniques |
JP3294740B2 (ja) * | 1995-07-31 | 2002-06-24 | 富士通株式会社 | 半導体装置 |
JP3534501B2 (ja) * | 1995-08-25 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
-
1997
- 1997-08-28 JP JP23192797A patent/JP4190602B2/ja not_active Expired - Lifetime
-
1998
- 1998-05-15 DE DE19821916A patent/DE19821916C2/de not_active Expired - Lifetime
- 1998-05-19 KR KR1019980018023A patent/KR100286746B1/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100708041B1 (ko) * | 2001-07-28 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
Also Published As
Publication number | Publication date |
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JP4190602B2 (ja) | 2008-12-03 |
KR100286746B1 (ko) | 2001-04-16 |
JPH1174417A (ja) | 1999-03-16 |
DE19821916C2 (de) | 2002-01-10 |
DE19821916A1 (de) | 1999-03-11 |
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