KR20060050209A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

Info

Publication number
KR20060050209A
KR20060050209A KR1020050064173A KR20050064173A KR20060050209A KR 20060050209 A KR20060050209 A KR 20060050209A KR 1020050064173 A KR1020050064173 A KR 1020050064173A KR 20050064173 A KR20050064173 A KR 20050064173A KR 20060050209 A KR20060050209 A KR 20060050209A
Authority
KR
South Korea
Prior art keywords
gate
field effect
cross
effect transistor
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020050064173A
Other languages
English (en)
Korean (ko)
Inventor
다이 히사모토
칸 야스이
신이치로 기무라
테쯔야 이시마루
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20060050209A publication Critical patent/KR20060050209A/ko
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
KR1020050064173A 2004-07-29 2005-07-15 반도체장치 및 그 제조방법 Ceased KR20060050209A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004221764A JP2006041354A (ja) 2004-07-29 2004-07-29 半導体装置及びその製造方法
JPJP-P-2004-00221764 2004-07-29

Publications (1)

Publication Number Publication Date
KR20060050209A true KR20060050209A (ko) 2006-05-19

Family

ID=35731149

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050064173A Ceased KR20060050209A (ko) 2004-07-29 2005-07-15 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (2) US7504689B2 (https=)
JP (1) JP2006041354A (https=)
KR (1) KR20060050209A (https=)
CN (1) CN1728401B (https=)
TW (1) TWI360865B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180035129A (ko) * 2016-09-28 2018-04-05 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4601316B2 (ja) * 2004-03-31 2010-12-22 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
JP4659527B2 (ja) * 2005-06-20 2011-03-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5086558B2 (ja) * 2006-04-04 2012-11-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR100762262B1 (ko) * 2006-10-23 2007-10-01 삼성전자주식회사 비휘발성 메모리 소자 및 그 형성방법
WO2008075656A1 (ja) * 2006-12-19 2008-06-26 Nec Corporation 半導体装置
JP2008263034A (ja) * 2007-04-11 2008-10-30 Oki Electric Ind Co Ltd 半導体記憶装置の製造方法
JP2009049097A (ja) * 2007-08-16 2009-03-05 Oki Electric Ind Co Ltd 半導体不揮発性メモリセルとその製造方法、及びその半導体不揮発性メモリセルを有する半導体不揮発性メモリとその製造方法
JP2010182751A (ja) 2009-02-03 2010-08-19 Renesas Electronics Corp 不揮発性半導体記憶装置及びその製造方法
JP5404149B2 (ja) * 2009-04-16 2014-01-29 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP5554973B2 (ja) * 2009-12-01 2014-07-23 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP5214700B2 (ja) * 2010-10-18 2013-06-19 ルネサスエレクトロニクス株式会社 半導体装置
US8598646B2 (en) 2011-01-13 2013-12-03 Spansion Llc Non-volatile FINFET memory array and manufacturing method thereof
JP5951374B2 (ja) * 2012-07-09 2016-07-13 ルネサスエレクトロニクス株式会社 半導体装置
US20140167220A1 (en) 2012-12-14 2014-06-19 Spansion Llc Three dimensional capacitor
US8836006B2 (en) 2012-12-14 2014-09-16 Spansion Llc Integrated circuits with non-volatile memory and methods for manufacture
US9368606B2 (en) 2012-12-14 2016-06-14 Cypress Semiconductor Corporation Memory first process flow and device
US20140167142A1 (en) 2012-12-14 2014-06-19 Spansion Llc Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
US20140167141A1 (en) 2012-12-14 2014-06-19 Spansion Llc Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
US10014380B2 (en) 2012-12-14 2018-07-03 Cypress Semiconductor Corporation Memory first process flow and device
US9209197B2 (en) 2012-12-14 2015-12-08 Cypress Semiconductor Corporation Memory gate landing pad made from dummy features
US9966477B2 (en) 2012-12-14 2018-05-08 Cypress Semiconductor Corporation Charge trapping split gate device and method of fabricating same
US8822289B2 (en) 2012-12-14 2014-09-02 Spansion Llc High voltage gate formation
US8816438B2 (en) 2012-12-14 2014-08-26 Spansion Llc Process charging protection for split gate charge trapping flash
US20140210012A1 (en) 2013-01-31 2014-07-31 Spansion Llc Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions
US9293359B2 (en) * 2013-03-14 2016-03-22 Silicon Storage Technology, Inc. Non-volatile memory cells with enhanced channel region effective width, and method of making same
JP2014232810A (ja) * 2013-05-29 2014-12-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6274826B2 (ja) 2013-11-14 2018-02-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9368644B2 (en) * 2013-12-20 2016-06-14 Cypress Semiconductor Corporation Gate formation memory by planarization
JP6238235B2 (ja) * 2014-06-13 2017-11-29 ルネサスエレクトロニクス株式会社 半導体装置
JP6375181B2 (ja) * 2014-08-28 2018-08-15 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN106158637B (zh) * 2015-03-31 2019-04-26 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN106158638B (zh) * 2015-04-01 2019-03-29 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管及其形成方法
CN105120143B (zh) * 2015-07-28 2019-03-29 深圳市理邦精密仪器股份有限公司 电子阴道镜消除图像光斑的方法及装置
JP6557095B2 (ja) 2015-08-26 2019-08-07 ルネサスエレクトロニクス株式会社 半導体装置
JP2017045947A (ja) 2015-08-28 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6578172B2 (ja) 2015-09-18 2019-09-18 ルネサスエレクトロニクス株式会社 半導体装置
JP5982055B1 (ja) * 2015-12-18 2016-08-31 株式会社フローディア メモリセル、不揮発性半導体記憶装置、および不揮発性半導体記憶装置の製造方法
JP6594198B2 (ja) 2015-12-28 2019-10-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6718248B2 (ja) 2016-02-17 2020-07-08 ルネサスエレクトロニクス株式会社 半導体装置
JP6620034B2 (ja) 2016-02-24 2019-12-11 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP6591311B2 (ja) 2016-02-24 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6629142B2 (ja) 2016-06-03 2020-01-15 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6652451B2 (ja) 2016-06-14 2020-02-26 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6750994B2 (ja) * 2016-09-29 2020-09-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6744185B2 (ja) * 2016-09-30 2020-08-19 ルネサスエレクトロニクス株式会社 半導体装置
JP2018056453A (ja) 2016-09-30 2018-04-05 ルネサスエレクトロニクス株式会社 半導体装置
JP6778607B2 (ja) 2016-12-22 2020-11-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2018107317A (ja) * 2016-12-27 2018-07-05 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
CN106981422B (zh) * 2017-03-01 2020-03-24 中国科学院微电子研究所 一种垂直tfet及其制造方法
JP6885787B2 (ja) 2017-05-26 2021-06-16 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP6783710B2 (ja) * 2017-06-22 2020-11-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
JP2019050314A (ja) 2017-09-11 2019-03-28 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2019054213A (ja) 2017-09-19 2019-04-04 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2019117913A (ja) 2017-12-27 2019-07-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6998267B2 (ja) 2018-05-08 2022-01-18 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP7053388B2 (ja) 2018-06-28 2022-04-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP7117223B2 (ja) 2018-11-08 2022-08-12 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP7200054B2 (ja) 2019-06-24 2023-01-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2021082656A (ja) 2019-11-15 2021-05-27 ルネサスエレクトロニクス株式会社 半導体装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
JP3228996B2 (ja) * 1992-03-30 2001-11-12 株式会社東芝 不揮発性半導体記憶装置
US5604146A (en) * 1996-06-10 1997-02-18 Vanguard International Semiconductor Corporation Method to fabricate a semiconductor memory device having an E-shaped storage node
JP3710880B2 (ja) 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
US5969383A (en) 1997-06-16 1999-10-19 Motorola, Inc. Split-gate memory device and method for accessing the same
US6383861B1 (en) * 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
JP3973819B2 (ja) * 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
JP2001036048A (ja) * 1999-07-16 2001-02-09 Denso Corp 半導体メモリ及びその製造方法
JP4068781B2 (ja) * 2000-02-28 2008-03-26 株式会社ルネサステクノロジ 半導体集積回路装置および半導体集積回路装置の製造方法
EP1172856A1 (en) * 2000-07-03 2002-01-16 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
JP4904631B2 (ja) * 2000-10-27 2012-03-28 ソニー株式会社 不揮発性半導体記憶装置およびその製造方法
KR100338783B1 (en) * 2000-10-28 2002-06-01 Samsung Electronics Co Ltd Semiconductor device having expanded effective width of active region and fabricating method thereof
DE10241171A1 (de) * 2002-09-05 2004-03-18 Infineon Technologies Ag Wort- und Bitleitungsanordnung für einen FINFET-Halbleiterspeicher
JP2004186452A (ja) 2002-12-04 2004-07-02 Renesas Technology Corp 不揮発性半導体記憶装置およびその製造方法
DE10260334B4 (de) * 2002-12-20 2007-07-12 Infineon Technologies Ag Fin-Feldeffektransitor-Speicherzelle, Fin-Feldeffekttransistor-Speicherzellen-Anordnung und Verfahren zum Herstellen einer Fin-Feldeffektransistor-Speicherzelle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180035129A (ko) * 2016-09-28 2018-04-05 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
US7504689B2 (en) 2009-03-17
JP2006041354A (ja) 2006-02-09
CN1728401B (zh) 2011-05-25
CN1728401A (zh) 2006-02-01
US20060022260A1 (en) 2006-02-02
TW200625553A (en) 2006-07-16
US7847343B2 (en) 2010-12-07
TWI360865B (en) 2012-03-21
US20090152619A1 (en) 2009-06-18

Similar Documents

Publication Publication Date Title
KR20060050209A (ko) 반도체장치 및 그 제조방법
JP4521597B2 (ja) 半導体記憶装置およびその製造方法
KR100395762B1 (ko) 비휘발성 메모리 소자 및 그 제조방법
US7259422B1 (en) Nonvolatile semiconductor memory device and its fabrication method
KR100634266B1 (ko) 불휘발성 메모리 장치, 이를 제조하는 방법 및 이를동작시키는 방법
US6903408B2 (en) Flash memory cell with high programming efficiency by coupling from floating gate to sidewall
US20070190724A1 (en) Semiconductor device
JP5116987B2 (ja) 集積半導体不揮発性記憶装置
JP2003332469A (ja) 不揮発性半導体記憶装置及びその製造方法
US6620693B2 (en) Non-volatile memory and fabrication thereof
US8951881B2 (en) Methods of fabricating nonvolatile memory devices including voids between active regions and related devices
US9287277B2 (en) Semiconductor device and fabricating method thereof
CN114497073A (zh) 半导体器件及其制造方法
KR100608376B1 (ko) 세 가지 상태를 갖는 비휘발성 메모리 및 그 제조방법
JP3653373B2 (ja) 半導体記憶装置及びその書き込み方法
WO2006035503A1 (ja) 半導体装置および半導体装置の製造方法
JP5214700B2 (ja) 半導体装置
CN101009288A (zh) 半导体器件
JP2004047614A (ja) トランジスタとそれを用いた半導体メモリ、およびトランジスタの製造方法
US7773416B2 (en) Single poly, multi-bit non-volatile memory device and methods for operating the same
JP2013077841A (ja) 半導体装置

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

N231 Notification of change of applicant
PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E601 Decision to refuse application
PE0601 Decision on rejection of patent

St.27 status event code: N-2-6-B10-B15-exm-PE0601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000